diff --git a/.github/workflows/release-firmware.yml b/.github/workflows/release-firmware.yml
index 4ec12692..ec398f82 100644
--- a/.github/workflows/release-firmware.yml
+++ b/.github/workflows/release-firmware.yml
@@ -49,6 +49,7 @@ on:
       - 'scripts/pin_lvgl_ref.sh'
       - 'scripts/stage_firmware_page.py'
       - 'scripts/ci_scope.py'
+      - 'build_mp.py'
       - 'modules.lock'
       - 'deps.lock'
       - 'tests/test_release_firmware.py'
diff --git a/scripts/ci_scope.py b/scripts/ci_scope.py
index 3c3a2aa0..234680be 100644
--- a/scripts/ci_scope.py
+++ b/scripts/ci_scope.py
@@ -95,6 +95,12 @@ def cp_reach(path):
 FIRMWARE_WORKFLOW = ".github/workflows/release-firmware.yml"
 # The pins every build fetches: a change to one can break any board.
 FIRMWARE_PINS = ("modules.lock", "deps.lock")
+# build_mp.py builds every board, and the btclassic, h264enc and circuitpython
+# workflows already build esp32, rp2 and CircuitPython boards through it on a
+# change. Nothing else builds an stm32 image, whose layout build_mp.py checks
+# (the GIGA's M4 pad), so a change to it builds those cells here.
+BUILD_MP = "build_mp.py"
+BUILD_MP_CELLS = ("mp-giga-shield",)
 
 
 def cells_of(source):
@@ -117,18 +123,19 @@ def firmware_scope(files, show_base, show_head):
     The workflow, or anything in release_firmware.py besides CELLS, builds the
     whole set. A change to CELLS builds the cells whose row changed, and the
     whole set when a cell is added or removed. A pin in modules.lock or
-    deps.lock builds the whole set too. Everything else the workflow watches is
-    read by the unit tests its gate job runs and by no build."""
+    deps.lock builds the whole set too, and build_mp.py the cells nothing else
+    builds through it. Everything else the workflow watches is read by the unit
+    tests its gate job runs and by no build."""
     if FIRMWARE_WORKFLOW in files or any(p in files for p in FIRMWARE_PINS):
         return True, True, []
-    if FIRMWARE not in files:
-        return False, False, []
-    old, old_rest = cells_of(show_base())
-    new, new_rest = cells_of(show_head())
-    if old_rest != new_rest or set(old) != set(new):
-        return True, True, []
-    changed = sorted(i for i in new if old[i] != new[i] and not new[i].get("optional"))
-    return bool(changed), False, changed
+    changed = set(BUILD_MP_CELLS) if BUILD_MP in files else set()
+    if FIRMWARE in files:
+        old, old_rest = cells_of(show_base())
+        new, new_rest = cells_of(show_head())
+        if old_rest != new_rest or set(old) != set(new):
+            return True, True, []
+        changed |= {i for i in new if old[i] != new[i] and not new[i].get("optional")}
+    return bool(changed), False, sorted(changed)
 
 
 # ---- git -------------------------------------------------------------------
diff --git a/tests/test_ci_scope.py b/tests/test_ci_scope.py
index db87ff81..7bf75d34 100644
--- a/tests/test_ci_scope.py
+++ b/tests/test_ci_scope.py
@@ -77,6 +77,12 @@ def test_a_pin_builds_the_whole_set(self):
         self.assertEqual(self.scope(["modules.lock"]), (True, True, []))
         self.assertEqual(self.scope(["deps.lock"]), (True, True, []))
 
+    def test_build_mp_builds_the_stm32_cells(self):
+        self.assertEqual(self.scope(["build_mp.py"]), (True, False, ["mp-giga-shield"]))
+        head = with_cell(SOURCE, "mp-s3-lcd43", 'flash="8MB"', 'flash="16MB"')
+        self.assertEqual(self.scope(["build_mp.py", ci_scope.FIRMWARE], head),
+                         (True, False, ["mp-giga-shield", "mp-s3-lcd43"]))
+
     def test_one_cells_row_builds_that_cell(self):
         head = with_cell(SOURCE, "mp-s3-lcd43", 'flash="8MB"', 'flash="16MB"')
         self.assertEqual(self.scope([ci_scope.FIRMWARE], head), (True, False, ["mp-s3-lcd43"]))