Add VCS openroad flow

Author: micprog

Bender.yml

@@ -35,7 +35,7 @@ sources:
   # add your design files containing anything but modules (packages) here
 
     # RTL
-  - target: not(netlist_yosys)
+  - target: not(any(netlist_yosys, netlist_openroad))
     files:
       # Level 1
       - rtl/core_wrap.sv
@@ -49,16 +49,21 @@ sources:
       # Level 3
       - rtl/croc_soc.sv
 
-  - target: not(fpga)
+  - target: not(any(fpga, netlist_yosys, netlist_openroad))
     files:
       # Level 0
       - rtl/croc_chip.sv
 
-  # netlist for simulation
+  # yosys netlist for simulation
   - target: netlist_yosys
     files:
       - yosys/out/croc_chip_yosys_debug.v
 
+  # openroad netlist for simulation
+  - target: netlist_openroad
+    files:
+      - openroad/out/croc.v
+
   - target: any(simulation, verilator)
     files:
       - rtl/tb_croc_soc.sv
@@ -187,4 +192,4 @@ vendor_package:
       - { from: 'rtl/',                                         to: '',                      patch_dir: 'rtl/' }
       - { from: 'README.md',                                    to: 'README.md',             patch_dir: '' }
       - { from: 'doc/03_reference/images/blockdiagram.svg',     to: 'blockdiagram.svg',      patch_dir: '' }
-      - { from: 'vendor/lowrisc_ip/ip/prim/rtl/',               to: 'include/lowrisc_prim/', patch_dir: 'lowrisc_prim/' }
+      - { from: 'vendor/lowrisc_ip/ip/prim/rtl/',               to: 'include/lowrisc_prim/', patch_dir: 'lowrisc_prim/' }

Makefile

@@ -117,27 +117,39 @@ vcs/compile_rtl.sh: Bender.lock Bender.yml
 	$(BENDER) script vcs -t rtl -t vcs -t simulation -t verilator -DSYNTHESIS -DSIMULATION --vlog-arg="$(VCS_SCRIPT_ARGS)" --vlogan-bin="$(VLOGAN)" > $@
 	chmod +x $@
 
-vcs/compile_netlist.sh: Bender.lock Bender.yml
+vcs/compile_netlist_yosys.sh: Bender.lock Bender.yml
 	$(BENDER) script vcs -t ihp13 -t vcs -t simulation -t verilator -t netlist_yosys -DSYNTHESIS -DSIMULATION --vlog-arg="$(VCS_SCRIPT_ARGS)" --vlogan-bin="$(VLOGAN)" > $@
 	cat vcs/compile_tech.sh >> $@
 	chmod +x $@
 
+vcs/compile_netlist_openroad.sh: Bender.lock Bender.yml
+	$(BENDER) script vcs -t ihp13 -t vcs -t simulation -t verilator -t netlist_openroad -DSYNTHESIS -DSIMULATION --vlog-arg="$(VCS_SCRIPT_ARGS)" --vlogan-bin="$(VLOGAN)" > $@
+	cat vcs/compile_tech.sh >> $@
+	chmod +x $@
+
 vcs/tb_croc_soc.sim: vcs/compile_rtl.sh
 	cd vcs; ./compile_rtl.sh
 	cd vcs; $(VCS) $(VCS_COMPILE_ARGS) -o tb_croc_soc.sim tb_croc_soc
 
-vcs/tb_croc_soc_yosys.sim: vcs/compile_netlist.sh yosys/out/croc_chip_yosys_debug.v
-	cd vcs; ./compile_netlist.sh
+vcs/tb_croc_soc_yosys.sim: vcs/compile_netlist_yosys.sh yosys/out/croc_chip_yosys_debug.v
+	cd vcs; ./compile_netlist_yosys.sh
 	cd vcs; $(VCS) $(VCS_COMPILE_ARGS) -o tb_croc_soc_yosys.sim tb_croc_soc
 
+vcs/tb_croc_soc_openroad.sim: vcs/compile_netlist_openroad.sh openroad/out/croc.v
+	cd vcs; ./compile_netlist_openroad.sh
+	cd vcs; $(VCS) $(VCS_COMPILE_ARGS) -o tb_croc_soc_openroad.sim tb_croc_soc
+
 ## Simulate RTL using VCS
 vcs: vcs/tb_croc_soc.sim $(SW_HEX)
 	cd vcs; ./tb_croc_soc.sim +fsdb+all=on +binary="$(realpath $(SW_HEX))" -l transcript.log
 
 vcs-yosys: vcs/tb_croc_soc_yosys.sim $(SW_HEX)
 	cd vcs; ./tb_croc_soc_yosys.sim +fsdb+all=on +binary="$(realpath $(SW_HEX))" -l transcript.log
 
-.PHONY: verilator vsim vsim-yosys vcs
+vcs-openroad: vcs/tb_croc_soc_openroad.sim $(SW_HEX)
+	cd vcs; ./tb_croc_soc_openroad.sim +fsdb+all=on +binary="$(realpath $(SW_HEX))" -l transcript.log
+
+.PHONY: verilator vsim vsim-yosys vcs vcs-yosys vcs-openroad
 
 
 ####################

vcs/.gitignore

@@ -6,7 +6,7 @@ csrc
 ucli.key
 croc.fst
 compile_rtl.sh
-compile_netlist.sh
+compile_netlist*
 compile.log
 novas*
 transcript.log