From 963b685b35db2137ff52cd5edcd6952c537df276 Mon Sep 17 00:00:00 2001 From: Frederic Pillon Date: Mon, 2 Nov 2026 16:07:46 +0100 Subject: [PATCH 1/2] system(f3) update STM32F3xx HAL Drivers to v1.5.9 Included in STM32CubeF3 FW v1.12.0 Signed-off-by: Frederic Pillon --- .../Inc/Legacy/stm32_hal_legacy.h | 145 +- .../Inc/stm32f3xx_hal_can.h | 8 +- .../Inc/stm32f3xx_hal_crc.h | 4 +- .../Inc/stm32f3xx_hal_gpio.h | 42 +- .../Inc/stm32f3xx_hal_gpio_ex.h | 32 +- .../Inc/stm32f3xx_hal_hrtim.h | 1594 +++++++------ .../Inc/stm32f3xx_hal_i2s.h | 4 +- .../Inc/stm32f3xx_hal_nand.h | 2 +- .../Inc/stm32f3xx_hal_nor.h | 7 + .../Inc/stm32f3xx_hal_pccard.h | 13 +- .../Inc/stm32f3xx_hal_pcd.h | 24 +- .../Inc/stm32f3xx_hal_pcd_ex.h | 1 - .../Inc/stm32f3xx_hal_rcc.h | 4 +- .../Inc/stm32f3xx_hal_smartcard.h | 6 +- .../Inc/stm32f3xx_hal_spi.h | 46 +- .../Inc/stm32f3xx_hal_tim.h | 67 +- .../Inc/stm32f3xx_hal_uart.h | 2 +- .../Inc/stm32f3xx_hal_usart.h | 12 +- .../Inc/stm32f3xx_hal_wwdg.h | 2 +- .../Inc/stm32f3xx_ll_adc.h | 4 +- .../Inc/stm32f3xx_ll_cortex.h | 2 +- .../Inc/stm32f3xx_ll_fmc.h | 104 +- .../Inc/stm32f3xx_ll_gpio.h | 2 +- .../Inc/stm32f3xx_ll_hrtim.h | 766 +++--- .../Inc/stm32f3xx_ll_rtc.h | 6 +- .../Inc/stm32f3xx_ll_spi.h | 167 +- .../Inc/stm32f3xx_ll_tim.h | 12 +- .../Inc/stm32f3xx_ll_usb.h | 11 +- .../Drivers/STM32F3xx_HAL_Driver/LICENSE.md | 2 +- system/Drivers/STM32F3xx_HAL_Driver/README.md | 4 +- .../STM32F3xx_HAL_Driver/Release_Notes.html | 124 +- .../STM32F3xx_HAL_Driver/SW_Security_Level.md | 47 + .../STM32F3xx_HAL_Driver/Src/stm32f3xx_hal.c | 4 +- .../Src/stm32f3xx_hal_adc_ex.c | 35 +- .../Src/stm32f3xx_hal_can.c | 11 +- .../Src/stm32f3xx_hal_crc.c | 30 +- .../Src/stm32f3xx_hal_dac_ex.c | 6 +- .../Src/stm32f3xx_hal_flash.c | 2 +- .../Src/stm32f3xx_hal_flash_ex.c | 22 +- .../Src/stm32f3xx_hal_gpio.c | 76 +- .../Src/stm32f3xx_hal_hrtim.c | 2117 +++++++++-------- .../Src/stm32f3xx_hal_i2c.c | 89 +- .../Src/stm32f3xx_hal_i2s.c | 4 +- .../Src/stm32f3xx_hal_i2s_ex.c | 23 +- .../Src/stm32f3xx_hal_nand.c | 274 ++- .../Src/stm32f3xx_hal_nor.c | 223 +- .../Src/stm32f3xx_hal_pccard.c | 49 +- .../Src/stm32f3xx_hal_pcd.c | 159 +- .../Src/stm32f3xx_hal_pcd_ex.c | 6 +- .../Src/stm32f3xx_hal_rcc.c | 4 +- .../Src/stm32f3xx_hal_rtc.c | 15 +- .../Src/stm32f3xx_hal_rtc_ex.c | 16 +- .../Src/stm32f3xx_hal_smartcard.c | 16 +- .../Src/stm32f3xx_hal_smbus.c | 55 +- .../Src/stm32f3xx_hal_spi.c | 470 ++-- .../Src/stm32f3xx_hal_sram.c | 3 + .../Src/stm32f3xx_hal_tim.c | 110 +- .../Src/stm32f3xx_hal_tim_ex.c | 12 +- .../Src/stm32f3xx_hal_timebase_tim_template.c | 15 + .../Src/stm32f3xx_hal_uart.c | 215 +- .../Src/stm32f3xx_hal_uart_ex.c | 47 +- .../Src/stm32f3xx_hal_wwdg.c | 10 +- .../Src/stm32f3xx_ll_exti.c | 5 + .../Src/stm32f3xx_ll_fmc.c | 88 +- .../Src/stm32f3xx_ll_gpio.c | 8 +- .../Src/stm32f3xx_ll_hrtim.c | 22 +- .../Src/stm32f3xx_ll_spi.c | 11 +- .../Src/stm32f3xx_ll_tim.c | 4 +- .../Src/stm32f3xx_ll_usb.c | 90 +- .../Drivers/STM32YYxx_HAL_Driver_version.md | 2 +- 70 files changed, 4035 insertions(+), 3579 deletions(-) create mode 100644 system/Drivers/STM32F3xx_HAL_Driver/SW_Security_Level.md diff --git a/system/Drivers/STM32F3xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h b/system/Drivers/STM32F3xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h index 62f7a7d66b..0cb12fd06f 100644 --- a/system/Drivers/STM32F3xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h +++ b/system/Drivers/STM32F3xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h @@ -361,7 +361,9 @@ extern "C" { #if defined(STM32L4R5xx) || defined(STM32L4R9xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || \ defined(STM32L4S7xx) || defined(STM32L4S9xx) #define DMA_REQUEST_DCMI_PSSI DMA_REQUEST_DCMI -#endif +#elif defined(STM32L4P5xx) || defined(STM32L4Q5xx) +#define DMA_REQUEST_PSSI DMA_REQUEST_DCMI_PSSI +#endif /* STM32L4R5xx || STM32L4R9xx || STM32L4R9xx || STM32L4S5xx || STM32L4S7xx || STM32L4S9xx */ #endif /* STM32L4 */ @@ -472,7 +474,9 @@ extern "C" { #define TYPEPROGRAMDATA_FASTBYTE FLASH_TYPEPROGRAMDATA_FASTBYTE #define TYPEPROGRAMDATA_FASTHALFWORD FLASH_TYPEPROGRAMDATA_FASTHALFWORD #define TYPEPROGRAMDATA_FASTWORD FLASH_TYPEPROGRAMDATA_FASTWORD +#if !defined(STM32F2) && !defined(STM32F4) && !defined(STM32F7) && !defined(STM32H7) && !defined(STM32H5) #define PAGESIZE FLASH_PAGE_SIZE +#endif /* STM32F2 && STM32F4 && STM32F7 && STM32H7 && STM32H5 */ #define TYPEPROGRAM_FASTBYTE FLASH_TYPEPROGRAM_BYTE #define TYPEPROGRAM_FASTHALFWORD FLASH_TYPEPROGRAM_HALFWORD #define TYPEPROGRAM_FASTWORD FLASH_TYPEPROGRAM_WORD @@ -536,6 +540,10 @@ extern "C" { #define FLASH_FLAG_WDW FLASH_FLAG_WBNE #define OB_WRP_SECTOR_All OB_WRP_SECTOR_ALL #endif /* STM32H7 */ +#if defined(STM32H7RS) +#define FLASH_OPTKEY1 FLASH_OPT_KEY1 +#define FLASH_OPTKEY2 FLASH_OPT_KEY2 +#endif /* STM32H7RS */ #if defined(STM32U5) #define OB_USER_nRST_STOP OB_USER_NRST_STOP #define OB_USER_nRST_STDBY OB_USER_NRST_STDBY @@ -558,6 +566,9 @@ extern "C" { #define OB_nBOOT0_RESET OB_NBOOT0_RESET #define OB_nBOOT0_SET OB_NBOOT0_SET #endif /* STM32U0 */ +#if defined(STM32H5) +#define FLASH_ECC_AREA_EDATA FLASH_ECC_AREA_EDATA_BANK1 +#endif /* STM32H5 */ /** * @} @@ -601,6 +612,15 @@ extern "C" { #define HAL_SYSCFG_DisableIOAnalogSwitchVDD HAL_SYSCFG_DisableIOSwitchVDD #endif /* STM32G4 */ +#if defined(STM32U5) + +#define HAL_SYSCFG_EnableIOAnalogSwitchBooster HAL_SYSCFG_EnableIOAnalogBooster +#define HAL_SYSCFG_DisableIOAnalogSwitchBooster HAL_SYSCFG_DisableIOAnalogBooster +#define HAL_SYSCFG_EnableIOAnalogSwitchVoltageSelection HAL_SYSCFG_EnableIOAnalogVoltageSelection +#define HAL_SYSCFG_DisableIOAnalogSwitchVoltageSelection HAL_SYSCFG_DisableIOAnalogVoltageSelection + +#endif /* STM32U5 */ + #if defined(STM32H5) #define SYSCFG_IT_FPU_IOC SBS_IT_FPU_IOC #define SYSCFG_IT_FPU_DZC SBS_IT_FPU_DZC @@ -806,6 +826,21 @@ extern "C" { #define GPIO_AF0_S2DSTOP GPIO_AF0_SRDSTOP #define GPIO_AF11_LPGPIO GPIO_AF11_LPGPIO1 #endif /* STM32U5 */ + +#if defined(STM32WBA) +#define GPIO_AF11_RF_ANTSW0 GPIO_AF11_RF +#define GPIO_AF11_RF_ANTSW1 GPIO_AF11_RF +#define GPIO_AF11_RF_ANTSW2 GPIO_AF11_RF +#define GPIO_AF11_RF_IO1 GPIO_AF11_RF +#define GPIO_AF11_RF_IO2 GPIO_AF11_RF +#define GPIO_AF11_RF_IO3 GPIO_AF11_RF +#define GPIO_AF11_RF_IO4 GPIO_AF11_RF +#define GPIO_AF11_RF_IO5 GPIO_AF11_RF +#define GPIO_AF11_RF_IO6 GPIO_AF11_RF +#define GPIO_AF11_RF_IO7 GPIO_AF11_RF +#define GPIO_AF11_RF_IO8 GPIO_AF11_RF +#define GPIO_AF11_RF_IO9 GPIO_AF11_RF +#endif /* STM32WBA */ /** * @} */ @@ -860,6 +895,10 @@ extern "C" { #define __HAL_HRTIM_SetCompare __HAL_HRTIM_SETCOMPARE #define __HAL_HRTIM_GetCompare __HAL_HRTIM_GETCOMPARE +#if defined(STM32F3) || defined(STM32G4) || defined(STM32H7) +#define HRTIMInterruptResquests HRTIMInterruptRequests +#endif /* STM32F3 || STM32G4 || STM32H7 */ + #if defined(STM32G4) #define HAL_HRTIM_ExternalEventCounterConfig HAL_HRTIM_ExtEventCounterConfig #define HAL_HRTIM_ExternalEventCounterEnable HAL_HRTIM_ExtEventCounterEnable @@ -997,8 +1036,8 @@ extern "C" { #define HRTIM_CALIBRATIONRATE_910 (HRTIM_DLLCR_CALRTE_0) #define HRTIM_CALIBRATIONRATE_114 (HRTIM_DLLCR_CALRTE_1) #define HRTIM_CALIBRATIONRATE_14 (HRTIM_DLLCR_CALRTE_1 | HRTIM_DLLCR_CALRTE_0) - #endif /* STM32F3 */ + /** * @} */ @@ -1249,10 +1288,10 @@ extern "C" { #define RTC_TAMPERPIN_PA0 RTC_TAMPERPIN_POS1 #define RTC_TAMPERPIN_PI8 RTC_TAMPERPIN_POS1 -#if defined(STM32H5) || defined(STM32H7RS) +#if defined(STM32H5) || defined(STM32H7RS) || defined(STM32N6) #define TAMP_SECRETDEVICE_ERASE_NONE TAMP_DEVICESECRETS_ERASE_NONE #define TAMP_SECRETDEVICE_ERASE_BKP_SRAM TAMP_DEVICESECRETS_ERASE_BKPSRAM -#endif /* STM32H5 || STM32H7RS */ +#endif /* STM32H5 || STM32H7RS || STM32N6 */ #if defined(STM32WBA) #define TAMP_SECRETDEVICE_ERASE_NONE TAMP_DEVICESECRETS_ERASE_NONE @@ -1264,27 +1303,27 @@ extern "C" { #define TAMP_SECRETDEVICE_ERASE_ALL TAMP_DEVICESECRETS_ERASE_ALL #endif /* STM32WBA */ -#if defined(STM32H5) || defined(STM32WBA) || defined(STM32H7RS) +#if defined(STM32H5) || defined(STM32WBA) || defined(STM32H7RS) || defined(STM32N6) #define TAMP_SECRETDEVICE_ERASE_DISABLE TAMP_DEVICESECRETS_ERASE_NONE #define TAMP_SECRETDEVICE_ERASE_ENABLE TAMP_SECRETDEVICE_ERASE_ALL -#endif /* STM32H5 || STM32WBA || STM32H7RS */ +#endif /* STM32H5 || STM32WBA || STM32H7RS || STM32N6 */ -#if defined(STM32F7) +#if defined(STM32F7) || defined(STM32WB) #define RTC_TAMPCR_TAMPXE RTC_TAMPER_ENABLE_BITS_MASK #define RTC_TAMPCR_TAMPXIE RTC_TAMPER_IT_ENABLE_BITS_MASK -#endif /* STM32F7 */ +#endif /* STM32F7 || STM32WB */ #if defined(STM32H7) #define RTC_TAMPCR_TAMPXE RTC_TAMPER_X #define RTC_TAMPCR_TAMPXIE RTC_TAMPER_X_INTERRUPT #endif /* STM32H7 */ -#if defined(STM32F7) || defined(STM32H7) || defined(STM32L0) +#if defined(STM32F7) || defined(STM32H7) || defined(STM32L0) || defined(STM32WB) #define RTC_TAMPER1_INTERRUPT RTC_IT_TAMP1 #define RTC_TAMPER2_INTERRUPT RTC_IT_TAMP2 #define RTC_TAMPER3_INTERRUPT RTC_IT_TAMP3 #define RTC_ALL_TAMPER_INTERRUPT RTC_IT_TAMP -#endif /* STM32F7 || STM32H7 || STM32L0 */ +#endif /* STM32F7 || STM32H7 || STM32L0 || STM32WB */ /** * @} @@ -1451,7 +1490,7 @@ extern "C" { #define TIM_TIM3_TI1_COMP1COMP2_OUT TIM_TIM3_TI1_COMP1_COMP2 #endif -#if defined(STM32U5) +#if defined(STM32U5) || defined(STM32MP2) #define OCREF_CLEAR_SELECT_Pos OCREF_CLEAR_SELECT_POS #define OCREF_CLEAR_SELECT_Msk OCREF_CLEAR_SELECT_MSK #endif @@ -1817,7 +1856,7 @@ extern "C" { #define HAL_FMPI2CEx_AnalogFilter_Config HAL_FMPI2CEx_ConfigAnalogFilter #define HAL_FMPI2CEx_DigitalFilter_Config HAL_FMPI2CEx_ConfigDigitalFilter -#define HAL_I2CFastModePlusConfig(SYSCFG_I2CFastModePlus, cmd) ((cmd == ENABLE)? \ +#define HAL_I2CFastModePlusConfig(SYSCFG_I2CFastModePlus, cmd) (((cmd) == ENABLE)? \ HAL_I2CEx_EnableFastModePlus(SYSCFG_I2CFastModePlus): \ HAL_I2CEx_DisableFastModePlus(SYSCFG_I2CFastModePlus)) @@ -1878,7 +1917,11 @@ extern "C" { #define HAL_PWREx_DisableSDADCAnalog HAL_PWREx_DisableSDADC #define HAL_PWREx_EnableSDADCAnalog HAL_PWREx_EnableSDADC #define HAL_PWREx_PVMConfig HAL_PWREx_ConfigPVM - +#if defined(STM32G0C1xx) || defined(STM32G0B1xx) +#define PWR_PVM_USB PWR_PVM_ENABLE +#define PWR_FLAG_PVMOUSB PWR_FLAG_PVMOVDDIO2 +#define PWR_FLAG_PVMO_USB PWR_FLAG_PVMO_VDDIO2 +#endif /* STM32G0C1xx || STM32G0B1xx */ #define PWR_MODE_NORMAL PWR_PVD_MODE_NORMAL #define PWR_MODE_IT_RISING PWR_PVD_MODE_IT_RISING #define PWR_MODE_IT_FALLING PWR_PVD_MODE_IT_FALLING @@ -1991,6 +2034,9 @@ extern "C" { #define PWR_ALL_RAM_RUN_RETENTION_MASK PWR_ALL_RAM_RUN_MASK #endif +#if defined (STM32H7RS) +#define PWR_SMPS_1V8_SUPPLIES_EXT_AND_LDO PWR_SMPS_1V8_SUPPLIES_EXT_VDD_SUPPLIES_LDO +#endif /** * @} @@ -1999,12 +2045,12 @@ extern "C" { /** @defgroup HAL_RTC_Aliased_Functions HAL RTC Aliased Functions maintained for legacy purpose * @{ */ -#if defined(STM32H5) || defined(STM32WBA) || defined(STM32H7RS) +#if defined(STM32H5) || defined(STM32WBA) || defined(STM32H7RS) || defined(STM32N6) #define HAL_RTCEx_SetBoothardwareKey HAL_RTCEx_LockBootHardwareKey #define HAL_RTCEx_BKUPBlock_Enable HAL_RTCEx_BKUPBlock #define HAL_RTCEx_BKUPBlock_Disable HAL_RTCEx_BKUPUnblock #define HAL_RTCEx_Erase_SecretDev_Conf HAL_RTCEx_ConfigEraseDeviceSecrets -#endif /* STM32H5 || STM32WBA || STM32H7RS */ +#endif /* STM32H5 || STM32WBA || STM32H7RS || STM32N6 */ /** * @} @@ -2112,6 +2158,20 @@ extern "C" { #define UFB_MODE_BitNumber UFB_MODE_BIT_NUMBER #define CMP_PD_BitNumber CMP_PD_BIT_NUMBER +#if defined(STM32H7RS) || defined(STM32N6) +#define FMC_SWAPBMAP_DISABLE FMC_SWAPBANK_MODE0 +#define FMC_SWAPBMAP_SDRAM_SRAM FMC_SWAPBANK_MODE1 +#define HAL_SetFMCMemorySwappingConfig HAL_FMC_SetBankSwapConfig +#define HAL_GetFMCMemorySwappingConfig HAL_FMC_GetBankSwapConfig +#endif /* STM32H7RS || STM32N6 */ + +#if defined(STM32N6) +/* alias CMSIS */ +#define CSI_PCR_PWRDOWN_Pos CSI_PCR_NPWRDOWN_Pos +#define CSI_PCR_PWRDOWN_Msk CSI_PCR_NPWRDOWN_Msk +#define CSI_PCR_PWRDOWN CSI_PCR_NPWRDOWN +#endif /* STM32N6 */ + /** * @} */ @@ -2197,6 +2257,15 @@ extern "C" { #define __HAL_ADC_CFGR1_SCANDIR ADC_CFGR1_SCANDIR #define __HAL_ADC_CFGR1_DMACONTREQ ADC_CFGR1_DMACONTREQ +#if defined (STM32L031xx) || defined (STM32L041xx) || \ + defined (STM32L051xx) || defined (STM32L052xx) || defined (STM32L053xx) || \ + defined (STM32L062xx) || defined (STM32L063xx) || \ + defined (STM32L071xx) || defined (STM32L072xx) || defined (STM32L073xx) || \ + defined (STM32L081xx) || defined (STM32L082xx) || defined (STM32L083xx) || \ + defined (STM32L010x6) || defined (STM32L010x8) || defined (STM32L010xB) +#define ADC_EXTERNALTRIGCONV_T21_TRGO (ADC_EXTERNALTRIGCONV_T22_TRGO) +#endif + /** * @} */ @@ -3638,7 +3707,11 @@ extern "C" { #define RCC_PLLDIV_4 RCC_PLL_DIV4 #define IS_RCC_MCOSOURCE IS_RCC_MCO1SOURCE +#define RCC_MCOSOURCE_SYSCLK RCC_MCO1SOURCE_SYSCLK +#define RCC_MCOSOURCE_HSE RCC_MCO1SOURCE_HSE #define __HAL_RCC_MCO_CONFIG __HAL_RCC_MCO1_CONFIG + + #define RCC_MCO_NODIV RCC_MCODIV_1 #define RCC_MCO_DIV1 RCC_MCODIV_1 #define RCC_MCO_DIV2 RCC_MCODIV_2 @@ -3651,11 +3724,9 @@ extern "C" { #define RCC_MCOSOURCE_NONE RCC_MCO1SOURCE_NOCLOCK #define RCC_MCOSOURCE_LSI RCC_MCO1SOURCE_LSI #define RCC_MCOSOURCE_LSE RCC_MCO1SOURCE_LSE -#define RCC_MCOSOURCE_SYSCLK RCC_MCO1SOURCE_SYSCLK #define RCC_MCOSOURCE_HSI RCC_MCO1SOURCE_HSI #define RCC_MCOSOURCE_HSI14 RCC_MCO1SOURCE_HSI14 #define RCC_MCOSOURCE_HSI48 RCC_MCO1SOURCE_HSI48 -#define RCC_MCOSOURCE_HSE RCC_MCO1SOURCE_HSE #define RCC_MCOSOURCE_PLLCLK_DIV1 RCC_MCO1SOURCE_PLLCLK #define RCC_MCOSOURCE_PLLCLK_NODIV RCC_MCO1SOURCE_PLLCLK #define RCC_MCOSOURCE_PLLCLK_DIV2 RCC_MCO1SOURCE_PLLCLK_DIV2 @@ -3664,8 +3735,14 @@ extern "C" { #define RCC_SYSCLKSOURCE_STATUS_PLLR RCC_SYSCLKSOURCE_STATUS_PLLCLK #endif +#if defined(STM32C0) +#define RCC_LSEDRIVE_LOW RCC_LSEDRIVE_MEDIUMHIGH +#define RCC_LSEDRIVE_MEDIUMLOW RCC_LSEDRIVE_MEDIUMHIGH +#endif + #if defined(STM32L4) || defined(STM32WB) || defined(STM32G0) || defined(STM32G4) || defined(STM32L5) || \ - defined(STM32WL) || defined(STM32C0) || defined(STM32H7RS) || defined(STM32U0) + defined(STM32WL) || defined(STM32C0) || defined(STM32N6) || defined(STM32H7RS) || \ + defined(STM32U0) #define RCC_RTCCLKSOURCE_NO_CLK RCC_RTCCLKSOURCE_NONE #else #define RCC_RTCCLKSOURCE_NONE RCC_RTCCLKSOURCE_NO_CLK @@ -3914,10 +3991,7 @@ extern "C" { /** @defgroup HAL_RTC_Aliased_Macros HAL RTC Aliased Macros maintained for legacy purpose * @{ */ -#if defined (STM32G0) || defined (STM32L5) || defined (STM32L412xx) || defined (STM32L422xx) || \ - defined (STM32L4P5xx)|| defined (STM32L4Q5xx) || defined (STM32G4) || defined (STM32WL) || defined (STM32U5) || \ - defined (STM32WBA) || defined (STM32H5) || \ - defined (STM32C0) || defined (STM32H7RS) || defined (STM32U0) +#if defined (STM32G0) || defined (STM32L5) || defined (STM32L412xx) || defined (STM32L422xx) || defined (STM32L4P5xx)|| defined (STM32L4Q5xx) || defined (STM32G4) || defined (STM32WL) || defined (STM32U5) || defined (STM32WBA) || defined (STM32H5) || defined (STM32C0) || defined (STM32N6) || defined (STM32H7RS) || defined (STM32U0) || defined (STM32U3) #else #define __HAL_RTC_CLEAR_FLAG __HAL_RTC_EXTI_CLEAR_FLAG #endif @@ -4211,6 +4285,33 @@ extern "C" { #define HAL_PCD_SetTxFiFo HAL_PCDEx_SetTxFiFo #define HAL_PCD_SetRxFiFo HAL_PCDEx_SetRxFiFo +#if defined(STM32U5) +#define USB_OTG_GOTGCTL_BSESVLD USB_OTG_GOTGCTL_BSVLD +#define USB_OTG_GAHBCFG_GINT USB_OTG_GAHBCFG_GINTMSK +#define USB_OTG_GUSBCFG_PHYLPCS USB_OTG_GUSBCFG_PHYLPC +#define USB_OTG_GRSTCTL_HSRST USB_OTG_GRSTCTL_PSRST +#define USB_OTG_GINTSTS_BOUTNAKEFF USB_OTG_GINTSTS_GONAKEFF +#define USB_OTG_GINTSTS_WKUINT USB_OTG_GINTSTS_WKUPINT +#define USB_OTG_GINTMSK_PXFRM_IISOOXFRM USB_OTG_GINTMSK_IPXFRM_IISOOXFRM +#define USB_OTG_GRXSTSP_EPNUM USB_OTG_GRXSTSP_EPNUM_CHNUM +#define USB_OTG_GLPMCFG_L1ResumeOK USB_OTG_GLPMCFG_L1RSMOK +#define USB_OTG_HPTXFSIZ_PTXFD USB_OTG_HPTXFSIZ_PTXFSIZ +#define USB_OTG_HCCHAR_MC USB_OTG_HCCHAR_MCNT +#define USB_OTG_HCCHAR_MC_0 USB_OTG_HCCHAR_MCNT_0 +#define USB_OTG_HCCHAR_MC_1 USB_OTG_HCCHAR_MCNT_1 +#define USB_OTG_HCINTMSK_AHBERR USB_OTG_HCINTMSK_AHBERRM +#define USB_OTG_HCTSIZ_DOPING USB_OTG_HCTSIZ_DOPNG +#define USB_OTG_DOEPMSK_OPEM USB_OTG_DOEPMSK_OUTPKTERRM +#define USB_OTG_DIEPCTL_SODDFRM USB_OTG_DIEPCTL_SD1PID_SODDFRM +#define USB_OTG_DIEPTSIZ_MULCNT USB_OTG_DIEPTSIZ_MCNT +#define USB_OTG_DOEPCTL_SODDFRM USB_OTG_DOEPCTL_SD1PID_SODDFRM +#define USB_OTG_DOEPCTL_DPID USB_OTG_DOEPCTL_DPID_EONUM +#define USB_OTG_DOEPTSIZ_STUPCNT USB_OTG_DOEPTSIZ_RXDPID +#define USB_OTG_DOEPTSIZ_STUPCNT_0 USB_OTG_DOEPTSIZ_RXDPID_0 +#define USB_OTG_DOEPTSIZ_STUPCNT_1 USB_OTG_DOEPTSIZ_RXDPID_1 +#define USB_OTG_PCGCCTL_STOPCLK USB_OTG_PCGCCTL_STPPCLK +#define USB_OTG_PCGCCTL_GATECLK USB_OTG_PCGCCTL_GATEHCLK +#endif /** * @} */ diff --git a/system/Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_can.h b/system/Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_can.h index 6c8028a004..a70d49ca4e 100644 --- a/system/Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_can.h +++ b/system/Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_can.h @@ -621,10 +621,10 @@ typedef void (*pCAN_CallbackTypeDef)(CAN_HandleTypeDef *hcan); /*!< pointer to * @retval None */ #define __HAL_CAN_CLEAR_FLAG(__HANDLE__, __FLAG__) \ - ((((__FLAG__) >> 8U) == 5U)? (((__HANDLE__)->Instance->TSR) = (1U << ((__FLAG__) & CAN_FLAG_MASK))): \ - (((__FLAG__) >> 8U) == 2U)? (((__HANDLE__)->Instance->RF0R) = (1U << ((__FLAG__) & CAN_FLAG_MASK))): \ - (((__FLAG__) >> 8U) == 4U)? (((__HANDLE__)->Instance->RF1R) = (1U << ((__FLAG__) & CAN_FLAG_MASK))): \ - (((__FLAG__) >> 8U) == 1U)? (((__HANDLE__)->Instance->MSR) = (1U << ((__FLAG__) & CAN_FLAG_MASK))): 0U) + ((((__FLAG__) >> 8U) == 5U)? (((__HANDLE__)->Instance->TSR) = (1UL << ((__FLAG__) & CAN_FLAG_MASK))): \ + (((__FLAG__) >> 8U) == 2U)? (((__HANDLE__)->Instance->RF0R) = (1UL << ((__FLAG__) & CAN_FLAG_MASK))): \ + (((__FLAG__) >> 8U) == 4U)? (((__HANDLE__)->Instance->RF1R) = (1UL << ((__FLAG__) & CAN_FLAG_MASK))): \ + (((__FLAG__) >> 8U) == 1U)? (((__HANDLE__)->Instance->MSR) = (1UL << ((__FLAG__) & CAN_FLAG_MASK))): 0U) /** * @} diff --git a/system/Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_crc.h b/system/Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_crc.h index 163041542f..0dd501c556 100644 --- a/system/Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_crc.h +++ b/system/Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_crc.h @@ -308,8 +308,8 @@ void HAL_CRC_MspDeInit(CRC_HandleTypeDef *hcrc); /** @defgroup CRC_Exported_Functions_Group2 Peripheral Control functions * @{ */ -uint32_t HAL_CRC_Accumulate(CRC_HandleTypeDef *hcrc, uint32_t pBuffer[], uint32_t BufferLength); -uint32_t HAL_CRC_Calculate(CRC_HandleTypeDef *hcrc, uint32_t pBuffer[], uint32_t BufferLength); +uint32_t HAL_CRC_Accumulate(CRC_HandleTypeDef *hcrc, const uint32_t pBuffer[], uint32_t BufferLength); +uint32_t HAL_CRC_Calculate(CRC_HandleTypeDef *hcrc, const uint32_t pBuffer[], uint32_t BufferLength); /** * @} */ diff --git a/system/Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_gpio.h b/system/Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_gpio.h index 7e7650c803..3efba823b1 100644 --- a/system/Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_gpio.h +++ b/system/Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_gpio.h @@ -210,25 +210,25 @@ typedef enum /** @defgroup GPIO_Private_Constants GPIO Private Constants * @{ */ -#define GPIO_MODE_Pos 0u -#define GPIO_MODE (0x3uL << GPIO_MODE_Pos) -#define MODE_INPUT (0x0uL << GPIO_MODE_Pos) -#define MODE_OUTPUT (0x1uL << GPIO_MODE_Pos) -#define MODE_AF (0x2uL << GPIO_MODE_Pos) -#define MODE_ANALOG (0x3uL << GPIO_MODE_Pos) -#define OUTPUT_TYPE_Pos 4u -#define OUTPUT_TYPE (0x1uL << OUTPUT_TYPE_Pos) -#define OUTPUT_PP (0x0uL << OUTPUT_TYPE_Pos) -#define OUTPUT_OD (0x1uL << OUTPUT_TYPE_Pos) -#define EXTI_MODE_Pos 16u -#define EXTI_MODE (0x3uL << EXTI_MODE_Pos) -#define EXTI_IT (0x1uL << EXTI_MODE_Pos) -#define EXTI_EVT (0x2uL << EXTI_MODE_Pos) -#define TRIGGER_MODE_Pos 20u -#define TRIGGER_MODE (0x7uL << TRIGGER_MODE_Pos) -#define TRIGGER_RISING (0x1uL << TRIGGER_MODE_Pos) -#define TRIGGER_FALLING (0x2uL << TRIGGER_MODE_Pos) -#define TRIGGER_LEVEL (0x4uL << TRIGGER_MODE_Pos) +#define GPIO_MODE_Pos 0U +#define GPIO_MODE (0x3UL << GPIO_MODE_Pos) +#define MODE_INPUT (0x0UL << GPIO_MODE_Pos) +#define MODE_OUTPUT (0x1UL << GPIO_MODE_Pos) +#define MODE_AF (0x2UL << GPIO_MODE_Pos) +#define MODE_ANALOG (0x3UL << GPIO_MODE_Pos) +#define OUTPUT_TYPE_Pos 4U +#define OUTPUT_TYPE (0x1UL << OUTPUT_TYPE_Pos) +#define OUTPUT_PP (0x0UL << OUTPUT_TYPE_Pos) +#define OUTPUT_OD (0x1UL << OUTPUT_TYPE_Pos) +#define EXTI_MODE_Pos 16U +#define EXTI_MODE (0x3UL << EXTI_MODE_Pos) +#define EXTI_IT (0x1UL << EXTI_MODE_Pos) +#define EXTI_EVT (0x2UL << EXTI_MODE_Pos) +#define TRIGGER_MODE_Pos 20U +#define TRIGGER_MODE (0x7UL << TRIGGER_MODE_Pos) +#define TRIGGER_RISING (0x1UL << TRIGGER_MODE_Pos) +#define TRIGGER_FALLING (0x2UL << TRIGGER_MODE_Pos) +#define TRIGGER_LEVEL (0x4UL << TRIGGER_MODE_Pos) /** * @} */ @@ -238,8 +238,8 @@ typedef enum */ #define IS_GPIO_PIN_ACTION(ACTION) (((ACTION) == GPIO_PIN_RESET) || ((ACTION) == GPIO_PIN_SET)) -#define IS_GPIO_PIN(__PIN__) (((((uint32_t)__PIN__) & GPIO_PIN_MASK) != 0x00U) &&\ - ((((uint32_t)__PIN__) & ~GPIO_PIN_MASK) == 0x00U)) +#define IS_GPIO_PIN(__PIN__) (((((uint32_t)(__PIN__)) & GPIO_PIN_MASK) != 0x00U) &&\ + ((((uint32_t)(__PIN__)) & ~GPIO_PIN_MASK) == 0x00U)) #define IS_GPIO_MODE(__MODE__) (((__MODE__) == GPIO_MODE_INPUT) ||\ ((__MODE__) == GPIO_MODE_OUTPUT_PP) ||\ diff --git a/system/Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_gpio_ex.h b/system/Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_gpio_ex.h index 8dd57aa93f..478de3701c 100644 --- a/system/Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_gpio_ex.h +++ b/system/Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_gpio_ex.h @@ -1468,31 +1468,31 @@ */ #if defined(STM32F303x8) || defined(STM32F334x8) || defined(STM32F328xx) || \ defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx) -#define GPIO_GET_INDEX(__GPIOx__) (((__GPIOx__) == (GPIOA))? 0U :\ - ((__GPIOx__) == (GPIOB))? 1U :\ - ((__GPIOx__) == (GPIOC))? 2U :\ - ((__GPIOx__) == (GPIOD))? 3U : 5U) +#define GPIO_GET_INDEX(__GPIOx__) (((__GPIOx__) == (GPIOA))? 0UL :\ + ((__GPIOx__) == (GPIOB))? 1UL :\ + ((__GPIOx__) == (GPIOC))? 2UL :\ + ((__GPIOx__) == (GPIOD))? 3UL : 5UL) #endif /* STM32F303x8 || STM32F334x8 || STM32F328xx || */ /* STM32F301x8 || STM32F302x8 || STM32F318xx */ #if defined(STM32F302xC) || defined(STM32F303xC) || defined(STM32F358xx) || \ defined(STM32F373xC) || defined(STM32F378xx) -#define GPIO_GET_INDEX(__GPIOx__) (((__GPIOx__) == (GPIOA))? 0U :\ - ((__GPIOx__) == (GPIOB))? 1U :\ - ((__GPIOx__) == (GPIOC))? 2U :\ - ((__GPIOx__) == (GPIOD))? 3U :\ - ((__GPIOx__) == (GPIOE))? 4U : 5U) +#define GPIO_GET_INDEX(__GPIOx__) (((__GPIOx__) == (GPIOA))? 0UL :\ + ((__GPIOx__) == (GPIOB))? 1UL :\ + ((__GPIOx__) == (GPIOC))? 2UL :\ + ((__GPIOx__) == (GPIOD))? 3UL :\ + ((__GPIOx__) == (GPIOE))? 4UL : 5UL) #endif /* STM32F302xC || STM32F303xC || STM32F358xx || */ /* STM32F373xC || STM32F378xx */ #if defined(STM32F302xE) || defined(STM32F303xE) || defined(STM32F398xx) -#define GPIO_GET_INDEX(__GPIOx__) (((__GPIOx__) == (GPIOA))? 0U :\ - ((__GPIOx__) == (GPIOB))? 1U :\ - ((__GPIOx__) == (GPIOC))? 2U :\ - ((__GPIOx__) == (GPIOD))? 3U :\ - ((__GPIOx__) == (GPIOE))? 4U :\ - ((__GPIOx__) == (GPIOF))? 5U :\ - ((__GPIOx__) == (GPIOG))? 6U : 7U) +#define GPIO_GET_INDEX(__GPIOx__) (((__GPIOx__) == (GPIOA))? 0UL :\ + ((__GPIOx__) == (GPIOB))? 1UL :\ + ((__GPIOx__) == (GPIOC))? 2UL :\ + ((__GPIOx__) == (GPIOD))? 3UL :\ + ((__GPIOx__) == (GPIOE))? 4UL :\ + ((__GPIOx__) == (GPIOF))? 5UL :\ + ((__GPIOx__) == (GPIOG))? 6UL : 7UL) #endif /* STM32F302xE || STM32F303xE || STM32F398xx */ /** diff --git a/system/Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_hrtim.h b/system/Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_hrtim.h index cfbc9039d7..f6cd5218c0 100644 --- a/system/Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_hrtim.h +++ b/system/Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_hrtim.h @@ -21,7 +21,7 @@ #define STM32F3xx_HAL_HRTIM_H #ifdef __cplusplus - extern "C" { +extern "C" { #endif /* Includes ------------------------------------------------------------------*/ @@ -60,7 +60,7 @@ */ typedef struct { - uint32_t HRTIMInterruptResquests; /*!< Specifies which interrupts requests must enabled for the HRTIM instance. + uint32_t HRTIMInterruptRequests; /*!< Specifies which interrupts requests must enabled for the HRTIM instance. This parameter can be any combination of @ref HRTIM_Common_Interrupt_Enable */ uint32_t SyncOptions; /*!< Specifies how the HRTIM instance handles the external synchronization signals. The HRTIM instance can be configured to act as a slave (waiting for a trigger @@ -119,7 +119,7 @@ typedef struct __HRTIM_HandleTypeDef typedef struct #endif /* USE_HAL_HRTIM_REGISTER_CALLBACKS */ { - HRTIM_TypeDef * Instance; /*!< Register base address */ + HRTIM_TypeDef *Instance; /*!< Register base address */ HRTIM_InitTypeDef Init; /*!< HRTIM required parameters */ @@ -129,12 +129,12 @@ typedef struct __IO HAL_HRTIM_StateTypeDef State; /*!< HRTIM communication state */ - DMA_HandleTypeDef * hdmaMaster; /*!< Master timer DMA handle parameters */ - DMA_HandleTypeDef * hdmaTimerA; /*!< Timer A DMA handle parameters */ - DMA_HandleTypeDef * hdmaTimerB; /*!< Timer B DMA handle parameters */ - DMA_HandleTypeDef * hdmaTimerC; /*!< Timer C DMA handle parameters */ - DMA_HandleTypeDef * hdmaTimerD; /*!< Timer D DMA handle parameters */ - DMA_HandleTypeDef * hdmaTimerE; /*!< Timer E DMA handle parameters */ + DMA_HandleTypeDef *hdmaMaster; /*!< Master timer DMA handle parameters */ + DMA_HandleTypeDef *hdmaTimerA; /*!< Timer A DMA handle parameters */ + DMA_HandleTypeDef *hdmaTimerB; /*!< Timer B DMA handle parameters */ + DMA_HandleTypeDef *hdmaTimerC; /*!< Timer C DMA handle parameters */ + DMA_HandleTypeDef *hdmaTimerD; /*!< Timer D DMA handle parameters */ + DMA_HandleTypeDef *hdmaTimerE; /*!< Timer E DMA handle parameters */ #if (USE_HAL_HRTIM_REGISTER_CALLBACKS == 1) void (* Fault1Callback)(struct __HRTIM_HandleTypeDef *hhrtim); /*!< Fault 1 interrupt callback function pointer */ @@ -482,7 +482,8 @@ typedef struct /** * @brief HAL HRTIM Callback ID enumeration definition */ -typedef enum { +typedef enum +{ HAL_HRTIM_FAULT1CALLBACK_CB_ID = 0x00U, /*!< Fault 1 interrupt callback ID */ HAL_HRTIM_FAULT2CALLBACK_CB_ID = 0x01U, /*!< Fault 2 interrupt callback ID */ HAL_HRTIM_FAULT3CALLBACK_CB_ID = 0x02U, /*!< Fault 3 interrupt callback ID */ @@ -512,7 +513,7 @@ typedef enum { HAL_HRTIM_MSPINIT_CB_ID = 0x20U, /*!< HRTIM MspInit callback ID */ HAL_HRTIM_MSPDEINIT_CB_ID = 0x21U, /*!< HRTIM MspInit callback ID */ -}HAL_HRTIM_CallbackIDTypeDef; +} HAL_HRTIM_CallbackIDTypeDef; /** * @brief HAL HRTIM Callback function pointer definitions @@ -558,8 +559,8 @@ typedef void (* pHRTIM_TIMxCallbackTypeDef)(HRTIM_HandleTypeDef *hhrtim, /*!< #define HRTIM_TIMERID_TIMER_D (HRTIM_MCR_TDCEN) /*!< Timer D identifier */ #define HRTIM_TIMERID_TIMER_E (HRTIM_MCR_TECEN) /*!< Timer E identifier */ /** - * @} - */ + * @} + */ /** @defgroup HRTIM_Compare_Unit HRTIM Compare Unit * @{ @@ -569,9 +570,9 @@ typedef void (* pHRTIM_TIMxCallbackTypeDef)(HRTIM_HandleTypeDef *hhrtim, /*!< #define HRTIM_COMPAREUNIT_2 0x00000002U /*!< Compare unit 2 identifier */ #define HRTIM_COMPAREUNIT_3 0x00000004U /*!< Compare unit 3 identifier */ #define HRTIM_COMPAREUNIT_4 0x00000008U /*!< Compare unit 4 identifier */ - /** +/** * @} - */ + */ /** @defgroup HRTIM_Capture_Unit HRTIM Capture Unit * @{ @@ -611,10 +612,10 @@ typedef void (* pHRTIM_TIMxCallbackTypeDef)(HRTIM_HandleTypeDef *hhrtim, /*!< #define HRTIM_ADCTRIGGER_4 0x00000008U /*!< ADC trigger 4 identifier */ #define IS_HRTIM_ADCTRIGGER(ADCTRIGGER)\ - (((ADCTRIGGER) == HRTIM_ADCTRIGGER_1) || \ - ((ADCTRIGGER) == HRTIM_ADCTRIGGER_2) || \ - ((ADCTRIGGER) == HRTIM_ADCTRIGGER_3) || \ - ((ADCTRIGGER) == HRTIM_ADCTRIGGER_4)) + (((ADCTRIGGER) == HRTIM_ADCTRIGGER_1) || \ + ((ADCTRIGGER) == HRTIM_ADCTRIGGER_2) || \ + ((ADCTRIGGER) == HRTIM_ADCTRIGGER_3) || \ + ((ADCTRIGGER) == HRTIM_ADCTRIGGER_4)) /** * @} */ @@ -651,10 +652,10 @@ typedef void (* pHRTIM_TIMxCallbackTypeDef)(HRTIM_HandleTypeDef *hhrtim, /*!< */ - /** @defgroup HRTIM_Prescaler_Ratio HRTIM Prescaler Ratio +/** @defgroup HRTIM_Prescaler_Ratio HRTIM Prescaler Ratio * @{ * @brief Constants defining timer high-resolution clock prescaler ratio. - */ + */ #define HRTIM_PRESCALERRATIO_MUL32 (0x00000000U) /*!< fHRCK: fHRTIM x 32U = 4.608 GHz - Resolution: 217 ps - Min PWM frequency: 70.3 kHz (fHRTIM=144MHz) */ #define HRTIM_PRESCALERRATIO_MUL16 (0x00000001U) /*!< fHRCK: fHRTIM x 16U = 2.304 GHz - Resolution: 434 ps - Min PWM frequency: 35.1 KHz (fHRTIM=144MHz) */ #define HRTIM_PRESCALERRATIO_MUL8 (0x00000002U) /*!< fHRCK: fHRTIM x 8U = 1.152 GHz - Resolution: 868 ps - Min PWM frequency: 17.6 kHz (fHRTIM=144MHz) */ @@ -941,9 +942,9 @@ typedef void (* pHRTIM_TIMxCallbackTypeDef)(HRTIM_HandleTypeDef *hhrtim, /*!< #define HRTIM_BASICOCMODE_ACTIVE (0x00000003U) /*!< Output forced to inactive level when the timer counter reaches the compare value */ #define IS_HRTIM_BASICOCMODE(BASICOCMODE)\ - (((BASICOCMODE) == HRTIM_BASICOCMODE_TOGGLE) || \ - ((BASICOCMODE) == HRTIM_BASICOCMODE_INACTIVE) || \ - ((BASICOCMODE) == HRTIM_BASICOCMODE_ACTIVE)) + (((BASICOCMODE) == HRTIM_BASICOCMODE_TOGGLE) || \ + ((BASICOCMODE) == HRTIM_BASICOCMODE_INACTIVE) || \ + ((BASICOCMODE) == HRTIM_BASICOCMODE_ACTIVE)) /** * @} */ @@ -1047,9 +1048,9 @@ typedef void (* pHRTIM_TIMxCallbackTypeDef)(HRTIM_HandleTypeDef *hhrtim, /*!< */ #define HRTIM_OUTPUTIDLEMODE_NONE 0x00000000U /*!< The output is not affected by the burst mode operation */ #define HRTIM_OUTPUTIDLEMODE_IDLE (HRTIM_OUTR_IDLM1) /*!< The output is in idle state when requested by the burst mode controller */ - /** +/** * @} - */ + */ /** @defgroup HRTIM_Output_IDLE_Level HRTIM Output IDLE Level * @{ @@ -1176,17 +1177,25 @@ typedef void (* pHRTIM_TIMxCallbackTypeDef)(HRTIM_HandleTypeDef *hhrtim, /*!< /** @defgroup HRTIM_Deadtime_Prescaler_Ratio HRTIM Dead-time Prescaler Ratio * @{ - * @brief Constants defining division ratio between the timer clock frequency - * (fHRTIM) and the dead-time generator clock (fDTG) + * @brief Constants defining the prescaler value for the deadtime generator time step (tDTG) relative to the + * HR-Timer clock period (tHRTIM). + * @note A customer reported that the HRTIM deadtime prescaler defines in + * stm32f3xx_ll_hrtim.h were swapped between the multiplication (MUL) and + * division (DIV) settings (for example, MUL8 and DIV8 values were reversed). + * The legacy naming is intentionally kept for backward compatibility, even + * though it does not strictly match the reference manual. Renaming these + * constants would introduce a breaking API change, which may lead to + * incorrect deadtime programming and potential safety issues due to deadtime + * violations in existing applications. */ -#define HRTIM_TIMDEADTIME_PRESCALERRATIO_MUL8 (0x00000000U) /*!< fDTG = fHRTIM * 8U */ -#define HRTIM_TIMDEADTIME_PRESCALERRATIO_MUL4 (HRTIM_DTR_DTPRSC_0) /*!< fDTG = fHRTIM * 4U */ -#define HRTIM_TIMDEADTIME_PRESCALERRATIO_MUL2 (HRTIM_DTR_DTPRSC_1) /*!< fDTG = fHRTIM * 2U */ -#define HRTIM_TIMDEADTIME_PRESCALERRATIO_DIV1 (HRTIM_DTR_DTPRSC_1 | HRTIM_DTR_DTPRSC_0) /*!< fDTG = fHRTIM */ -#define HRTIM_TIMDEADTIME_PRESCALERRATIO_DIV2 (HRTIM_DTR_DTPRSC_2) /*!< fDTG = fHRTIM / 2U */ -#define HRTIM_TIMDEADTIME_PRESCALERRATIO_DIV4 (HRTIM_DTR_DTPRSC_2 | HRTIM_DTR_DTPRSC_0) /*!< fDTG = fHRTIM / 4U */ -#define HRTIM_TIMDEADTIME_PRESCALERRATIO_DIV8 (HRTIM_DTR_DTPRSC_2 | HRTIM_DTR_DTPRSC_1) /*!< fDTG = fHRTIM / 8U */ -#define HRTIM_TIMDEADTIME_PRESCALERRATIO_DIV16 (HRTIM_DTR_DTPRSC_2 | HRTIM_DTR_DTPRSC_1 | HRTIM_DTR_DTPRSC_0) /*!< fDTG = fHRTIM / 16U */ +#define HRTIM_TIMDEADTIME_PRESCALERRATIO_MUL8 (0x00000000U) /*!< tDTG = tHRTIM / 8U */ +#define HRTIM_TIMDEADTIME_PRESCALERRATIO_MUL4 (HRTIM_DTR_DTPRSC_0) /*!< tDTG = tHRTIM / 4U */ +#define HRTIM_TIMDEADTIME_PRESCALERRATIO_MUL2 (HRTIM_DTR_DTPRSC_1) /*!< tDTG = tHRTIM / 2U */ +#define HRTIM_TIMDEADTIME_PRESCALERRATIO_DIV1 (HRTIM_DTR_DTPRSC_1 | HRTIM_DTR_DTPRSC_0) /*!< tDTG = tHRTIM */ +#define HRTIM_TIMDEADTIME_PRESCALERRATIO_DIV2 (HRTIM_DTR_DTPRSC_2) /*!< tDTG = tHRTIM * 2U */ +#define HRTIM_TIMDEADTIME_PRESCALERRATIO_DIV4 (HRTIM_DTR_DTPRSC_2 | HRTIM_DTR_DTPRSC_0) /*!< tDTG = tHRTIM * 4U */ +#define HRTIM_TIMDEADTIME_PRESCALERRATIO_DIV8 (HRTIM_DTR_DTPRSC_2 | HRTIM_DTR_DTPRSC_1) /*!< tDTG = tHRTIM * 8U */ +#define HRTIM_TIMDEADTIME_PRESCALERRATIO_DIV16 (HRTIM_DTR_DTPRSC_2 | HRTIM_DTR_DTPRSC_1 | HRTIM_DTR_DTPRSC_0) /*!< tDTG = tHRTIM * 16U */ /** * @} */ @@ -1277,9 +1286,9 @@ typedef void (* pHRTIM_TIMxCallbackTypeDef)(HRTIM_HandleTypeDef *hhrtim, /*!< #define HRTIM_CHOPPER_PRESCALERRATIO_DIV224 (HRTIM_CHPR_CARFRQ_3 | HRTIM_CHPR_CARFRQ_2 | HRTIM_CHPR_CARFRQ_0) /*!< fCHPFRQ = fHRTIM / 224 */ #define HRTIM_CHOPPER_PRESCALERRATIO_DIV240 (HRTIM_CHPR_CARFRQ_3 | HRTIM_CHPR_CARFRQ_2 | HRTIM_CHPR_CARFRQ_1) /*!< fCHPFRQ = fHRTIM / 240 */ #define HRTIM_CHOPPER_PRESCALERRATIO_DIV256 (HRTIM_CHPR_CARFRQ_3 | HRTIM_CHPR_CARFRQ_2 | HRTIM_CHPR_CARFRQ_1 | HRTIM_CHPR_CARFRQ_0) /*!< fCHPFRQ = fHRTIM / 256 */ - /** +/** * @} - */ + */ /** @defgroup HRTIM_Chopper_Duty_Cycle HRTIM Chopper Duty Cycle * @{ @@ -1827,8 +1836,8 @@ typedef void (* pHRTIM_TIMxCallbackTypeDef)(HRTIM_HandleTypeDef *hhrtim, /*!< #define HRTIM_OUTPUTLEVEL_INACTIVE (0x00000002U) /*!< Force the output to its inactive state */ #define IS_HRTIM_OUTPUTLEVEL(OUTPUTLEVEL)\ - (((OUTPUTLEVEL) == HRTIM_OUTPUTLEVEL_ACTIVE) || \ - ((OUTPUTLEVEL) == HRTIM_OUTPUTLEVEL_INACTIVE)) + (((OUTPUTLEVEL) == HRTIM_OUTPUTLEVEL_ACTIVE) || \ + ((OUTPUTLEVEL) == HRTIM_OUTPUTLEVEL_INACTIVE)) /** * @} */ @@ -2024,174 +2033,174 @@ typedef void (* pHRTIM_TIMxCallbackTypeDef)(HRTIM_HandleTypeDef *hhrtim, /*!< * @} */ - /* Private macros --------------------------------------------------------*/ +/* Private macros --------------------------------------------------------*/ /** @addtogroup HRTIM_Private_Macros * @{ */ #define IS_HRTIM_TIMERINDEX(TIMERINDEX)\ - (((TIMERINDEX) == HRTIM_TIMERINDEX_MASTER) || \ - ((TIMERINDEX) == HRTIM_TIMERINDEX_TIMER_A) || \ - ((TIMERINDEX) == HRTIM_TIMERINDEX_TIMER_B) || \ - ((TIMERINDEX) == HRTIM_TIMERINDEX_TIMER_C) || \ - ((TIMERINDEX) == HRTIM_TIMERINDEX_TIMER_D) || \ - ((TIMERINDEX) == HRTIM_TIMERINDEX_TIMER_E)) + (((TIMERINDEX) == HRTIM_TIMERINDEX_MASTER) || \ + ((TIMERINDEX) == HRTIM_TIMERINDEX_TIMER_A) || \ + ((TIMERINDEX) == HRTIM_TIMERINDEX_TIMER_B) || \ + ((TIMERINDEX) == HRTIM_TIMERINDEX_TIMER_C) || \ + ((TIMERINDEX) == HRTIM_TIMERINDEX_TIMER_D) || \ + ((TIMERINDEX) == HRTIM_TIMERINDEX_TIMER_E)) #define IS_HRTIM_TIMING_UNIT(TIMERINDEX)\ - (((TIMERINDEX) == HRTIM_TIMERINDEX_TIMER_A) || \ - ((TIMERINDEX) == HRTIM_TIMERINDEX_TIMER_B) || \ - ((TIMERINDEX) == HRTIM_TIMERINDEX_TIMER_C) || \ - ((TIMERINDEX) == HRTIM_TIMERINDEX_TIMER_D) || \ - ((TIMERINDEX) == HRTIM_TIMERINDEX_TIMER_E)) + (((TIMERINDEX) == HRTIM_TIMERINDEX_TIMER_A) || \ + ((TIMERINDEX) == HRTIM_TIMERINDEX_TIMER_B) || \ + ((TIMERINDEX) == HRTIM_TIMERINDEX_TIMER_C) || \ + ((TIMERINDEX) == HRTIM_TIMERINDEX_TIMER_D) || \ + ((TIMERINDEX) == HRTIM_TIMERINDEX_TIMER_E)) #define IS_HRTIM_TIMERID(TIMERID) (((TIMERID) & 0xFFC0FFFFU) == 0x00000000U) #define IS_HRTIM_COMPAREUNIT(COMPAREUNIT)\ - (((COMPAREUNIT) == HRTIM_COMPAREUNIT_1) || \ - ((COMPAREUNIT) == HRTIM_COMPAREUNIT_2) || \ - ((COMPAREUNIT) == HRTIM_COMPAREUNIT_3) || \ - ((COMPAREUNIT) == HRTIM_COMPAREUNIT_4)) + (((COMPAREUNIT) == HRTIM_COMPAREUNIT_1) || \ + ((COMPAREUNIT) == HRTIM_COMPAREUNIT_2) || \ + ((COMPAREUNIT) == HRTIM_COMPAREUNIT_3) || \ + ((COMPAREUNIT) == HRTIM_COMPAREUNIT_4)) #define IS_HRTIM_CAPTUREUNIT(CAPTUREUNIT)\ - (((CAPTUREUNIT) == HRTIM_CAPTUREUNIT_1) || \ - ((CAPTUREUNIT) == HRTIM_CAPTUREUNIT_2)) + (((CAPTUREUNIT) == HRTIM_CAPTUREUNIT_1) || \ + ((CAPTUREUNIT) == HRTIM_CAPTUREUNIT_2)) #define IS_HRTIM_OUTPUT(OUTPUT) (((OUTPUT) & 0xFFFFFC00U) == 0x00000000U) #define IS_HRTIM_TIMER_OUTPUT(TIMER, OUTPUT)\ - ((((TIMER) == HRTIM_TIMERINDEX_TIMER_A) && \ - (((OUTPUT) == HRTIM_OUTPUT_TA1) || \ - ((OUTPUT) == HRTIM_OUTPUT_TA2))) \ - || \ - (((TIMER) == HRTIM_TIMERINDEX_TIMER_B) && \ - (((OUTPUT) == HRTIM_OUTPUT_TB1) || \ - ((OUTPUT) == HRTIM_OUTPUT_TB2))) \ - || \ - (((TIMER) == HRTIM_TIMERINDEX_TIMER_C) && \ - (((OUTPUT) == HRTIM_OUTPUT_TC1) || \ - ((OUTPUT) == HRTIM_OUTPUT_TC2))) \ - || \ - (((TIMER) == HRTIM_TIMERINDEX_TIMER_D) && \ - (((OUTPUT) == HRTIM_OUTPUT_TD1) || \ - ((OUTPUT) == HRTIM_OUTPUT_TD2))) \ - || \ - (((TIMER) == HRTIM_TIMERINDEX_TIMER_E) && \ - (((OUTPUT) == HRTIM_OUTPUT_TE1) || \ - ((OUTPUT) == HRTIM_OUTPUT_TE2)))) + ((((TIMER) == HRTIM_TIMERINDEX_TIMER_A) && \ + (((OUTPUT) == HRTIM_OUTPUT_TA1) || \ + ((OUTPUT) == HRTIM_OUTPUT_TA2))) \ + || \ + (((TIMER) == HRTIM_TIMERINDEX_TIMER_B) && \ + (((OUTPUT) == HRTIM_OUTPUT_TB1) || \ + ((OUTPUT) == HRTIM_OUTPUT_TB2))) \ + || \ + (((TIMER) == HRTIM_TIMERINDEX_TIMER_C) && \ + (((OUTPUT) == HRTIM_OUTPUT_TC1) || \ + ((OUTPUT) == HRTIM_OUTPUT_TC2))) \ + || \ + (((TIMER) == HRTIM_TIMERINDEX_TIMER_D) && \ + (((OUTPUT) == HRTIM_OUTPUT_TD1) || \ + ((OUTPUT) == HRTIM_OUTPUT_TD2))) \ + || \ + (((TIMER) == HRTIM_TIMERINDEX_TIMER_E) && \ + (((OUTPUT) == HRTIM_OUTPUT_TE1) || \ + ((OUTPUT) == HRTIM_OUTPUT_TE2)))) #define IS_HRTIM_EVENT(EVENT)\ - (((EVENT) == HRTIM_EVENT_NONE)|| \ - ((EVENT) == HRTIM_EVENT_1) || \ - ((EVENT) == HRTIM_EVENT_2) || \ - ((EVENT) == HRTIM_EVENT_3) || \ - ((EVENT) == HRTIM_EVENT_4) || \ - ((EVENT) == HRTIM_EVENT_5) || \ - ((EVENT) == HRTIM_EVENT_6) || \ - ((EVENT) == HRTIM_EVENT_7) || \ - ((EVENT) == HRTIM_EVENT_8) || \ - ((EVENT) == HRTIM_EVENT_9) || \ - ((EVENT) == HRTIM_EVENT_10)) + (((EVENT) == HRTIM_EVENT_NONE)|| \ + ((EVENT) == HRTIM_EVENT_1) || \ + ((EVENT) == HRTIM_EVENT_2) || \ + ((EVENT) == HRTIM_EVENT_3) || \ + ((EVENT) == HRTIM_EVENT_4) || \ + ((EVENT) == HRTIM_EVENT_5) || \ + ((EVENT) == HRTIM_EVENT_6) || \ + ((EVENT) == HRTIM_EVENT_7) || \ + ((EVENT) == HRTIM_EVENT_8) || \ + ((EVENT) == HRTIM_EVENT_9) || \ + ((EVENT) == HRTIM_EVENT_10)) #define IS_HRTIM_FAULT(FAULT)\ - (((FAULT) == HRTIM_FAULT_1) || \ - ((FAULT) == HRTIM_FAULT_2) || \ - ((FAULT) == HRTIM_FAULT_3) || \ - ((FAULT) == HRTIM_FAULT_4) || \ - ((FAULT) == HRTIM_FAULT_5)) + (((FAULT) == HRTIM_FAULT_1) || \ + ((FAULT) == HRTIM_FAULT_2) || \ + ((FAULT) == HRTIM_FAULT_3) || \ + ((FAULT) == HRTIM_FAULT_4) || \ + ((FAULT) == HRTIM_FAULT_5)) #define IS_HRTIM_PRESCALERRATIO(PRESCALERRATIO)\ - (((PRESCALERRATIO) == HRTIM_PRESCALERRATIO_MUL32) || \ - ((PRESCALERRATIO) == HRTIM_PRESCALERRATIO_MUL16) || \ - ((PRESCALERRATIO) == HRTIM_PRESCALERRATIO_MUL8) || \ - ((PRESCALERRATIO) == HRTIM_PRESCALERRATIO_MUL4) || \ - ((PRESCALERRATIO) == HRTIM_PRESCALERRATIO_MUL2) || \ - ((PRESCALERRATIO) == HRTIM_PRESCALERRATIO_DIV1) || \ - ((PRESCALERRATIO) == HRTIM_PRESCALERRATIO_DIV2) || \ - ((PRESCALERRATIO) == HRTIM_PRESCALERRATIO_DIV4)) + (((PRESCALERRATIO) == HRTIM_PRESCALERRATIO_MUL32) || \ + ((PRESCALERRATIO) == HRTIM_PRESCALERRATIO_MUL16) || \ + ((PRESCALERRATIO) == HRTIM_PRESCALERRATIO_MUL8) || \ + ((PRESCALERRATIO) == HRTIM_PRESCALERRATIO_MUL4) || \ + ((PRESCALERRATIO) == HRTIM_PRESCALERRATIO_MUL2) || \ + ((PRESCALERRATIO) == HRTIM_PRESCALERRATIO_DIV1) || \ + ((PRESCALERRATIO) == HRTIM_PRESCALERRATIO_DIV2) || \ + ((PRESCALERRATIO) == HRTIM_PRESCALERRATIO_DIV4)) #define IS_HRTIM_MODE(MODE)\ - (((MODE) == HRTIM_MODE_CONTINUOUS) || \ - ((MODE) == HRTIM_MODE_SINGLESHOT) || \ - ((MODE) == HRTIM_MODE_SINGLESHOT_RETRIGGERABLE)) + (((MODE) == HRTIM_MODE_CONTINUOUS) || \ + ((MODE) == HRTIM_MODE_SINGLESHOT) || \ + ((MODE) == HRTIM_MODE_SINGLESHOT_RETRIGGERABLE)) #define IS_HRTIM_MODE_ONEPULSE(MODE)\ - (((MODE) == HRTIM_MODE_SINGLESHOT) || \ - ((MODE) == HRTIM_MODE_SINGLESHOT_RETRIGGERABLE)) + (((MODE) == HRTIM_MODE_SINGLESHOT) || \ + ((MODE) == HRTIM_MODE_SINGLESHOT_RETRIGGERABLE)) #define IS_HRTIM_HALFMODE(HALFMODE)\ - (((HALFMODE) == HRTIM_HALFMODE_DISABLED) || \ - ((HALFMODE) == HRTIM_HALFMODE_ENABLED)) + (((HALFMODE) == HRTIM_HALFMODE_DISABLED) || \ + ((HALFMODE) == HRTIM_HALFMODE_ENABLED)) #define IS_HRTIM_SYNCSTART(SYNCSTART)\ - (((SYNCSTART) == HRTIM_SYNCSTART_DISABLED) || \ - ((SYNCSTART) == HRTIM_SYNCSTART_ENABLED)) + (((SYNCSTART) == HRTIM_SYNCSTART_DISABLED) || \ + ((SYNCSTART) == HRTIM_SYNCSTART_ENABLED)) #define IS_HRTIM_SYNCRESET(SYNCRESET)\ - (((SYNCRESET) == HRTIM_SYNCRESET_DISABLED) || \ - ((SYNCRESET) == HRTIM_SYNCRESET_ENABLED)) + (((SYNCRESET) == HRTIM_SYNCRESET_DISABLED) || \ + ((SYNCRESET) == HRTIM_SYNCRESET_ENABLED)) #define IS_HRTIM_DACSYNC(DACSYNC)\ - (((DACSYNC) == HRTIM_DACSYNC_NONE) || \ - ((DACSYNC) == HRTIM_DACSYNC_DACTRIGOUT_1) || \ - ((DACSYNC) == HRTIM_DACSYNC_DACTRIGOUT_2) || \ - ((DACSYNC) == HRTIM_DACSYNC_DACTRIGOUT_3)) + (((DACSYNC) == HRTIM_DACSYNC_NONE) || \ + ((DACSYNC) == HRTIM_DACSYNC_DACTRIGOUT_1) || \ + ((DACSYNC) == HRTIM_DACSYNC_DACTRIGOUT_2) || \ + ((DACSYNC) == HRTIM_DACSYNC_DACTRIGOUT_3)) #define IS_HRTIM_PRELOAD(PRELOAD)\ - (((PRELOAD) == HRTIM_PRELOAD_DISABLED) || \ - ((PRELOAD) == HRTIM_PRELOAD_ENABLED)) + (((PRELOAD) == HRTIM_PRELOAD_DISABLED) || \ + ((PRELOAD) == HRTIM_PRELOAD_ENABLED)) #define IS_HRTIM_UPDATEGATING_MASTER(UPDATEGATING)\ - (((UPDATEGATING) == HRTIM_UPDATEGATING_INDEPENDENT) || \ - ((UPDATEGATING) == HRTIM_UPDATEGATING_DMABURST) || \ - ((UPDATEGATING) == HRTIM_UPDATEGATING_DMABURST_UPDATE)) + (((UPDATEGATING) == HRTIM_UPDATEGATING_INDEPENDENT) || \ + ((UPDATEGATING) == HRTIM_UPDATEGATING_DMABURST) || \ + ((UPDATEGATING) == HRTIM_UPDATEGATING_DMABURST_UPDATE)) #define IS_HRTIM_UPDATEGATING_TIM(UPDATEGATING)\ - (((UPDATEGATING) == HRTIM_UPDATEGATING_INDEPENDENT) || \ - ((UPDATEGATING) == HRTIM_UPDATEGATING_DMABURST) || \ - ((UPDATEGATING) == HRTIM_UPDATEGATING_DMABURST_UPDATE) || \ - ((UPDATEGATING) == HRTIM_UPDATEGATING_UPDEN1) || \ - ((UPDATEGATING) == HRTIM_UPDATEGATING_UPDEN2) || \ - ((UPDATEGATING) == HRTIM_UPDATEGATING_UPDEN3) || \ - ((UPDATEGATING) == HRTIM_UPDATEGATING_UPDEN1_UPDATE) || \ - ((UPDATEGATING) == HRTIM_UPDATEGATING_UPDEN2_UPDATE) || \ - ((UPDATEGATING) == HRTIM_UPDATEGATING_UPDEN3_UPDATE)) + (((UPDATEGATING) == HRTIM_UPDATEGATING_INDEPENDENT) || \ + ((UPDATEGATING) == HRTIM_UPDATEGATING_DMABURST) || \ + ((UPDATEGATING) == HRTIM_UPDATEGATING_DMABURST_UPDATE) || \ + ((UPDATEGATING) == HRTIM_UPDATEGATING_UPDEN1) || \ + ((UPDATEGATING) == HRTIM_UPDATEGATING_UPDEN2) || \ + ((UPDATEGATING) == HRTIM_UPDATEGATING_UPDEN3) || \ + ((UPDATEGATING) == HRTIM_UPDATEGATING_UPDEN1_UPDATE) || \ + ((UPDATEGATING) == HRTIM_UPDATEGATING_UPDEN2_UPDATE) || \ + ((UPDATEGATING) == HRTIM_UPDATEGATING_UPDEN3_UPDATE)) #define IS_HRTIM_TIMERBURSTMODE(MODE) \ - (((MODE) == HRTIM_TIMERBURSTMODE_MAINTAINCLOCK) || \ - ((MODE) == HRTIM_TIMERBURSTMODE_RESETCOUNTER)) + (((MODE) == HRTIM_TIMERBURSTMODE_MAINTAINCLOCK) || \ + ((MODE) == HRTIM_TIMERBURSTMODE_RESETCOUNTER)) #define IS_HRTIM_UPDATEONREPETITION(UPDATEONREPETITION) \ - (((UPDATEONREPETITION) == HRTIM_UPDATEONREPETITION_DISABLED) || \ - ((UPDATEONREPETITION) == HRTIM_UPDATEONREPETITION_ENABLED)) + (((UPDATEONREPETITION) == HRTIM_UPDATEONREPETITION_DISABLED) || \ + ((UPDATEONREPETITION) == HRTIM_UPDATEONREPETITION_ENABLED)) #define IS_HRTIM_TIMPUSHPULLMODE(TIMPUSHPULLMODE)\ - (((TIMPUSHPULLMODE) == HRTIM_TIMPUSHPULLMODE_DISABLED) || \ - ((TIMPUSHPULLMODE) == HRTIM_TIMPUSHPULLMODE_ENABLED)) + (((TIMPUSHPULLMODE) == HRTIM_TIMPUSHPULLMODE_DISABLED) || \ + ((TIMPUSHPULLMODE) == HRTIM_TIMPUSHPULLMODE_ENABLED)) #define IS_HRTIM_TIMFAULTENABLE(TIMFAULTENABLE) (((TIMFAULTENABLE) & 0xFFFFFFE0U) == 0x00000000U) #define IS_HRTIM_TIMFAULTLOCK(TIMFAULTLOCK)\ - (((TIMFAULTLOCK) == HRTIM_TIMFAULTLOCK_READWRITE) || \ - ((TIMFAULTLOCK) == HRTIM_TIMFAULTLOCK_READONLY)) + (((TIMFAULTLOCK) == HRTIM_TIMFAULTLOCK_READWRITE) || \ + ((TIMFAULTLOCK) == HRTIM_TIMFAULTLOCK_READONLY)) #define IS_HRTIM_TIMDEADTIMEINSERTION(TIMPUSHPULLMODE, TIMDEADTIMEINSERTION)\ - ((((TIMPUSHPULLMODE) == HRTIM_TIMPUSHPULLMODE_DISABLED) && \ - ((((TIMDEADTIMEINSERTION) == HRTIM_TIMDEADTIMEINSERTION_DISABLED) || \ - ((TIMDEADTIMEINSERTION) == HRTIM_TIMDEADTIMEINSERTION_ENABLED)))) \ - || \ - (((TIMPUSHPULLMODE) == HRTIM_TIMPUSHPULLMODE_ENABLED) && \ - ((TIMDEADTIMEINSERTION) == HRTIM_TIMDEADTIMEINSERTION_DISABLED))) + ((((TIMPUSHPULLMODE) == HRTIM_TIMPUSHPULLMODE_DISABLED) && \ + ((((TIMDEADTIMEINSERTION) == HRTIM_TIMDEADTIMEINSERTION_DISABLED) || \ + ((TIMDEADTIMEINSERTION) == HRTIM_TIMDEADTIMEINSERTION_ENABLED)))) \ + || \ + (((TIMPUSHPULLMODE) == HRTIM_TIMPUSHPULLMODE_ENABLED) && \ + ((TIMDEADTIMEINSERTION) == HRTIM_TIMDEADTIMEINSERTION_DISABLED))) #define IS_HRTIM_TIMDELAYEDPROTECTION(TIMPUSHPULLMODE, TIMDELAYEDPROTECTION)\ - ((((TIMDELAYEDPROTECTION) == HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DISABLED) || \ - ((TIMDELAYEDPROTECTION) == HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DELAYEDOUT1_EEV6) || \ - ((TIMDELAYEDPROTECTION) == HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DELAYEDOUT2_EEV6) || \ - ((TIMDELAYEDPROTECTION) == HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DELAYEDBOTH_EEV6) || \ - ((TIMDELAYEDPROTECTION) == HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DELAYEDOUT1_DEEV7) || \ - ((TIMDELAYEDPROTECTION) == HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DELAYEDOUT2_DEEV7) || \ - ((TIMDELAYEDPROTECTION) == HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DELAYEDBOTH_EEV7)) \ - || \ - (((TIMPUSHPULLMODE) == HRTIM_TIMPUSHPULLMODE_ENABLED) && \ - (((TIMDELAYEDPROTECTION) == HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_BALANCED_EEV6) || \ - ((TIMDELAYEDPROTECTION) == HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_BALANCED_EEV7)))) + ((((TIMDELAYEDPROTECTION) == HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DISABLED) || \ + ((TIMDELAYEDPROTECTION) == HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DELAYEDOUT1_EEV6) || \ + ((TIMDELAYEDPROTECTION) == HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DELAYEDOUT2_EEV6) || \ + ((TIMDELAYEDPROTECTION) == HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DELAYEDBOTH_EEV6) || \ + ((TIMDELAYEDPROTECTION) == HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DELAYEDOUT1_DEEV7) || \ + ((TIMDELAYEDPROTECTION) == HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DELAYEDOUT2_DEEV7) || \ + ((TIMDELAYEDPROTECTION) == HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DELAYEDBOTH_EEV7)) \ + || \ + (((TIMPUSHPULLMODE) == HRTIM_TIMPUSHPULLMODE_ENABLED) && \ + (((TIMDELAYEDPROTECTION) == HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_BALANCED_EEV6) || \ + ((TIMDELAYEDPROTECTION) == HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_BALANCED_EEV7)))) #define IS_HRTIM_TIMUPDATETRIGGER(TIMUPDATETRIGGER) (((TIMUPDATETRIGGER) & 0xFE07FFFFU) == 0x00000000U) @@ -2199,128 +2208,128 @@ typedef void (* pHRTIM_TIMxCallbackTypeDef)(HRTIM_HandleTypeDef *hhrtim, /*!< #define IS_HRTIM_TIMUPDATEONRESET(TIMUPDATEONRESET) \ - (((TIMUPDATEONRESET) == HRTIM_TIMUPDATEONRESET_DISABLED) || \ - ((TIMUPDATEONRESET) == HRTIM_TIMUPDATEONRESET_ENABLED)) + (((TIMUPDATEONRESET) == HRTIM_TIMUPDATEONRESET_DISABLED) || \ + ((TIMUPDATEONRESET) == HRTIM_TIMUPDATEONRESET_ENABLED)) #define IS_HRTIM_AUTODELAYEDMODE(AUTODELAYEDMODE)\ - (((AUTODELAYEDMODE) == HRTIM_AUTODELAYEDMODE_REGULAR) || \ - ((AUTODELAYEDMODE) == HRTIM_AUTODELAYEDMODE_AUTODELAYED_NOTIMEOUT) || \ - ((AUTODELAYEDMODE) == HRTIM_AUTODELAYEDMODE_AUTODELAYED_TIMEOUTCMP1) || \ - ((AUTODELAYEDMODE) == HRTIM_AUTODELAYEDMODE_AUTODELAYED_TIMEOUTCMP3)) + (((AUTODELAYEDMODE) == HRTIM_AUTODELAYEDMODE_REGULAR) || \ + ((AUTODELAYEDMODE) == HRTIM_AUTODELAYEDMODE_AUTODELAYED_NOTIMEOUT) || \ + ((AUTODELAYEDMODE) == HRTIM_AUTODELAYEDMODE_AUTODELAYED_TIMEOUTCMP1) || \ + ((AUTODELAYEDMODE) == HRTIM_AUTODELAYEDMODE_AUTODELAYED_TIMEOUTCMP3)) /* Auto delayed mode is only available for compare units 2 and 4U */ #define IS_HRTIM_COMPAREUNIT_AUTODELAYEDMODE(COMPAREUNIT, AUTODELAYEDMODE) \ - ((((COMPAREUNIT) == HRTIM_COMPAREUNIT_2) && \ - (((AUTODELAYEDMODE) == HRTIM_AUTODELAYEDMODE_REGULAR) || \ - ((AUTODELAYEDMODE) == HRTIM_AUTODELAYEDMODE_AUTODELAYED_NOTIMEOUT) || \ - ((AUTODELAYEDMODE) == HRTIM_AUTODELAYEDMODE_AUTODELAYED_TIMEOUTCMP1) || \ - ((AUTODELAYEDMODE) == HRTIM_AUTODELAYEDMODE_AUTODELAYED_TIMEOUTCMP3))) \ - || \ - (((COMPAREUNIT) == HRTIM_COMPAREUNIT_4) && \ - (((AUTODELAYEDMODE) == HRTIM_AUTODELAYEDMODE_REGULAR) || \ - ((AUTODELAYEDMODE) == HRTIM_AUTODELAYEDMODE_AUTODELAYED_NOTIMEOUT) || \ - ((AUTODELAYEDMODE) == HRTIM_AUTODELAYEDMODE_AUTODELAYED_TIMEOUTCMP1) || \ - ((AUTODELAYEDMODE) == HRTIM_AUTODELAYEDMODE_AUTODELAYED_TIMEOUTCMP3)))) + ((((COMPAREUNIT) == HRTIM_COMPAREUNIT_2) && \ + (((AUTODELAYEDMODE) == HRTIM_AUTODELAYEDMODE_REGULAR) || \ + ((AUTODELAYEDMODE) == HRTIM_AUTODELAYEDMODE_AUTODELAYED_NOTIMEOUT) || \ + ((AUTODELAYEDMODE) == HRTIM_AUTODELAYEDMODE_AUTODELAYED_TIMEOUTCMP1) || \ + ((AUTODELAYEDMODE) == HRTIM_AUTODELAYEDMODE_AUTODELAYED_TIMEOUTCMP3))) \ + || \ + (((COMPAREUNIT) == HRTIM_COMPAREUNIT_4) && \ + (((AUTODELAYEDMODE) == HRTIM_AUTODELAYEDMODE_REGULAR) || \ + ((AUTODELAYEDMODE) == HRTIM_AUTODELAYEDMODE_AUTODELAYED_NOTIMEOUT) || \ + ((AUTODELAYEDMODE) == HRTIM_AUTODELAYEDMODE_AUTODELAYED_TIMEOUTCMP1) || \ + ((AUTODELAYEDMODE) == HRTIM_AUTODELAYEDMODE_AUTODELAYED_TIMEOUTCMP3)))) #define IS_HRTIM_OUTPUTPOLARITY(OUTPUTPOLARITY)\ - (((OUTPUTPOLARITY) == HRTIM_OUTPUTPOLARITY_HIGH) || \ - ((OUTPUTPOLARITY) == HRTIM_OUTPUTPOLARITY_LOW)) + (((OUTPUTPOLARITY) == HRTIM_OUTPUTPOLARITY_HIGH) || \ + ((OUTPUTPOLARITY) == HRTIM_OUTPUTPOLARITY_LOW)) #define IS_HRTIM_OUTPUTPULSE(OUTPUTPULSE) ((OUTPUTPULSE) <= 0x0000FFFFU) #define IS_HRTIM_OUTPUTSET(OUTPUTSET)\ - (((OUTPUTSET) == HRTIM_OUTPUTSET_NONE) || \ - ((OUTPUTSET) == HRTIM_OUTPUTSET_RESYNC) || \ - ((OUTPUTSET) == HRTIM_OUTPUTSET_TIMPER) || \ - ((OUTPUTSET) == HRTIM_OUTPUTSET_TIMCMP1) || \ - ((OUTPUTSET) == HRTIM_OUTPUTSET_TIMCMP2) || \ - ((OUTPUTSET) == HRTIM_OUTPUTSET_TIMCMP3) || \ - ((OUTPUTSET) == HRTIM_OUTPUTSET_TIMCMP4) || \ - ((OUTPUTSET) == HRTIM_OUTPUTSET_MASTERPER) || \ - ((OUTPUTSET) == HRTIM_OUTPUTSET_MASTERCMP1) || \ - ((OUTPUTSET) == HRTIM_OUTPUTSET_MASTERCMP2) || \ - ((OUTPUTSET) == HRTIM_OUTPUTSET_MASTERCMP3) || \ - ((OUTPUTSET) == HRTIM_OUTPUTSET_MASTERCMP4) || \ - ((OUTPUTSET) == HRTIM_OUTPUTSET_TIMEV_1) || \ - ((OUTPUTSET) == HRTIM_OUTPUTSET_TIMEV_2) || \ - ((OUTPUTSET) == HRTIM_OUTPUTSET_TIMEV_3) || \ - ((OUTPUTSET) == HRTIM_OUTPUTSET_TIMEV_4) || \ - ((OUTPUTSET) == HRTIM_OUTPUTSET_TIMEV_5) || \ - ((OUTPUTSET) == HRTIM_OUTPUTSET_TIMEV_6) || \ - ((OUTPUTSET) == HRTIM_OUTPUTSET_TIMEV_7) || \ - ((OUTPUTSET) == HRTIM_OUTPUTSET_TIMEV_8) || \ - ((OUTPUTSET) == HRTIM_OUTPUTSET_TIMEV_9) || \ - ((OUTPUTSET) == HRTIM_OUTPUTSET_EEV_1) || \ - ((OUTPUTSET) == HRTIM_OUTPUTSET_EEV_2) || \ - ((OUTPUTSET) == HRTIM_OUTPUTSET_EEV_3) || \ - ((OUTPUTSET) == HRTIM_OUTPUTSET_EEV_4) || \ - ((OUTPUTSET) == HRTIM_OUTPUTSET_EEV_5) || \ - ((OUTPUTSET) == HRTIM_OUTPUTSET_EEV_6) || \ - ((OUTPUTSET) == HRTIM_OUTPUTSET_EEV_7) || \ - ((OUTPUTSET) == HRTIM_OUTPUTSET_EEV_8) || \ - ((OUTPUTSET) == HRTIM_OUTPUTSET_EEV_9) || \ - ((OUTPUTSET) == HRTIM_OUTPUTSET_EEV_10) || \ - ((OUTPUTSET) == HRTIM_OUTPUTSET_UPDATE)) + (((OUTPUTSET) == HRTIM_OUTPUTSET_NONE) || \ + ((OUTPUTSET) == HRTIM_OUTPUTSET_RESYNC) || \ + ((OUTPUTSET) == HRTIM_OUTPUTSET_TIMPER) || \ + ((OUTPUTSET) == HRTIM_OUTPUTSET_TIMCMP1) || \ + ((OUTPUTSET) == HRTIM_OUTPUTSET_TIMCMP2) || \ + ((OUTPUTSET) == HRTIM_OUTPUTSET_TIMCMP3) || \ + ((OUTPUTSET) == HRTIM_OUTPUTSET_TIMCMP4) || \ + ((OUTPUTSET) == HRTIM_OUTPUTSET_MASTERPER) || \ + ((OUTPUTSET) == HRTIM_OUTPUTSET_MASTERCMP1) || \ + ((OUTPUTSET) == HRTIM_OUTPUTSET_MASTERCMP2) || \ + ((OUTPUTSET) == HRTIM_OUTPUTSET_MASTERCMP3) || \ + ((OUTPUTSET) == HRTIM_OUTPUTSET_MASTERCMP4) || \ + ((OUTPUTSET) == HRTIM_OUTPUTSET_TIMEV_1) || \ + ((OUTPUTSET) == HRTIM_OUTPUTSET_TIMEV_2) || \ + ((OUTPUTSET) == HRTIM_OUTPUTSET_TIMEV_3) || \ + ((OUTPUTSET) == HRTIM_OUTPUTSET_TIMEV_4) || \ + ((OUTPUTSET) == HRTIM_OUTPUTSET_TIMEV_5) || \ + ((OUTPUTSET) == HRTIM_OUTPUTSET_TIMEV_6) || \ + ((OUTPUTSET) == HRTIM_OUTPUTSET_TIMEV_7) || \ + ((OUTPUTSET) == HRTIM_OUTPUTSET_TIMEV_8) || \ + ((OUTPUTSET) == HRTIM_OUTPUTSET_TIMEV_9) || \ + ((OUTPUTSET) == HRTIM_OUTPUTSET_EEV_1) || \ + ((OUTPUTSET) == HRTIM_OUTPUTSET_EEV_2) || \ + ((OUTPUTSET) == HRTIM_OUTPUTSET_EEV_3) || \ + ((OUTPUTSET) == HRTIM_OUTPUTSET_EEV_4) || \ + ((OUTPUTSET) == HRTIM_OUTPUTSET_EEV_5) || \ + ((OUTPUTSET) == HRTIM_OUTPUTSET_EEV_6) || \ + ((OUTPUTSET) == HRTIM_OUTPUTSET_EEV_7) || \ + ((OUTPUTSET) == HRTIM_OUTPUTSET_EEV_8) || \ + ((OUTPUTSET) == HRTIM_OUTPUTSET_EEV_9) || \ + ((OUTPUTSET) == HRTIM_OUTPUTSET_EEV_10) || \ + ((OUTPUTSET) == HRTIM_OUTPUTSET_UPDATE)) #define IS_HRTIM_OUTPUTRESET(OUTPUTRESET)\ - (((OUTPUTRESET) == HRTIM_OUTPUTRESET_NONE) || \ - ((OUTPUTRESET) == HRTIM_OUTPUTRESET_RESYNC) || \ - ((OUTPUTRESET) == HRTIM_OUTPUTRESET_TIMPER) || \ - ((OUTPUTRESET) == HRTIM_OUTPUTRESET_TIMCMP1) || \ - ((OUTPUTRESET) == HRTIM_OUTPUTRESET_TIMCMP2) || \ - ((OUTPUTRESET) == HRTIM_OUTPUTRESET_TIMCMP3) || \ - ((OUTPUTRESET) == HRTIM_OUTPUTRESET_TIMCMP4) || \ - ((OUTPUTRESET) == HRTIM_OUTPUTRESET_MASTERPER) || \ - ((OUTPUTRESET) == HRTIM_OUTPUTRESET_MASTERCMP1) || \ - ((OUTPUTRESET) == HRTIM_OUTPUTRESET_MASTERCMP2) || \ - ((OUTPUTRESET) == HRTIM_OUTPUTRESET_MASTERCMP3) || \ - ((OUTPUTRESET) == HRTIM_OUTPUTRESET_MASTERCMP4) || \ - ((OUTPUTRESET) == HRTIM_OUTPUTRESET_TIMEV_1) || \ - ((OUTPUTRESET) == HRTIM_OUTPUTRESET_TIMEV_2) || \ - ((OUTPUTRESET) == HRTIM_OUTPUTRESET_TIMEV_3) || \ - ((OUTPUTRESET) == HRTIM_OUTPUTRESET_TIMEV_4) || \ - ((OUTPUTRESET) == HRTIM_OUTPUTRESET_TIMEV_5) || \ - ((OUTPUTRESET) == HRTIM_OUTPUTRESET_TIMEV_6) || \ - ((OUTPUTRESET) == HRTIM_OUTPUTRESET_TIMEV_7) || \ - ((OUTPUTRESET) == HRTIM_OUTPUTRESET_TIMEV_8) || \ - ((OUTPUTRESET) == HRTIM_OUTPUTRESET_TIMEV_9) || \ - ((OUTPUTRESET) == HRTIM_OUTPUTRESET_EEV_1) || \ - ((OUTPUTRESET) == HRTIM_OUTPUTRESET_EEV_2) || \ - ((OUTPUTRESET) == HRTIM_OUTPUTRESET_EEV_3) || \ - ((OUTPUTRESET) == HRTIM_OUTPUTRESET_EEV_4) || \ - ((OUTPUTRESET) == HRTIM_OUTPUTRESET_EEV_5) || \ - ((OUTPUTRESET) == HRTIM_OUTPUTRESET_EEV_6) || \ - ((OUTPUTRESET) == HRTIM_OUTPUTRESET_EEV_7) || \ - ((OUTPUTRESET) == HRTIM_OUTPUTRESET_EEV_8) || \ - ((OUTPUTRESET) == HRTIM_OUTPUTRESET_EEV_9) || \ - ((OUTPUTRESET) == HRTIM_OUTPUTRESET_EEV_10) || \ - ((OUTPUTRESET) == HRTIM_OUTPUTRESET_UPDATE)) + (((OUTPUTRESET) == HRTIM_OUTPUTRESET_NONE) || \ + ((OUTPUTRESET) == HRTIM_OUTPUTRESET_RESYNC) || \ + ((OUTPUTRESET) == HRTIM_OUTPUTRESET_TIMPER) || \ + ((OUTPUTRESET) == HRTIM_OUTPUTRESET_TIMCMP1) || \ + ((OUTPUTRESET) == HRTIM_OUTPUTRESET_TIMCMP2) || \ + ((OUTPUTRESET) == HRTIM_OUTPUTRESET_TIMCMP3) || \ + ((OUTPUTRESET) == HRTIM_OUTPUTRESET_TIMCMP4) || \ + ((OUTPUTRESET) == HRTIM_OUTPUTRESET_MASTERPER) || \ + ((OUTPUTRESET) == HRTIM_OUTPUTRESET_MASTERCMP1) || \ + ((OUTPUTRESET) == HRTIM_OUTPUTRESET_MASTERCMP2) || \ + ((OUTPUTRESET) == HRTIM_OUTPUTRESET_MASTERCMP3) || \ + ((OUTPUTRESET) == HRTIM_OUTPUTRESET_MASTERCMP4) || \ + ((OUTPUTRESET) == HRTIM_OUTPUTRESET_TIMEV_1) || \ + ((OUTPUTRESET) == HRTIM_OUTPUTRESET_TIMEV_2) || \ + ((OUTPUTRESET) == HRTIM_OUTPUTRESET_TIMEV_3) || \ + ((OUTPUTRESET) == HRTIM_OUTPUTRESET_TIMEV_4) || \ + ((OUTPUTRESET) == HRTIM_OUTPUTRESET_TIMEV_5) || \ + ((OUTPUTRESET) == HRTIM_OUTPUTRESET_TIMEV_6) || \ + ((OUTPUTRESET) == HRTIM_OUTPUTRESET_TIMEV_7) || \ + ((OUTPUTRESET) == HRTIM_OUTPUTRESET_TIMEV_8) || \ + ((OUTPUTRESET) == HRTIM_OUTPUTRESET_TIMEV_9) || \ + ((OUTPUTRESET) == HRTIM_OUTPUTRESET_EEV_1) || \ + ((OUTPUTRESET) == HRTIM_OUTPUTRESET_EEV_2) || \ + ((OUTPUTRESET) == HRTIM_OUTPUTRESET_EEV_3) || \ + ((OUTPUTRESET) == HRTIM_OUTPUTRESET_EEV_4) || \ + ((OUTPUTRESET) == HRTIM_OUTPUTRESET_EEV_5) || \ + ((OUTPUTRESET) == HRTIM_OUTPUTRESET_EEV_6) || \ + ((OUTPUTRESET) == HRTIM_OUTPUTRESET_EEV_7) || \ + ((OUTPUTRESET) == HRTIM_OUTPUTRESET_EEV_8) || \ + ((OUTPUTRESET) == HRTIM_OUTPUTRESET_EEV_9) || \ + ((OUTPUTRESET) == HRTIM_OUTPUTRESET_EEV_10) || \ + ((OUTPUTRESET) == HRTIM_OUTPUTRESET_UPDATE)) #define IS_HRTIM_OUTPUTIDLEMODE(OUTPUTIDLEMODE)\ - (((OUTPUTIDLEMODE) == HRTIM_OUTPUTIDLEMODE_NONE) || \ - ((OUTPUTIDLEMODE) == HRTIM_OUTPUTIDLEMODE_IDLE)) + (((OUTPUTIDLEMODE) == HRTIM_OUTPUTIDLEMODE_NONE) || \ + ((OUTPUTIDLEMODE) == HRTIM_OUTPUTIDLEMODE_IDLE)) #define IS_HRTIM_OUTPUTIDLELEVEL(OUTPUTIDLELEVEL)\ - (((OUTPUTIDLELEVEL) == HRTIM_OUTPUTIDLELEVEL_INACTIVE) || \ - ((OUTPUTIDLELEVEL) == HRTIM_OUTPUTIDLELEVEL_ACTIVE)) + (((OUTPUTIDLELEVEL) == HRTIM_OUTPUTIDLELEVEL_INACTIVE) || \ + ((OUTPUTIDLELEVEL) == HRTIM_OUTPUTIDLELEVEL_ACTIVE)) #define IS_HRTIM_OUTPUTFAULTLEVEL(OUTPUTFAULTLEVEL)\ - (((OUTPUTFAULTLEVEL) == HRTIM_OUTPUTFAULTLEVEL_NONE) || \ - ((OUTPUTFAULTLEVEL) == HRTIM_OUTPUTFAULTLEVEL_ACTIVE) || \ - ((OUTPUTFAULTLEVEL) == HRTIM_OUTPUTFAULTLEVEL_INACTIVE) || \ - ((OUTPUTFAULTLEVEL) == HRTIM_OUTPUTFAULTLEVEL_HIGHZ)) + (((OUTPUTFAULTLEVEL) == HRTIM_OUTPUTFAULTLEVEL_NONE) || \ + ((OUTPUTFAULTLEVEL) == HRTIM_OUTPUTFAULTLEVEL_ACTIVE) || \ + ((OUTPUTFAULTLEVEL) == HRTIM_OUTPUTFAULTLEVEL_INACTIVE) || \ + ((OUTPUTFAULTLEVEL) == HRTIM_OUTPUTFAULTLEVEL_HIGHZ)) #define IS_HRTIM_OUTPUTCHOPPERMODE(OUTPUTCHOPPERMODE)\ - (((OUTPUTCHOPPERMODE) == HRTIM_OUTPUTCHOPPERMODE_DISABLED) || \ - ((OUTPUTCHOPPERMODE) == HRTIM_OUTPUTCHOPPERMODE_ENABLED)) + (((OUTPUTCHOPPERMODE) == HRTIM_OUTPUTCHOPPERMODE_DISABLED) || \ + ((OUTPUTCHOPPERMODE) == HRTIM_OUTPUTCHOPPERMODE_ENABLED)) #define IS_HRTIM_OUTPUTBURSTMODEENTRY(OUTPUTBURSTMODEENTRY)\ - (((OUTPUTBURSTMODEENTRY) == HRTIM_OUTPUTBURSTMODEENTRY_REGULAR) || \ - ((OUTPUTBURSTMODEENTRY) == HRTIM_OUTPUTBURSTMODEENTRY_DELAYED)) + (((OUTPUTBURSTMODEENTRY) == HRTIM_OUTPUTBURSTMODEENTRY_REGULAR) || \ + ((OUTPUTBURSTMODEENTRY) == HRTIM_OUTPUTBURSTMODEENTRY_DELAYED)) #define IS_HRTIM_TIMER_CAPTURETRIGGER(TIMER, CAPTURETRIGGER) \ - (((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_NONE) || \ + (((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_NONE) || \ ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_UPDATE) || \ ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_EEV_1) || \ ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_EEV_2) || \ @@ -2334,423 +2343,423 @@ typedef void (* pHRTIM_TIMxCallbackTypeDef)(HRTIM_HandleTypeDef *hhrtim, /*!< ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_EEV_10) \ || \ (((TIMER) == HRTIM_TIMERINDEX_TIMER_A) && \ - (((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TB1_SET) || \ - ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TB1_RESET) || \ - ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERB_CMP1) || \ - ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERB_CMP2) || \ - ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TC1_SET) || \ - ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TC1_RESET) || \ - ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERC_CMP1) || \ - ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERC_CMP2) || \ - ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TD1_SET) || \ - ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TD1_RESET) || \ - ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERD_CMP1) || \ - ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERD_CMP2) || \ - ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TE1_SET) || \ - ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TE1_RESET) || \ - ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERE_CMP1) || \ - ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERE_CMP2))) \ - || \ + (((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TB1_SET) || \ + ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TB1_RESET) || \ + ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERB_CMP1) || \ + ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERB_CMP2) || \ + ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TC1_SET) || \ + ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TC1_RESET) || \ + ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERC_CMP1) || \ + ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERC_CMP2) || \ + ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TD1_SET) || \ + ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TD1_RESET) || \ + ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERD_CMP1) || \ + ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERD_CMP2) || \ + ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TE1_SET) || \ + ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TE1_RESET) || \ + ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERE_CMP1) || \ + ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERE_CMP2))) \ + || \ (((TIMER) == HRTIM_TIMERINDEX_TIMER_B) && \ - (((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TA1_SET) || \ - ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TA1_RESET) || \ - ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERA_CMP1) || \ - ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERA_CMP2) || \ - ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TC1_SET) || \ - ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TC1_RESET) || \ - ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERC_CMP1) || \ - ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERC_CMP2) || \ - ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TD1_SET) || \ - ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TD1_RESET) || \ - ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERD_CMP1) || \ - ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERD_CMP2) || \ - ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TE1_SET) || \ - ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TE1_RESET) || \ - ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERE_CMP1) || \ - ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERE_CMP2))) \ - || \ + (((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TA1_SET) || \ + ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TA1_RESET) || \ + ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERA_CMP1) || \ + ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERA_CMP2) || \ + ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TC1_SET) || \ + ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TC1_RESET) || \ + ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERC_CMP1) || \ + ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERC_CMP2) || \ + ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TD1_SET) || \ + ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TD1_RESET) || \ + ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERD_CMP1) || \ + ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERD_CMP2) || \ + ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TE1_SET) || \ + ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TE1_RESET) || \ + ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERE_CMP1) || \ + ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERE_CMP2))) \ + || \ (((TIMER) == HRTIM_TIMERINDEX_TIMER_C) && \ - (((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TA1_SET) || \ - ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TA1_RESET) || \ - ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERA_CMP1) || \ - ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERA_CMP2) || \ - ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TB1_SET) || \ - ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TB1_RESET) || \ - ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERB_CMP1) || \ - ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERB_CMP2) || \ - ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TD1_SET) || \ - ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TD1_RESET) || \ - ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERD_CMP1) || \ - ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERD_CMP2) || \ - ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TE1_SET) || \ - ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TE1_RESET) || \ - ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERE_CMP1) || \ - ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERE_CMP2))) \ - || \ + (((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TA1_SET) || \ + ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TA1_RESET) || \ + ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERA_CMP1) || \ + ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERA_CMP2) || \ + ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TB1_SET) || \ + ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TB1_RESET) || \ + ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERB_CMP1) || \ + ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERB_CMP2) || \ + ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TD1_SET) || \ + ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TD1_RESET) || \ + ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERD_CMP1) || \ + ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERD_CMP2) || \ + ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TE1_SET) || \ + ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TE1_RESET) || \ + ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERE_CMP1) || \ + ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERE_CMP2))) \ + || \ (((TIMER) == HRTIM_TIMERINDEX_TIMER_D) && \ - (((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TA1_SET) || \ - ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TA1_RESET) || \ - ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERA_CMP1) || \ - ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERA_CMP2) || \ - ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TB1_SET) || \ - ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TB1_RESET) || \ - ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERB_CMP1) || \ - ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERB_CMP2) || \ - ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TC1_SET) || \ - ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TC1_RESET) || \ - ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERC_CMP1) || \ - ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERC_CMP2) || \ - ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TE1_SET) || \ - ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TE1_RESET) || \ - ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERE_CMP1) || \ - ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERE_CMP2))) \ - || \ + (((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TA1_SET) || \ + ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TA1_RESET) || \ + ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERA_CMP1) || \ + ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERA_CMP2) || \ + ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TB1_SET) || \ + ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TB1_RESET) || \ + ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERB_CMP1) || \ + ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERB_CMP2) || \ + ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TC1_SET) || \ + ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TC1_RESET) || \ + ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERC_CMP1) || \ + ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERC_CMP2) || \ + ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TE1_SET) || \ + ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TE1_RESET) || \ + ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERE_CMP1) || \ + ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERE_CMP2))) \ + || \ (((TIMER) == HRTIM_TIMERINDEX_TIMER_E) && \ - (((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TA1_SET) || \ - ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TA1_RESET) || \ - ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERA_CMP1) || \ - ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERA_CMP2) || \ - ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TB1_SET) || \ - ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TB1_RESET) || \ - ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERB_CMP1) || \ - ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERB_CMP2) || \ - ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TC1_SET) || \ - ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TC1_RESET) || \ - ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERC_CMP1) || \ - ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERC_CMP2) || \ - ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TD1_SET) || \ - ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TD1_RESET) || \ - ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERD_CMP1) || \ - ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERD_CMP2)))) + (((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TA1_SET) || \ + ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TA1_RESET) || \ + ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERA_CMP1) || \ + ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERA_CMP2) || \ + ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TB1_SET) || \ + ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TB1_RESET) || \ + ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERB_CMP1) || \ + ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERB_CMP2) || \ + ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TC1_SET) || \ + ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TC1_RESET) || \ + ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERC_CMP1) || \ + ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERC_CMP2) || \ + ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TD1_SET) || \ + ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TD1_RESET) || \ + ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERD_CMP1) || \ + ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERD_CMP2)))) #define IS_HRTIM_TIMEVENTFILTER(TIMEVENTFILTER)\ - (((TIMEVENTFILTER) == HRTIM_TIMEVENTFILTER_NONE) || \ - ((TIMEVENTFILTER) == HRTIM_TIMEVENTFILTER_BLANKINGCMP1) || \ - ((TIMEVENTFILTER) == HRTIM_TIMEVENTFILTER_BLANKINGCMP2) || \ - ((TIMEVENTFILTER) == HRTIM_TIMEVENTFILTER_BLANKINGCMP3) || \ - ((TIMEVENTFILTER) == HRTIM_TIMEVENTFILTER_BLANKINGCMP4) || \ - ((TIMEVENTFILTER) == HRTIM_TIMEVENTFILTER_BLANKINGFLTR1) || \ - ((TIMEVENTFILTER) == HRTIM_TIMEVENTFILTER_BLANKINGFLTR2) || \ - ((TIMEVENTFILTER) == HRTIM_TIMEVENTFILTER_BLANKINGFLTR3) || \ - ((TIMEVENTFILTER) == HRTIM_TIMEVENTFILTER_BLANKINGFLTR4) || \ - ((TIMEVENTFILTER) == HRTIM_TIMEVENTFILTER_BLANKINGFLTR5) || \ - ((TIMEVENTFILTER) == HRTIM_TIMEVENTFILTER_BLANKINGFLTR6) || \ - ((TIMEVENTFILTER) == HRTIM_TIMEVENTFILTER_BLANKINGFLTR7) || \ - ((TIMEVENTFILTER) == HRTIM_TIMEVENTFILTER_BLANKINGFLTR8) || \ - ((TIMEVENTFILTER) == HRTIM_TIMEVENTFILTER_WINDOWINGCMP2) || \ - ((TIMEVENTFILTER) == HRTIM_TIMEVENTFILTER_WINDOWINGCMP3) || \ - ((TIMEVENTFILTER) == HRTIM_TIMEVENTFILTER_WINDOWINGTIM)) + (((TIMEVENTFILTER) == HRTIM_TIMEVENTFILTER_NONE) || \ + ((TIMEVENTFILTER) == HRTIM_TIMEVENTFILTER_BLANKINGCMP1) || \ + ((TIMEVENTFILTER) == HRTIM_TIMEVENTFILTER_BLANKINGCMP2) || \ + ((TIMEVENTFILTER) == HRTIM_TIMEVENTFILTER_BLANKINGCMP3) || \ + ((TIMEVENTFILTER) == HRTIM_TIMEVENTFILTER_BLANKINGCMP4) || \ + ((TIMEVENTFILTER) == HRTIM_TIMEVENTFILTER_BLANKINGFLTR1) || \ + ((TIMEVENTFILTER) == HRTIM_TIMEVENTFILTER_BLANKINGFLTR2) || \ + ((TIMEVENTFILTER) == HRTIM_TIMEVENTFILTER_BLANKINGFLTR3) || \ + ((TIMEVENTFILTER) == HRTIM_TIMEVENTFILTER_BLANKINGFLTR4) || \ + ((TIMEVENTFILTER) == HRTIM_TIMEVENTFILTER_BLANKINGFLTR5) || \ + ((TIMEVENTFILTER) == HRTIM_TIMEVENTFILTER_BLANKINGFLTR6) || \ + ((TIMEVENTFILTER) == HRTIM_TIMEVENTFILTER_BLANKINGFLTR7) || \ + ((TIMEVENTFILTER) == HRTIM_TIMEVENTFILTER_BLANKINGFLTR8) || \ + ((TIMEVENTFILTER) == HRTIM_TIMEVENTFILTER_WINDOWINGCMP2) || \ + ((TIMEVENTFILTER) == HRTIM_TIMEVENTFILTER_WINDOWINGCMP3) || \ + ((TIMEVENTFILTER) == HRTIM_TIMEVENTFILTER_WINDOWINGTIM)) #define IS_HRTIM_TIMEVENTLATCH(TIMEVENTLATCH)\ - (((TIMEVENTLATCH) == HRTIM_TIMEVENTLATCH_DISABLED) || \ - ((TIMEVENTLATCH) == HRTIM_TIMEVENTLATCH_ENABLED)) + (((TIMEVENTLATCH) == HRTIM_TIMEVENTLATCH_DISABLED) || \ + ((TIMEVENTLATCH) == HRTIM_TIMEVENTLATCH_ENABLED)) #define IS_HRTIM_TIMDEADTIME_PRESCALERRATIO(PRESCALERRATIO)\ - (((PRESCALERRATIO) == HRTIM_TIMDEADTIME_PRESCALERRATIO_MUL8) || \ - ((PRESCALERRATIO) == HRTIM_TIMDEADTIME_PRESCALERRATIO_MUL4) || \ - ((PRESCALERRATIO) == HRTIM_TIMDEADTIME_PRESCALERRATIO_MUL2) || \ - ((PRESCALERRATIO) == HRTIM_TIMDEADTIME_PRESCALERRATIO_DIV1) || \ - ((PRESCALERRATIO) == HRTIM_TIMDEADTIME_PRESCALERRATIO_DIV2) || \ - ((PRESCALERRATIO) == HRTIM_TIMDEADTIME_PRESCALERRATIO_DIV4) || \ - ((PRESCALERRATIO) == HRTIM_TIMDEADTIME_PRESCALERRATIO_DIV8) || \ - ((PRESCALERRATIO) == HRTIM_TIMDEADTIME_PRESCALERRATIO_DIV16)) + (((PRESCALERRATIO) == HRTIM_TIMDEADTIME_PRESCALERRATIO_MUL8) || \ + ((PRESCALERRATIO) == HRTIM_TIMDEADTIME_PRESCALERRATIO_MUL4) || \ + ((PRESCALERRATIO) == HRTIM_TIMDEADTIME_PRESCALERRATIO_MUL2) || \ + ((PRESCALERRATIO) == HRTIM_TIMDEADTIME_PRESCALERRATIO_DIV1) || \ + ((PRESCALERRATIO) == HRTIM_TIMDEADTIME_PRESCALERRATIO_DIV2) || \ + ((PRESCALERRATIO) == HRTIM_TIMDEADTIME_PRESCALERRATIO_DIV4) || \ + ((PRESCALERRATIO) == HRTIM_TIMDEADTIME_PRESCALERRATIO_DIV8) || \ + ((PRESCALERRATIO) == HRTIM_TIMDEADTIME_PRESCALERRATIO_DIV16)) #define IS_HRTIM_TIMDEADTIME_RISINGSIGN(RISINGSIGN)\ - (((RISINGSIGN) == HRTIM_TIMDEADTIME_RISINGSIGN_POSITIVE) || \ - ((RISINGSIGN) == HRTIM_TIMDEADTIME_RISINGSIGN_NEGATIVE)) + (((RISINGSIGN) == HRTIM_TIMDEADTIME_RISINGSIGN_POSITIVE) || \ + ((RISINGSIGN) == HRTIM_TIMDEADTIME_RISINGSIGN_NEGATIVE)) #define IS_HRTIM_TIMDEADTIME_RISINGLOCK(RISINGLOCK)\ - (((RISINGLOCK) == HRTIM_TIMDEADTIME_RISINGLOCK_WRITE) || \ - ((RISINGLOCK) == HRTIM_TIMDEADTIME_RISINGLOCK_READONLY)) + (((RISINGLOCK) == HRTIM_TIMDEADTIME_RISINGLOCK_WRITE) || \ + ((RISINGLOCK) == HRTIM_TIMDEADTIME_RISINGLOCK_READONLY)) #define IS_HRTIM_TIMDEADTIME_RISINGSIGNLOCK(RISINGSIGNLOCK)\ - (((RISINGSIGNLOCK) == HRTIM_TIMDEADTIME_RISINGSIGNLOCK_WRITE) || \ - ((RISINGSIGNLOCK) == HRTIM_TIMDEADTIME_RISINGSIGNLOCK_READONLY)) + (((RISINGSIGNLOCK) == HRTIM_TIMDEADTIME_RISINGSIGNLOCK_WRITE) || \ + ((RISINGSIGNLOCK) == HRTIM_TIMDEADTIME_RISINGSIGNLOCK_READONLY)) #define IS_HRTIM_TIMDEADTIME_FALLINGSIGN(FALLINGSIGN)\ - (((FALLINGSIGN) == HRTIM_TIMDEADTIME_FALLINGSIGN_POSITIVE) || \ - ((FALLINGSIGN) == HRTIM_TIMDEADTIME_FALLINGSIGN_NEGATIVE)) + (((FALLINGSIGN) == HRTIM_TIMDEADTIME_FALLINGSIGN_POSITIVE) || \ + ((FALLINGSIGN) == HRTIM_TIMDEADTIME_FALLINGSIGN_NEGATIVE)) #define IS_HRTIM_TIMDEADTIME_FALLINGLOCK(FALLINGLOCK)\ - (((FALLINGLOCK) == HRTIM_TIMDEADTIME_FALLINGLOCK_WRITE) || \ - ((FALLINGLOCK) == HRTIM_TIMDEADTIME_FALLINGLOCK_READONLY)) + (((FALLINGLOCK) == HRTIM_TIMDEADTIME_FALLINGLOCK_WRITE) || \ + ((FALLINGLOCK) == HRTIM_TIMDEADTIME_FALLINGLOCK_READONLY)) #define IS_HRTIM_TIMDEADTIME_FALLINGSIGNLOCK(FALLINGSIGNLOCK)\ - (((FALLINGSIGNLOCK) == HRTIM_TIMDEADTIME_FALLINGSIGNLOCK_WRITE) || \ - ((FALLINGSIGNLOCK) == HRTIM_TIMDEADTIME_FALLINGSIGNLOCK_READONLY)) + (((FALLINGSIGNLOCK) == HRTIM_TIMDEADTIME_FALLINGSIGNLOCK_WRITE) || \ + ((FALLINGSIGNLOCK) == HRTIM_TIMDEADTIME_FALLINGSIGNLOCK_READONLY)) #define IS_HRTIM_CHOPPER_PRESCALERRATIO(PRESCALERRATIO)\ - (((PRESCALERRATIO) == HRTIM_CHOPPER_PRESCALERRATIO_DIV16) || \ - ((PRESCALERRATIO) == HRTIM_CHOPPER_PRESCALERRATIO_DIV32) || \ - ((PRESCALERRATIO) == HRTIM_CHOPPER_PRESCALERRATIO_DIV48) || \ - ((PRESCALERRATIO) == HRTIM_CHOPPER_PRESCALERRATIO_DIV64) || \ - ((PRESCALERRATIO) == HRTIM_CHOPPER_PRESCALERRATIO_DIV80) || \ - ((PRESCALERRATIO) == HRTIM_CHOPPER_PRESCALERRATIO_DIV96) || \ - ((PRESCALERRATIO) == HRTIM_CHOPPER_PRESCALERRATIO_DIV112) || \ - ((PRESCALERRATIO) == HRTIM_CHOPPER_PRESCALERRATIO_DIV128) || \ - ((PRESCALERRATIO) == HRTIM_CHOPPER_PRESCALERRATIO_DIV144) || \ - ((PRESCALERRATIO) == HRTIM_CHOPPER_PRESCALERRATIO_DIV160) || \ - ((PRESCALERRATIO) == HRTIM_CHOPPER_PRESCALERRATIO_DIV176) || \ - ((PRESCALERRATIO) == HRTIM_CHOPPER_PRESCALERRATIO_DIV192) || \ - ((PRESCALERRATIO) == HRTIM_CHOPPER_PRESCALERRATIO_DIV208) || \ - ((PRESCALERRATIO) == HRTIM_CHOPPER_PRESCALERRATIO_DIV224) || \ - ((PRESCALERRATIO) == HRTIM_CHOPPER_PRESCALERRATIO_DIV240) || \ - ((PRESCALERRATIO) == HRTIM_CHOPPER_PRESCALERRATIO_DIV256)) + (((PRESCALERRATIO) == HRTIM_CHOPPER_PRESCALERRATIO_DIV16) || \ + ((PRESCALERRATIO) == HRTIM_CHOPPER_PRESCALERRATIO_DIV32) || \ + ((PRESCALERRATIO) == HRTIM_CHOPPER_PRESCALERRATIO_DIV48) || \ + ((PRESCALERRATIO) == HRTIM_CHOPPER_PRESCALERRATIO_DIV64) || \ + ((PRESCALERRATIO) == HRTIM_CHOPPER_PRESCALERRATIO_DIV80) || \ + ((PRESCALERRATIO) == HRTIM_CHOPPER_PRESCALERRATIO_DIV96) || \ + ((PRESCALERRATIO) == HRTIM_CHOPPER_PRESCALERRATIO_DIV112) || \ + ((PRESCALERRATIO) == HRTIM_CHOPPER_PRESCALERRATIO_DIV128) || \ + ((PRESCALERRATIO) == HRTIM_CHOPPER_PRESCALERRATIO_DIV144) || \ + ((PRESCALERRATIO) == HRTIM_CHOPPER_PRESCALERRATIO_DIV160) || \ + ((PRESCALERRATIO) == HRTIM_CHOPPER_PRESCALERRATIO_DIV176) || \ + ((PRESCALERRATIO) == HRTIM_CHOPPER_PRESCALERRATIO_DIV192) || \ + ((PRESCALERRATIO) == HRTIM_CHOPPER_PRESCALERRATIO_DIV208) || \ + ((PRESCALERRATIO) == HRTIM_CHOPPER_PRESCALERRATIO_DIV224) || \ + ((PRESCALERRATIO) == HRTIM_CHOPPER_PRESCALERRATIO_DIV240) || \ + ((PRESCALERRATIO) == HRTIM_CHOPPER_PRESCALERRATIO_DIV256)) #define IS_HRTIM_CHOPPER_DUTYCYCLE(DUTYCYCLE)\ - (((DUTYCYCLE) == HRTIM_CHOPPER_DUTYCYCLE_0) || \ - ((DUTYCYCLE) == HRTIM_CHOPPER_DUTYCYCLE_125) || \ - ((DUTYCYCLE) == HRTIM_CHOPPER_DUTYCYCLE_250) || \ - ((DUTYCYCLE) == HRTIM_CHOPPER_DUTYCYCLE_375) || \ - ((DUTYCYCLE) == HRTIM_CHOPPER_DUTYCYCLE_500) || \ - ((DUTYCYCLE) == HRTIM_CHOPPER_DUTYCYCLE_625) || \ - ((DUTYCYCLE) == HRTIM_CHOPPER_DUTYCYCLE_750) || \ - ((DUTYCYCLE) == HRTIM_CHOPPER_DUTYCYCLE_875)) + (((DUTYCYCLE) == HRTIM_CHOPPER_DUTYCYCLE_0) || \ + ((DUTYCYCLE) == HRTIM_CHOPPER_DUTYCYCLE_125) || \ + ((DUTYCYCLE) == HRTIM_CHOPPER_DUTYCYCLE_250) || \ + ((DUTYCYCLE) == HRTIM_CHOPPER_DUTYCYCLE_375) || \ + ((DUTYCYCLE) == HRTIM_CHOPPER_DUTYCYCLE_500) || \ + ((DUTYCYCLE) == HRTIM_CHOPPER_DUTYCYCLE_625) || \ + ((DUTYCYCLE) == HRTIM_CHOPPER_DUTYCYCLE_750) || \ + ((DUTYCYCLE) == HRTIM_CHOPPER_DUTYCYCLE_875)) #define IS_HRTIM_CHOPPER_PULSEWIDTH(PULSEWIDTH)\ - (((PULSEWIDTH) == HRTIM_CHOPPER_PULSEWIDTH_16) || \ - ((PULSEWIDTH) == HRTIM_CHOPPER_PULSEWIDTH_32) || \ - ((PULSEWIDTH) == HRTIM_CHOPPER_PULSEWIDTH_48) || \ - ((PULSEWIDTH) == HRTIM_CHOPPER_PULSEWIDTH_64) || \ - ((PULSEWIDTH) == HRTIM_CHOPPER_PULSEWIDTH_80) || \ - ((PULSEWIDTH) == HRTIM_CHOPPER_PULSEWIDTH_96) || \ - ((PULSEWIDTH) == HRTIM_CHOPPER_PULSEWIDTH_112) || \ - ((PULSEWIDTH) == HRTIM_CHOPPER_PULSEWIDTH_128) || \ - ((PULSEWIDTH) == HRTIM_CHOPPER_PULSEWIDTH_144) || \ - ((PULSEWIDTH) == HRTIM_CHOPPER_PULSEWIDTH_160) || \ - ((PULSEWIDTH) == HRTIM_CHOPPER_PULSEWIDTH_176) || \ - ((PULSEWIDTH) == HRTIM_CHOPPER_PULSEWIDTH_192) || \ - ((PULSEWIDTH) == HRTIM_CHOPPER_PULSEWIDTH_208) || \ - ((PULSEWIDTH) == HRTIM_CHOPPER_PULSEWIDTH_224) || \ - ((PULSEWIDTH) == HRTIM_CHOPPER_PULSEWIDTH_240) || \ - ((PULSEWIDTH) == HRTIM_CHOPPER_PULSEWIDTH_256)) + (((PULSEWIDTH) == HRTIM_CHOPPER_PULSEWIDTH_16) || \ + ((PULSEWIDTH) == HRTIM_CHOPPER_PULSEWIDTH_32) || \ + ((PULSEWIDTH) == HRTIM_CHOPPER_PULSEWIDTH_48) || \ + ((PULSEWIDTH) == HRTIM_CHOPPER_PULSEWIDTH_64) || \ + ((PULSEWIDTH) == HRTIM_CHOPPER_PULSEWIDTH_80) || \ + ((PULSEWIDTH) == HRTIM_CHOPPER_PULSEWIDTH_96) || \ + ((PULSEWIDTH) == HRTIM_CHOPPER_PULSEWIDTH_112) || \ + ((PULSEWIDTH) == HRTIM_CHOPPER_PULSEWIDTH_128) || \ + ((PULSEWIDTH) == HRTIM_CHOPPER_PULSEWIDTH_144) || \ + ((PULSEWIDTH) == HRTIM_CHOPPER_PULSEWIDTH_160) || \ + ((PULSEWIDTH) == HRTIM_CHOPPER_PULSEWIDTH_176) || \ + ((PULSEWIDTH) == HRTIM_CHOPPER_PULSEWIDTH_192) || \ + ((PULSEWIDTH) == HRTIM_CHOPPER_PULSEWIDTH_208) || \ + ((PULSEWIDTH) == HRTIM_CHOPPER_PULSEWIDTH_224) || \ + ((PULSEWIDTH) == HRTIM_CHOPPER_PULSEWIDTH_240) || \ + ((PULSEWIDTH) == HRTIM_CHOPPER_PULSEWIDTH_256)) #define IS_HRTIM_SYNCINPUTSOURCE(SYNCINPUTSOURCE)\ - (((SYNCINPUTSOURCE) == HRTIM_SYNCINPUTSOURCE_NONE) || \ - ((SYNCINPUTSOURCE) == HRTIM_SYNCINPUTSOURCE_INTERNALEVENT) || \ - ((SYNCINPUTSOURCE) == HRTIM_SYNCINPUTSOURCE_EXTERNALEVENT)) + (((SYNCINPUTSOURCE) == HRTIM_SYNCINPUTSOURCE_NONE) || \ + ((SYNCINPUTSOURCE) == HRTIM_SYNCINPUTSOURCE_INTERNALEVENT) || \ + ((SYNCINPUTSOURCE) == HRTIM_SYNCINPUTSOURCE_EXTERNALEVENT)) #define IS_HRTIM_SYNCOUTPUTSOURCE(SYNCOUTPUTSOURCE)\ - (((SYNCOUTPUTSOURCE) == HRTIM_SYNCOUTPUTSOURCE_MASTER_START) || \ - ((SYNCOUTPUTSOURCE) == HRTIM_SYNCOUTPUTSOURCE_MASTER_CMP1) || \ - ((SYNCOUTPUTSOURCE) == HRTIM_SYNCOUTPUTSOURCE_TIMA_START) || \ - ((SYNCOUTPUTSOURCE) == HRTIM_SYNCOUTPUTSOURCE_TIMA_CMP1)) + (((SYNCOUTPUTSOURCE) == HRTIM_SYNCOUTPUTSOURCE_MASTER_START) || \ + ((SYNCOUTPUTSOURCE) == HRTIM_SYNCOUTPUTSOURCE_MASTER_CMP1) || \ + ((SYNCOUTPUTSOURCE) == HRTIM_SYNCOUTPUTSOURCE_TIMA_START) || \ + ((SYNCOUTPUTSOURCE) == HRTIM_SYNCOUTPUTSOURCE_TIMA_CMP1)) #define IS_HRTIM_SYNCOUTPUTPOLARITY(SYNCOUTPUTPOLARITY)\ - (((SYNCOUTPUTPOLARITY) == HRTIM_SYNCOUTPUTPOLARITY_NONE) || \ - ((SYNCOUTPUTPOLARITY) == HRTIM_SYNCOUTPUTPOLARITY_POSITIVE) || \ - ((SYNCOUTPUTPOLARITY) == HRTIM_SYNCOUTPUTPOLARITY_NEGATIVE)) + (((SYNCOUTPUTPOLARITY) == HRTIM_SYNCOUTPUTPOLARITY_NONE) || \ + ((SYNCOUTPUTPOLARITY) == HRTIM_SYNCOUTPUTPOLARITY_POSITIVE) || \ + ((SYNCOUTPUTPOLARITY) == HRTIM_SYNCOUTPUTPOLARITY_NEGATIVE)) #define IS_HRTIM_EVENTSRC(EVENTSRC)\ - (((EVENTSRC) == HRTIM_EVENTSRC_1) || \ - ((EVENTSRC) == HRTIM_EVENTSRC_2) || \ - ((EVENTSRC) == HRTIM_EVENTSRC_3) || \ - ((EVENTSRC) == HRTIM_EVENTSRC_4)) + (((EVENTSRC) == HRTIM_EVENTSRC_1) || \ + ((EVENTSRC) == HRTIM_EVENTSRC_2) || \ + ((EVENTSRC) == HRTIM_EVENTSRC_3) || \ + ((EVENTSRC) == HRTIM_EVENTSRC_4)) #define IS_HRTIM_EVENTPOLARITY(EVENTSENSITIVITY, EVENTPOLARITY)\ - ((((EVENTSENSITIVITY) == HRTIM_EVENTSENSITIVITY_LEVEL) && \ - (((EVENTPOLARITY) == HRTIM_EVENTPOLARITY_HIGH) || \ - ((EVENTPOLARITY) == HRTIM_EVENTPOLARITY_LOW))) \ - || \ - (((EVENTSENSITIVITY) == HRTIM_EVENTSENSITIVITY_RISINGEDGE) || \ - ((EVENTSENSITIVITY) == HRTIM_EVENTSENSITIVITY_FALLINGEDGE)|| \ - ((EVENTSENSITIVITY) == HRTIM_EVENTSENSITIVITY_BOTHEDGES))) + ((((EVENTSENSITIVITY) == HRTIM_EVENTSENSITIVITY_LEVEL) && \ + (((EVENTPOLARITY) == HRTIM_EVENTPOLARITY_HIGH) || \ + ((EVENTPOLARITY) == HRTIM_EVENTPOLARITY_LOW))) \ + || \ + (((EVENTSENSITIVITY) == HRTIM_EVENTSENSITIVITY_RISINGEDGE) || \ + ((EVENTSENSITIVITY) == HRTIM_EVENTSENSITIVITY_FALLINGEDGE)|| \ + ((EVENTSENSITIVITY) == HRTIM_EVENTSENSITIVITY_BOTHEDGES))) #define IS_HRTIM_EVENTSENSITIVITY(EVENTSENSITIVITY)\ - (((EVENTSENSITIVITY) == HRTIM_EVENTSENSITIVITY_LEVEL) || \ - ((EVENTSENSITIVITY) == HRTIM_EVENTSENSITIVITY_RISINGEDGE) || \ - ((EVENTSENSITIVITY) == HRTIM_EVENTSENSITIVITY_FALLINGEDGE) || \ - ((EVENTSENSITIVITY) == HRTIM_EVENTSENSITIVITY_BOTHEDGES)) + (((EVENTSENSITIVITY) == HRTIM_EVENTSENSITIVITY_LEVEL) || \ + ((EVENTSENSITIVITY) == HRTIM_EVENTSENSITIVITY_RISINGEDGE) || \ + ((EVENTSENSITIVITY) == HRTIM_EVENTSENSITIVITY_FALLINGEDGE) || \ + ((EVENTSENSITIVITY) == HRTIM_EVENTSENSITIVITY_BOTHEDGES)) #define IS_HRTIM_EVENTFASTMODE(EVENT, FASTMODE)\ - (((((EVENT) == HRTIM_EVENT_1) || \ - ((EVENT) == HRTIM_EVENT_2) || \ - ((EVENT) == HRTIM_EVENT_3) || \ - ((EVENT) == HRTIM_EVENT_4) || \ - ((EVENT) == HRTIM_EVENT_5)) && \ - (((FASTMODE) == HRTIM_EVENTFASTMODE_ENABLE) || \ - ((FASTMODE) == HRTIM_EVENTFASTMODE_DISABLE))) \ - || \ - (((EVENT) == HRTIM_EVENT_6) || \ - ((EVENT) == HRTIM_EVENT_7) || \ - ((EVENT) == HRTIM_EVENT_8) || \ - ((EVENT) == HRTIM_EVENT_9) || \ - ((EVENT) == HRTIM_EVENT_10))) + (((((EVENT) == HRTIM_EVENT_1) || \ + ((EVENT) == HRTIM_EVENT_2) || \ + ((EVENT) == HRTIM_EVENT_3) || \ + ((EVENT) == HRTIM_EVENT_4) || \ + ((EVENT) == HRTIM_EVENT_5)) && \ + (((FASTMODE) == HRTIM_EVENTFASTMODE_ENABLE) || \ + ((FASTMODE) == HRTIM_EVENTFASTMODE_DISABLE))) \ + || \ + (((EVENT) == HRTIM_EVENT_6) || \ + ((EVENT) == HRTIM_EVENT_7) || \ + ((EVENT) == HRTIM_EVENT_8) || \ + ((EVENT) == HRTIM_EVENT_9) || \ + ((EVENT) == HRTIM_EVENT_10))) #define IS_HRTIM_EVENTFILTER(EVENT, FILTER)\ - ((((EVENT) == HRTIM_EVENT_1) || \ - ((EVENT) == HRTIM_EVENT_2) || \ - ((EVENT) == HRTIM_EVENT_3) || \ - ((EVENT) == HRTIM_EVENT_4) || \ - ((EVENT) == HRTIM_EVENT_5)) \ - || \ - ((((EVENT) == HRTIM_EVENT_6) || \ - ((EVENT) == HRTIM_EVENT_7) || \ - ((EVENT) == HRTIM_EVENT_8) || \ - ((EVENT) == HRTIM_EVENT_9) || \ - ((EVENT) == HRTIM_EVENT_10)) && \ - (((FILTER) == HRTIM_EVENTFILTER_NONE) || \ - ((FILTER) == HRTIM_EVENTFILTER_1) || \ - ((FILTER) == HRTIM_EVENTFILTER_2) || \ - ((FILTER) == HRTIM_EVENTFILTER_3) || \ - ((FILTER) == HRTIM_EVENTFILTER_4) || \ - ((FILTER) == HRTIM_EVENTFILTER_5) || \ - ((FILTER) == HRTIM_EVENTFILTER_6) || \ - ((FILTER) == HRTIM_EVENTFILTER_7) || \ - ((FILTER) == HRTIM_EVENTFILTER_8) || \ - ((FILTER) == HRTIM_EVENTFILTER_9) || \ - ((FILTER) == HRTIM_EVENTFILTER_10) || \ - ((FILTER) == HRTIM_EVENTFILTER_11) || \ - ((FILTER) == HRTIM_EVENTFILTER_12) || \ - ((FILTER) == HRTIM_EVENTFILTER_13) || \ - ((FILTER) == HRTIM_EVENTFILTER_14) || \ - ((FILTER) == HRTIM_EVENTFILTER_15)))) + ((((EVENT) == HRTIM_EVENT_1) || \ + ((EVENT) == HRTIM_EVENT_2) || \ + ((EVENT) == HRTIM_EVENT_3) || \ + ((EVENT) == HRTIM_EVENT_4) || \ + ((EVENT) == HRTIM_EVENT_5)) \ + || \ + ((((EVENT) == HRTIM_EVENT_6) || \ + ((EVENT) == HRTIM_EVENT_7) || \ + ((EVENT) == HRTIM_EVENT_8) || \ + ((EVENT) == HRTIM_EVENT_9) || \ + ((EVENT) == HRTIM_EVENT_10)) && \ + (((FILTER) == HRTIM_EVENTFILTER_NONE) || \ + ((FILTER) == HRTIM_EVENTFILTER_1) || \ + ((FILTER) == HRTIM_EVENTFILTER_2) || \ + ((FILTER) == HRTIM_EVENTFILTER_3) || \ + ((FILTER) == HRTIM_EVENTFILTER_4) || \ + ((FILTER) == HRTIM_EVENTFILTER_5) || \ + ((FILTER) == HRTIM_EVENTFILTER_6) || \ + ((FILTER) == HRTIM_EVENTFILTER_7) || \ + ((FILTER) == HRTIM_EVENTFILTER_8) || \ + ((FILTER) == HRTIM_EVENTFILTER_9) || \ + ((FILTER) == HRTIM_EVENTFILTER_10) || \ + ((FILTER) == HRTIM_EVENTFILTER_11) || \ + ((FILTER) == HRTIM_EVENTFILTER_12) || \ + ((FILTER) == HRTIM_EVENTFILTER_13) || \ + ((FILTER) == HRTIM_EVENTFILTER_14) || \ + ((FILTER) == HRTIM_EVENTFILTER_15)))) #define IS_HRTIM_EVENTPRESCALER(EVENTPRESCALER)\ - (((EVENTPRESCALER) == HRTIM_EVENTPRESCALER_DIV1) || \ - ((EVENTPRESCALER) == HRTIM_EVENTPRESCALER_DIV2) || \ - ((EVENTPRESCALER) == HRTIM_EVENTPRESCALER_DIV4) || \ - ((EVENTPRESCALER) == HRTIM_EVENTPRESCALER_DIV8)) + (((EVENTPRESCALER) == HRTIM_EVENTPRESCALER_DIV1) || \ + ((EVENTPRESCALER) == HRTIM_EVENTPRESCALER_DIV2) || \ + ((EVENTPRESCALER) == HRTIM_EVENTPRESCALER_DIV4) || \ + ((EVENTPRESCALER) == HRTIM_EVENTPRESCALER_DIV8)) #define IS_HRTIM_FAULTSOURCE(FAULTSOURCE)\ - (((FAULTSOURCE) == HRTIM_FAULTSOURCE_DIGITALINPUT) || \ - ((FAULTSOURCE) == HRTIM_FAULTSOURCE_INTERNAL)) + (((FAULTSOURCE) == HRTIM_FAULTSOURCE_DIGITALINPUT) || \ + ((FAULTSOURCE) == HRTIM_FAULTSOURCE_INTERNAL)) #define IS_HRTIM_FAULTPOLARITY(HRTIM_FAULTPOLARITY)\ - (((HRTIM_FAULTPOLARITY) == HRTIM_FAULTPOLARITY_LOW) || \ - ((HRTIM_FAULTPOLARITY) == HRTIM_FAULTPOLARITY_HIGH)) + (((HRTIM_FAULTPOLARITY) == HRTIM_FAULTPOLARITY_LOW) || \ + ((HRTIM_FAULTPOLARITY) == HRTIM_FAULTPOLARITY_HIGH)) #define IS_HRTIM_FAULTMODECTL(FAULTMODECTL)\ - (((FAULTMODECTL) == HRTIM_FAULTMODECTL_DISABLED) || \ - ((FAULTMODECTL) == HRTIM_FAULTMODECTL_ENABLED)) + (((FAULTMODECTL) == HRTIM_FAULTMODECTL_DISABLED) || \ + ((FAULTMODECTL) == HRTIM_FAULTMODECTL_ENABLED)) #define IS_HRTIM_FAULTFILTER(FAULTFILTER)\ - (((FAULTFILTER) == HRTIM_FAULTFILTER_NONE) || \ - ((FAULTFILTER) == HRTIM_FAULTFILTER_1) || \ - ((FAULTFILTER) == HRTIM_FAULTFILTER_2) || \ - ((FAULTFILTER) == HRTIM_FAULTFILTER_3) || \ - ((FAULTFILTER) == HRTIM_FAULTFILTER_4) || \ - ((FAULTFILTER) == HRTIM_FAULTFILTER_5) || \ - ((FAULTFILTER) == HRTIM_FAULTFILTER_6) || \ - ((FAULTFILTER) == HRTIM_FAULTFILTER_7) || \ - ((FAULTFILTER) == HRTIM_FAULTFILTER_8) || \ - ((FAULTFILTER) == HRTIM_FAULTFILTER_9) || \ - ((FAULTFILTER) == HRTIM_FAULTFILTER_10) || \ - ((FAULTFILTER) == HRTIM_FAULTFILTER_11) || \ - ((FAULTFILTER) == HRTIM_FAULTFILTER_12) || \ - ((FAULTFILTER) == HRTIM_FAULTFILTER_13) || \ - ((FAULTFILTER) == HRTIM_FAULTFILTER_14) || \ - ((FAULTFILTER) == HRTIM_FAULTFILTER_15)) + (((FAULTFILTER) == HRTIM_FAULTFILTER_NONE) || \ + ((FAULTFILTER) == HRTIM_FAULTFILTER_1) || \ + ((FAULTFILTER) == HRTIM_FAULTFILTER_2) || \ + ((FAULTFILTER) == HRTIM_FAULTFILTER_3) || \ + ((FAULTFILTER) == HRTIM_FAULTFILTER_4) || \ + ((FAULTFILTER) == HRTIM_FAULTFILTER_5) || \ + ((FAULTFILTER) == HRTIM_FAULTFILTER_6) || \ + ((FAULTFILTER) == HRTIM_FAULTFILTER_7) || \ + ((FAULTFILTER) == HRTIM_FAULTFILTER_8) || \ + ((FAULTFILTER) == HRTIM_FAULTFILTER_9) || \ + ((FAULTFILTER) == HRTIM_FAULTFILTER_10) || \ + ((FAULTFILTER) == HRTIM_FAULTFILTER_11) || \ + ((FAULTFILTER) == HRTIM_FAULTFILTER_12) || \ + ((FAULTFILTER) == HRTIM_FAULTFILTER_13) || \ + ((FAULTFILTER) == HRTIM_FAULTFILTER_14) || \ + ((FAULTFILTER) == HRTIM_FAULTFILTER_15)) #define IS_HRTIM_FAULTLOCK(FAULTLOCK)\ - (((FAULTLOCK) == HRTIM_FAULTLOCK_READWRITE) || \ - ((FAULTLOCK) == HRTIM_FAULTLOCK_READONLY)) + (((FAULTLOCK) == HRTIM_FAULTLOCK_READWRITE) || \ + ((FAULTLOCK) == HRTIM_FAULTLOCK_READONLY)) #define IS_HRTIM_FAULTPRESCALER(FAULTPRESCALER)\ - (((FAULTPRESCALER) == HRTIM_FAULTPRESCALER_DIV1) || \ - ((FAULTPRESCALER) == HRTIM_FAULTPRESCALER_DIV2) || \ - ((FAULTPRESCALER) == HRTIM_FAULTPRESCALER_DIV4) || \ - ((FAULTPRESCALER) == HRTIM_FAULTPRESCALER_DIV8)) + (((FAULTPRESCALER) == HRTIM_FAULTPRESCALER_DIV1) || \ + ((FAULTPRESCALER) == HRTIM_FAULTPRESCALER_DIV2) || \ + ((FAULTPRESCALER) == HRTIM_FAULTPRESCALER_DIV4) || \ + ((FAULTPRESCALER) == HRTIM_FAULTPRESCALER_DIV8)) #define IS_HRTIM_BURSTMODE(BURSTMODE)\ - (((BURSTMODE) == HRTIM_BURSTMODE_SINGLESHOT) || \ - ((BURSTMODE) == HRTIM_BURSTMODE_CONTINOUS)) + (((BURSTMODE) == HRTIM_BURSTMODE_SINGLESHOT) || \ + ((BURSTMODE) == HRTIM_BURSTMODE_CONTINOUS)) #define IS_HRTIM_BURSTMODECLOCKSOURCE(BURSTMODECLOCKSOURCE)\ - (((BURSTMODECLOCKSOURCE) == HRTIM_BURSTMODECLOCKSOURCE_MASTER) || \ - ((BURSTMODECLOCKSOURCE) == HRTIM_BURSTMODECLOCKSOURCE_TIMER_A) || \ - ((BURSTMODECLOCKSOURCE) == HRTIM_BURSTMODECLOCKSOURCE_TIMER_B) || \ - ((BURSTMODECLOCKSOURCE) == HRTIM_BURSTMODECLOCKSOURCE_TIMER_C) || \ - ((BURSTMODECLOCKSOURCE) == HRTIM_BURSTMODECLOCKSOURCE_TIMER_D) || \ - ((BURSTMODECLOCKSOURCE) == HRTIM_BURSTMODECLOCKSOURCE_TIMER_E) || \ - ((BURSTMODECLOCKSOURCE) == HRTIM_BURSTMODECLOCKSOURCE_TIM16_OC) || \ - ((BURSTMODECLOCKSOURCE) == HRTIM_BURSTMODECLOCKSOURCE_TIM17_OC) || \ - ((BURSTMODECLOCKSOURCE) == HRTIM_BURSTMODECLOCKSOURCE_TIM7_TRGO) || \ - ((BURSTMODECLOCKSOURCE) == HRTIM_BURSTMODECLOCKSOURCE_FHRTIM)) + (((BURSTMODECLOCKSOURCE) == HRTIM_BURSTMODECLOCKSOURCE_MASTER) || \ + ((BURSTMODECLOCKSOURCE) == HRTIM_BURSTMODECLOCKSOURCE_TIMER_A) || \ + ((BURSTMODECLOCKSOURCE) == HRTIM_BURSTMODECLOCKSOURCE_TIMER_B) || \ + ((BURSTMODECLOCKSOURCE) == HRTIM_BURSTMODECLOCKSOURCE_TIMER_C) || \ + ((BURSTMODECLOCKSOURCE) == HRTIM_BURSTMODECLOCKSOURCE_TIMER_D) || \ + ((BURSTMODECLOCKSOURCE) == HRTIM_BURSTMODECLOCKSOURCE_TIMER_E) || \ + ((BURSTMODECLOCKSOURCE) == HRTIM_BURSTMODECLOCKSOURCE_TIM16_OC) || \ + ((BURSTMODECLOCKSOURCE) == HRTIM_BURSTMODECLOCKSOURCE_TIM17_OC) || \ + ((BURSTMODECLOCKSOURCE) == HRTIM_BURSTMODECLOCKSOURCE_TIM7_TRGO) || \ + ((BURSTMODECLOCKSOURCE) == HRTIM_BURSTMODECLOCKSOURCE_FHRTIM)) #define IS_HRTIM_HRTIM_BURSTMODEPRESCALER(BURSTMODEPRESCALER)\ - (((BURSTMODEPRESCALER) == HRTIM_BURSTMODEPRESCALER_DIV1) || \ - ((BURSTMODEPRESCALER) == HRTIM_BURSTMODEPRESCALER_DIV2) || \ - ((BURSTMODEPRESCALER) == HRTIM_BURSTMODEPRESCALER_DIV4) || \ - ((BURSTMODEPRESCALER) == HRTIM_BURSTMODEPRESCALER_DIV8) || \ - ((BURSTMODEPRESCALER) == HRTIM_BURSTMODEPRESCALER_DIV16) || \ - ((BURSTMODEPRESCALER) == HRTIM_BURSTMODEPRESCALER_DIV32) || \ - ((BURSTMODEPRESCALER) == HRTIM_BURSTMODEPRESCALER_DIV64) || \ - ((BURSTMODEPRESCALER) == HRTIM_BURSTMODEPRESCALER_DIV128) || \ - ((BURSTMODEPRESCALER) == HRTIM_BURSTMODEPRESCALER_DIV256) || \ - ((BURSTMODEPRESCALER) == HRTIM_BURSTMODEPRESCALER_DIV512) || \ - ((BURSTMODEPRESCALER) == HRTIM_BURSTMODEPRESCALER_DIV1024) || \ - ((BURSTMODEPRESCALER) == HRTIM_BURSTMODEPRESCALER_DIV2048) || \ - ((BURSTMODEPRESCALER) == HRTIM_BURSTMODEPRESCALER_DIV4096) || \ - ((BURSTMODEPRESCALER) == HRTIM_BURSTMODEPRESCALER_DIV8192) || \ - ((BURSTMODEPRESCALER) == HRTIM_BURSTMODEPRESCALER_DIV16384) || \ - ((BURSTMODEPRESCALER) == HRTIM_BURSTMODEPRESCALER_DIV32768)) + (((BURSTMODEPRESCALER) == HRTIM_BURSTMODEPRESCALER_DIV1) || \ + ((BURSTMODEPRESCALER) == HRTIM_BURSTMODEPRESCALER_DIV2) || \ + ((BURSTMODEPRESCALER) == HRTIM_BURSTMODEPRESCALER_DIV4) || \ + ((BURSTMODEPRESCALER) == HRTIM_BURSTMODEPRESCALER_DIV8) || \ + ((BURSTMODEPRESCALER) == HRTIM_BURSTMODEPRESCALER_DIV16) || \ + ((BURSTMODEPRESCALER) == HRTIM_BURSTMODEPRESCALER_DIV32) || \ + ((BURSTMODEPRESCALER) == HRTIM_BURSTMODEPRESCALER_DIV64) || \ + ((BURSTMODEPRESCALER) == HRTIM_BURSTMODEPRESCALER_DIV128) || \ + ((BURSTMODEPRESCALER) == HRTIM_BURSTMODEPRESCALER_DIV256) || \ + ((BURSTMODEPRESCALER) == HRTIM_BURSTMODEPRESCALER_DIV512) || \ + ((BURSTMODEPRESCALER) == HRTIM_BURSTMODEPRESCALER_DIV1024) || \ + ((BURSTMODEPRESCALER) == HRTIM_BURSTMODEPRESCALER_DIV2048) || \ + ((BURSTMODEPRESCALER) == HRTIM_BURSTMODEPRESCALER_DIV4096) || \ + ((BURSTMODEPRESCALER) == HRTIM_BURSTMODEPRESCALER_DIV8192) || \ + ((BURSTMODEPRESCALER) == HRTIM_BURSTMODEPRESCALER_DIV16384) || \ + ((BURSTMODEPRESCALER) == HRTIM_BURSTMODEPRESCALER_DIV32768)) #define IS_HRTIM_BURSTMODEPRELOAD(BURSTMODEPRELOAD)\ - (((BURSTMODEPRELOAD) == HRIM_BURSTMODEPRELOAD_DISABLED) || \ - ((BURSTMODEPRELOAD) == HRIM_BURSTMODEPRELOAD_ENABLED)) + (((BURSTMODEPRELOAD) == HRIM_BURSTMODEPRELOAD_DISABLED) || \ + ((BURSTMODEPRELOAD) == HRIM_BURSTMODEPRELOAD_ENABLED)) #define IS_HRTIM_BURSTMODETRIGGER(BURSTMODETRIGGER)\ - (((BURSTMODETRIGGER) == HRTIM_BURSTMODETRIGGER_NONE) || \ - ((BURSTMODETRIGGER) == HRTIM_BURSTMODETRIGGER_MASTER_RESET) || \ - ((BURSTMODETRIGGER) == HRTIM_BURSTMODETRIGGER_MASTER_REPETITION) || \ - ((BURSTMODETRIGGER) == HRTIM_BURSTMODETRIGGER_MASTER_CMP1) || \ - ((BURSTMODETRIGGER) == HRTIM_BURSTMODETRIGGER_MASTER_CMP2) || \ - ((BURSTMODETRIGGER) == HRTIM_BURSTMODETRIGGER_MASTER_CMP3) || \ - ((BURSTMODETRIGGER) == HRTIM_BURSTMODETRIGGER_MASTER_CMP4) || \ - ((BURSTMODETRIGGER) == HRTIM_BURSTMODETRIGGER_TIMERA_RESET) || \ - ((BURSTMODETRIGGER) == HRTIM_BURSTMODETRIGGER_TIMERA_REPETITION) || \ - ((BURSTMODETRIGGER) == HRTIM_BURSTMODETRIGGER_TIMERA_CMP1) || \ - ((BURSTMODETRIGGER) == HRTIM_BURSTMODETRIGGER_TIMERA_CMP2) || \ - ((BURSTMODETRIGGER) == HRTIM_BURSTMODETRIGGER_TIMERB_RESET) || \ - ((BURSTMODETRIGGER) == HRTIM_BURSTMODETRIGGER_TIMERB_REPETITION) || \ - ((BURSTMODETRIGGER) == HRTIM_BURSTMODETRIGGER_TIMERB_CMP1) || \ - ((BURSTMODETRIGGER) == HRTIM_BURSTMODETRIGGER_TIMERB_CMP2) || \ - ((BURSTMODETRIGGER) == HRTIM_BURSTMODETRIGGER_TIMERC_RESET) || \ - ((BURSTMODETRIGGER) == HRTIM_BURSTMODETRIGGER_TIMERC_REPETITION) || \ - ((BURSTMODETRIGGER) == HRTIM_BURSTMODETRIGGER_TIMERC_CMP1) || \ - ((BURSTMODETRIGGER) == HRTIM_BURSTMODETRIGGER_TIMERC_CMP2) || \ - ((BURSTMODETRIGGER) == HRTIM_BURSTMODETRIGGER_TIMERD_RESET) || \ - ((BURSTMODETRIGGER) == HRTIM_BURSTMODETRIGGER_TIMERD_REPETITION) || \ - ((BURSTMODETRIGGER) == HRTIM_BURSTMODETRIGGER_TIMERD_CMP1) || \ - ((BURSTMODETRIGGER) == HRTIM_BURSTMODETRIGGER_TIMERD_CMP2) || \ - ((BURSTMODETRIGGER) == HRTIM_BURSTMODETRIGGER_TIMERE_RESET) || \ - ((BURSTMODETRIGGER) == HRTIM_BURSTMODETRIGGER_TIMERE_REPETITION) || \ - ((BURSTMODETRIGGER) == HRTIM_BURSTMODETRIGGER_TIMERE_CMP1) || \ - ((BURSTMODETRIGGER) == HRTIM_BURSTMODETRIGGER_TIMERE_CMP2) || \ - ((BURSTMODETRIGGER) == HRTIM_BURSTMODETRIGGER_TIMERA_EVENT7) || \ - ((BURSTMODETRIGGER) == HRTIM_BURSTMODETRIGGER_TIMERD_EVENT8) || \ - ((BURSTMODETRIGGER) == HRTIM_BURSTMODETRIGGER_EVENT_7) || \ - ((BURSTMODETRIGGER) == HRTIM_BURSTMODETRIGGER_EVENT_8) || \ - ((BURSTMODETRIGGER) == HRTIM_BURSTMODETRIGGER_EVENT_ONCHIP)) + (((BURSTMODETRIGGER) == HRTIM_BURSTMODETRIGGER_NONE) || \ + ((BURSTMODETRIGGER) == HRTIM_BURSTMODETRIGGER_MASTER_RESET) || \ + ((BURSTMODETRIGGER) == HRTIM_BURSTMODETRIGGER_MASTER_REPETITION) || \ + ((BURSTMODETRIGGER) == HRTIM_BURSTMODETRIGGER_MASTER_CMP1) || \ + ((BURSTMODETRIGGER) == HRTIM_BURSTMODETRIGGER_MASTER_CMP2) || \ + ((BURSTMODETRIGGER) == HRTIM_BURSTMODETRIGGER_MASTER_CMP3) || \ + ((BURSTMODETRIGGER) == HRTIM_BURSTMODETRIGGER_MASTER_CMP4) || \ + ((BURSTMODETRIGGER) == HRTIM_BURSTMODETRIGGER_TIMERA_RESET) || \ + ((BURSTMODETRIGGER) == HRTIM_BURSTMODETRIGGER_TIMERA_REPETITION) || \ + ((BURSTMODETRIGGER) == HRTIM_BURSTMODETRIGGER_TIMERA_CMP1) || \ + ((BURSTMODETRIGGER) == HRTIM_BURSTMODETRIGGER_TIMERA_CMP2) || \ + ((BURSTMODETRIGGER) == HRTIM_BURSTMODETRIGGER_TIMERB_RESET) || \ + ((BURSTMODETRIGGER) == HRTIM_BURSTMODETRIGGER_TIMERB_REPETITION) || \ + ((BURSTMODETRIGGER) == HRTIM_BURSTMODETRIGGER_TIMERB_CMP1) || \ + ((BURSTMODETRIGGER) == HRTIM_BURSTMODETRIGGER_TIMERB_CMP2) || \ + ((BURSTMODETRIGGER) == HRTIM_BURSTMODETRIGGER_TIMERC_RESET) || \ + ((BURSTMODETRIGGER) == HRTIM_BURSTMODETRIGGER_TIMERC_REPETITION) || \ + ((BURSTMODETRIGGER) == HRTIM_BURSTMODETRIGGER_TIMERC_CMP1) || \ + ((BURSTMODETRIGGER) == HRTIM_BURSTMODETRIGGER_TIMERC_CMP2) || \ + ((BURSTMODETRIGGER) == HRTIM_BURSTMODETRIGGER_TIMERD_RESET) || \ + ((BURSTMODETRIGGER) == HRTIM_BURSTMODETRIGGER_TIMERD_REPETITION) || \ + ((BURSTMODETRIGGER) == HRTIM_BURSTMODETRIGGER_TIMERD_CMP1) || \ + ((BURSTMODETRIGGER) == HRTIM_BURSTMODETRIGGER_TIMERD_CMP2) || \ + ((BURSTMODETRIGGER) == HRTIM_BURSTMODETRIGGER_TIMERE_RESET) || \ + ((BURSTMODETRIGGER) == HRTIM_BURSTMODETRIGGER_TIMERE_REPETITION) || \ + ((BURSTMODETRIGGER) == HRTIM_BURSTMODETRIGGER_TIMERE_CMP1) || \ + ((BURSTMODETRIGGER) == HRTIM_BURSTMODETRIGGER_TIMERE_CMP2) || \ + ((BURSTMODETRIGGER) == HRTIM_BURSTMODETRIGGER_TIMERA_EVENT7) || \ + ((BURSTMODETRIGGER) == HRTIM_BURSTMODETRIGGER_TIMERD_EVENT8) || \ + ((BURSTMODETRIGGER) == HRTIM_BURSTMODETRIGGER_EVENT_7) || \ + ((BURSTMODETRIGGER) == HRTIM_BURSTMODETRIGGER_EVENT_8) || \ + ((BURSTMODETRIGGER) == HRTIM_BURSTMODETRIGGER_EVENT_ONCHIP)) #define IS_HRTIM_ADCTRIGGERUPDATE(ADCTRIGGERUPDATE)\ - (((ADCTRIGGERUPDATE) == HRTIM_ADCTRIGGERUPDATE_MASTER) || \ - ((ADCTRIGGERUPDATE) == HRTIM_ADCTRIGGERUPDATE_TIMER_A) || \ - ((ADCTRIGGERUPDATE) == HRTIM_ADCTRIGGERUPDATE_TIMER_B) || \ - ((ADCTRIGGERUPDATE) == HRTIM_ADCTRIGGERUPDATE_TIMER_C) || \ - ((ADCTRIGGERUPDATE) == HRTIM_ADCTRIGGERUPDATE_TIMER_D) || \ - ((ADCTRIGGERUPDATE) == HRTIM_ADCTRIGGERUPDATE_TIMER_E)) + (((ADCTRIGGERUPDATE) == HRTIM_ADCTRIGGERUPDATE_MASTER) || \ + ((ADCTRIGGERUPDATE) == HRTIM_ADCTRIGGERUPDATE_TIMER_A) || \ + ((ADCTRIGGERUPDATE) == HRTIM_ADCTRIGGERUPDATE_TIMER_B) || \ + ((ADCTRIGGERUPDATE) == HRTIM_ADCTRIGGERUPDATE_TIMER_C) || \ + ((ADCTRIGGERUPDATE) == HRTIM_ADCTRIGGERUPDATE_TIMER_D) || \ + ((ADCTRIGGERUPDATE) == HRTIM_ADCTRIGGERUPDATE_TIMER_E)) #define IS_HRTIM_CALIBRATIONRATE(CALIBRATIONRATE)\ - (((CALIBRATIONRATE) == HRTIM_SINGLE_CALIBRATION) || \ - ((CALIBRATIONRATE) == HRTIM_CALIBRATIONRATE_7300) || \ - ((CALIBRATIONRATE) == HRTIM_CALIBRATIONRATE_910) || \ - ((CALIBRATIONRATE) == HRTIM_CALIBRATIONRATE_114) || \ - ((CALIBRATIONRATE) == HRTIM_CALIBRATIONRATE_14)) + (((CALIBRATIONRATE) == HRTIM_SINGLE_CALIBRATION) || \ + ((CALIBRATIONRATE) == HRTIM_CALIBRATIONRATE_7300) || \ + ((CALIBRATIONRATE) == HRTIM_CALIBRATIONRATE_910) || \ + ((CALIBRATIONRATE) == HRTIM_CALIBRATIONRATE_114) || \ + ((CALIBRATIONRATE) == HRTIM_CALIBRATIONRATE_14)) #define IS_HRTIM_TIMER_BURSTDMA(TIMER, BURSTDMA) \ - ((((TIMER) == HRTIM_TIMERINDEX_MASTER) && (((BURSTDMA) & 0xFFFFC000U) == 0x00000000U)) \ - || (((TIMER) == HRTIM_TIMERINDEX_TIMER_A) && (((BURSTDMA) & 0xFFE00000U) == 0x00000000U)) \ - || (((TIMER) == HRTIM_TIMERINDEX_TIMER_B) && (((BURSTDMA) & 0xFFE00000U) == 0x00000000U)) \ - || (((TIMER) == HRTIM_TIMERINDEX_TIMER_C) && (((BURSTDMA) & 0xFFE00000U) == 0x00000000U)) \ - || (((TIMER) == HRTIM_TIMERINDEX_TIMER_D) && (((BURSTDMA) & 0xFFE00000U) == 0x00000000U)) \ - || (((TIMER) == HRTIM_TIMERINDEX_TIMER_E) && (((BURSTDMA) & 0xFFE00000U) == 0x00000000U))) + ((((TIMER) == HRTIM_TIMERINDEX_MASTER) && (((BURSTDMA) & 0xFFFFC000U) == 0x00000000U)) \ + || (((TIMER) == HRTIM_TIMERINDEX_TIMER_A) && (((BURSTDMA) & 0xFFE00000U) == 0x00000000U)) \ + || (((TIMER) == HRTIM_TIMERINDEX_TIMER_B) && (((BURSTDMA) & 0xFFE00000U) == 0x00000000U)) \ + || (((TIMER) == HRTIM_TIMERINDEX_TIMER_C) && (((BURSTDMA) & 0xFFE00000U) == 0x00000000U)) \ + || (((TIMER) == HRTIM_TIMERINDEX_TIMER_D) && (((BURSTDMA) & 0xFFE00000U) == 0x00000000U)) \ + || (((TIMER) == HRTIM_TIMERINDEX_TIMER_E) && (((BURSTDMA) & 0xFFE00000U) == 0x00000000U))) #define IS_HRTIM_BURSTMODECTL(BURSTMODECTL)\ - (((BURSTMODECTL) == HRTIM_BURSTMODECTL_DISABLED) || \ - ((BURSTMODECTL) == HRTIM_BURSTMODECTL_ENABLED)) + (((BURSTMODECTL) == HRTIM_BURSTMODECTL_DISABLED) || \ + ((BURSTMODECTL) == HRTIM_BURSTMODECTL_ENABLED)) #define IS_HRTIM_TIMERUPDATE(TIMERUPDATE) (((TIMERUPDATE) & 0xFFFFFFC0U) == 0x00000000U) @@ -2783,10 +2792,10 @@ typedef void (* pHRTIM_TIMxCallbackTypeDef)(HRTIM_HandleTypeDef *hhrtim, /*!< */ #if (USE_HAL_HRTIM_REGISTER_CALLBACKS == 1) #define __HAL_HRTIM_RESET_HANDLE_STATE(__HANDLE__) do{ \ - (__HANDLE__)->State = HAL_HRTIM_STATE_RESET; \ - (__HANDLE__)->MspInitCallback = NULL; \ - (__HANDLE__)->MspDeInitCallback = NULL; \ - } while(0) + (__HANDLE__)->State = HAL_HRTIM_STATE_RESET; \ + (__HANDLE__)->MspInitCallback = NULL; \ + (__HANDLE__)->MspDeInitCallback = NULL; \ + } while(0) #else #define __HAL_HRTIM_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_HRTIM_STATE_RESET) #endif @@ -2815,44 +2824,44 @@ typedef void (* pHRTIM_TIMxCallbackTypeDef)(HRTIM_HandleTypeDef *hhrtim, /*!< #define __HAL_HRTIM_DISABLE(__HANDLE__, __TIMERS__)\ do {\ if (((__TIMERS__) & HRTIM_TIMERID_MASTER) == HRTIM_TIMERID_MASTER)\ - {\ - ((__HANDLE__)->Instance->sMasterRegs.MCR &= ~HRTIM_TIMERID_MASTER);\ - }\ + {\ + ((__HANDLE__)->Instance->sMasterRegs.MCR &= ~HRTIM_TIMERID_MASTER);\ + }\ if (((__TIMERS__) & HRTIM_TIMERID_TIMER_A) == HRTIM_TIMERID_TIMER_A)\ + {\ + if (((__HANDLE__)->Instance->sCommonRegs.OENR & HRTIM_TAOEN_MASK) == (uint32_t)RESET)\ {\ - if (((__HANDLE__)->Instance->sCommonRegs.OENR & HRTIM_TAOEN_MASK) == (uint32_t)RESET)\ - {\ - ((__HANDLE__)->Instance->sMasterRegs.MCR &= ~HRTIM_TIMERID_TIMER_A);\ - }\ + ((__HANDLE__)->Instance->sMasterRegs.MCR &= ~HRTIM_TIMERID_TIMER_A);\ }\ + }\ if (((__TIMERS__) & HRTIM_TIMERID_TIMER_B) == HRTIM_TIMERID_TIMER_B)\ + {\ + if (((__HANDLE__)->Instance->sCommonRegs.OENR & HRTIM_TBOEN_MASK) == (uint32_t)RESET)\ {\ - if (((__HANDLE__)->Instance->sCommonRegs.OENR & HRTIM_TBOEN_MASK) == (uint32_t)RESET)\ - {\ - ((__HANDLE__)->Instance->sMasterRegs.MCR &= ~HRTIM_TIMERID_TIMER_B);\ - }\ + ((__HANDLE__)->Instance->sMasterRegs.MCR &= ~HRTIM_TIMERID_TIMER_B);\ }\ + }\ if (((__TIMERS__) & HRTIM_TIMERID_TIMER_C) == HRTIM_TIMERID_TIMER_C)\ + {\ + if (((__HANDLE__)->Instance->sCommonRegs.OENR & HRTIM_TCOEN_MASK) == (uint32_t)RESET)\ {\ - if (((__HANDLE__)->Instance->sCommonRegs.OENR & HRTIM_TCOEN_MASK) == (uint32_t)RESET)\ - {\ - ((__HANDLE__)->Instance->sMasterRegs.MCR &= ~HRTIM_TIMERID_TIMER_C);\ - }\ + ((__HANDLE__)->Instance->sMasterRegs.MCR &= ~HRTIM_TIMERID_TIMER_C);\ }\ + }\ if (((__TIMERS__) & HRTIM_TIMERID_TIMER_D) == HRTIM_TIMERID_TIMER_D)\ + {\ + if (((__HANDLE__)->Instance->sCommonRegs.OENR & HRTIM_TDOEN_MASK) == (uint32_t)RESET)\ {\ - if (((__HANDLE__)->Instance->sCommonRegs.OENR & HRTIM_TDOEN_MASK) == (uint32_t)RESET)\ - {\ - ((__HANDLE__)->Instance->sMasterRegs.MCR &= ~HRTIM_TIMERID_TIMER_D);\ - }\ + ((__HANDLE__)->Instance->sMasterRegs.MCR &= ~HRTIM_TIMERID_TIMER_D);\ }\ + }\ if (((__TIMERS__) & HRTIM_TIMERID_TIMER_E) == HRTIM_TIMERID_TIMER_E)\ + {\ + if (((__HANDLE__)->Instance->sCommonRegs.OENR & HRTIM_TEOEN_MASK) == (uint32_t)RESET)\ {\ - if (((__HANDLE__)->Instance->sCommonRegs.OENR & HRTIM_TEOEN_MASK) == (uint32_t)RESET)\ - {\ - ((__HANDLE__)->Instance->sMasterRegs.MCR &= ~HRTIM_TIMERID_TIMER_E);\ - }\ + ((__HANDLE__)->Instance->sMasterRegs.MCR &= ~HRTIM_TIMERID_TIMER_E);\ }\ + }\ } while(0U) @@ -2886,8 +2895,10 @@ typedef void (* pHRTIM_TIMxCallbackTypeDef)(HRTIM_HandleTypeDef *hhrtim, /*!< * @arg HRTIM_MASTER_IT_MUPD: Master update interrupt enable * @retval None */ -#define __HAL_HRTIM_MASTER_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->sMasterRegs.MDIER |= (__INTERRUPT__)) -#define __HAL_HRTIM_MASTER_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->sMasterRegs.MDIER &= ~(__INTERRUPT__)) +#define __HAL_HRTIM_MASTER_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->sMasterRegs.MDIER \ + |= (__INTERRUPT__)) +#define __HAL_HRTIM_MASTER_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->sMasterRegs.MDIER \ + &= ~(__INTERRUPT__)) /** @brief Enables or disables the specified HRTIM Timerx interrupts. * @param __HANDLE__ specifies the HRTIM Handle. @@ -2927,7 +2938,8 @@ typedef void (* pHRTIM_TIMxCallbackTypeDef)(HRTIM_HandleTypeDef *hhrtim, /*!< * @arg HRTIM_IT_BMPER: Burst mode period interrupt enable * @retval The new state of __INTERRUPT__ (TRUE or FALSE). */ -#define __HAL_HRTIM_GET_ITSTATUS(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->sCommonRegs.IER & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET) +#define __HAL_HRTIM_GET_ITSTATUS(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->sCommonRegs.IER &\ + (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET) /** @brief Checks if the specified HRTIM Master interrupt source is enabled or disabled. * @param __HANDLE__ specifies the HRTIM Handle. @@ -2942,7 +2954,8 @@ typedef void (* pHRTIM_TIMxCallbackTypeDef)(HRTIM_HandleTypeDef *hhrtim, /*!< * @arg HRTIM_MASTER_IT_MUPD: Master update interrupt enable * @retval The new state of __INTERRUPT__ (TRUE or FALSE). */ -#define __HAL_HRTIM_MASTER_GET_ITSTATUS(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->sMasterRegs.MDIER & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET) +#define __HAL_HRTIM_MASTER_GET_ITSTATUS(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->sMasterRegs.MDIER &\ + (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET) /** @brief Checks if the specified HRTIM Timerx interrupt source is enabled or disabled. * @param __HANDLE__ specifies the HRTIM Handle. @@ -2972,7 +2985,8 @@ typedef void (* pHRTIM_TIMxCallbackTypeDef)(HRTIM_HandleTypeDef *hhrtim, /*!< * @arg HRTIM_TIM_IT_DLYPRT: Timer delay protection interrupt enable * @retval The new state of __INTERRUPT__ (TRUE or FALSE). */ -#define __HAL_HRTIM_TIMER_GET_ITSTATUS(__HANDLE__, __TIMER__, __INTERRUPT__) ((((__HANDLE__)->Instance->sTimerxRegs[(__TIMER__)].TIMxDIER & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET) +#define __HAL_HRTIM_TIMER_GET_ITSTATUS(__HANDLE__, __TIMER__, __INTERRUPT__) ((((__HANDLE__)->Instance->sTimerxRegs[(__TIMER__)].TIMxDIER &\ + (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET) /** @brief Clears the specified HRTIM common pending flag. * @param __HANDLE__ specifies the HRTIM Handle. @@ -3003,7 +3017,8 @@ typedef void (* pHRTIM_TIMxCallbackTypeDef)(HRTIM_HandleTypeDef *hhrtim, /*!< * @arg HRTIM_MASTER_IT_MUPD: Master update interrupt clear flag * @retval None */ -#define __HAL_HRTIM_MASTER_CLEAR_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->sMasterRegs.MICR = (__INTERRUPT__)) +#define __HAL_HRTIM_MASTER_CLEAR_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->sMasterRegs.MICR\ + = (__INTERRUPT__)) /** @brief Clears the specified HRTIM Timerx pending flag. * @param __HANDLE__ specifies the HRTIM Handle. @@ -3026,7 +3041,8 @@ typedef void (* pHRTIM_TIMxCallbackTypeDef)(HRTIM_HandleTypeDef *hhrtim, /*!< * @arg HRTIM_TIM_IT_DLYPRT: Timer output 1 delay protection interrupt clear flag * @retval None */ -#define __HAL_HRTIM_TIMER_CLEAR_IT(__HANDLE__, __TIMER__, __INTERRUPT__) ((__HANDLE__)->Instance->sTimerxRegs[(__TIMER__)].TIMxICR = (__INTERRUPT__)) +#define __HAL_HRTIM_TIMER_CLEAR_IT(__HANDLE__, __TIMER__, __INTERRUPT__) ((__HANDLE__)->Instance->sTimerxRegs[(__TIMER__)].TIMxICR\ + = (__INTERRUPT__)) /* DMA HANDLING */ /** @brief Enables or disables the specified HRTIM Master timer DMA requests. @@ -3069,14 +3085,18 @@ typedef void (* pHRTIM_TIMxCallbackTypeDef)(HRTIM_HandleTypeDef *hhrtim, /*!< #define __HAL_HRTIM_TIMER_ENABLE_DMA(__HANDLE__, __TIMER__, __DMA__) ((__HANDLE__)->Instance->sTimerxRegs[(__TIMER__)].TIMxDIER |= (__DMA__)) #define __HAL_HRTIM_TIMER_DISABLE_DMA(__HANDLE__, __TIMER__, __DMA__) ((__HANDLE__)->Instance->sTimerxRegs[(__TIMER__)].TIMxDIER &= ~(__DMA__)) -#define __HAL_HRTIM_GET_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->sCommonRegs.ISR & (__FLAG__)) == (__FLAG__)) +#define __HAL_HRTIM_GET_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->sCommonRegs.ISR &\ + (__FLAG__)) == (__FLAG__)) #define __HAL_HRTIM_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->sCommonRegs.ICR = (__FLAG__)) -#define __HAL_HRTIM_MASTER_GET_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->sMasterRegs.MISR & (__FLAG__)) == (__FLAG__)) +#define __HAL_HRTIM_MASTER_GET_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->sMasterRegs.MISR &\ + (__FLAG__)) == (__FLAG__)) #define __HAL_HRTIM_MASTER_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->sMasterRegs.MICR = (__FLAG__)) -#define __HAL_HRTIM_TIMER_GET_FLAG(__HANDLE__, __TIMER__, __FLAG__) (((__HANDLE__)->Instance->sTimerxRegs[(__TIMER__)].TIMxISR & (__FLAG__)) == (__FLAG__)) -#define __HAL_HRTIM_TIMER_CLEAR_FLAG(__HANDLE__, __TIMER__, __FLAG__) ((__HANDLE__)->Instance->sTimerxRegs[(__TIMER__)].TIMxICR = (__FLAG__)) +#define __HAL_HRTIM_TIMER_GET_FLAG(__HANDLE__, __TIMER__, __FLAG__) (((__HANDLE__)->Instance->sTimerxRegs[(__TIMER__)].TIMxISR &\ + (__FLAG__)) == (__FLAG__)) +#define __HAL_HRTIM_TIMER_CLEAR_FLAG(__HANDLE__, __TIMER__, __FLAG__) ((__HANDLE__)->Instance->sTimerxRegs[(__TIMER__)].TIMxICR\ + = (__FLAG__)) /** @brief Sets the HRTIM timer Counter Register value on runtime * @param __HANDLE__ HRTIM Handle. @@ -3177,16 +3197,16 @@ typedef void (* pHRTIM_TIMxCallbackTypeDef)(HRTIM_HandleTypeDef *hhrtim, /*!< * @retval None */ #define __HAL_HRTIM_SETCOMPARE(__HANDLE__, __TIMER__, __COMPAREUNIT__, __COMPARE__) \ - (((__TIMER__) == HRTIM_TIMERINDEX_MASTER) ? \ - (((__COMPAREUNIT__) == HRTIM_COMPAREUNIT_1) ? ((__HANDLE__)->Instance->sMasterRegs.MCMP1R = (__COMPARE__)) :\ - ((__COMPAREUNIT__) == HRTIM_COMPAREUNIT_2) ? ((__HANDLE__)->Instance->sMasterRegs.MCMP2R = (__COMPARE__)) :\ - ((__COMPAREUNIT__) == HRTIM_COMPAREUNIT_3) ? ((__HANDLE__)->Instance->sMasterRegs.MCMP3R = (__COMPARE__)) :\ - ((__HANDLE__)->Instance->sMasterRegs.MCMP4R = (__COMPARE__))) \ - : \ - (((__COMPAREUNIT__) == HRTIM_COMPAREUNIT_1) ? ((__HANDLE__)->Instance->sTimerxRegs[(__TIMER__)].CMP1xR = (__COMPARE__)) :\ - ((__COMPAREUNIT__) == HRTIM_COMPAREUNIT_2) ? ((__HANDLE__)->Instance->sTimerxRegs[(__TIMER__)].CMP2xR = (__COMPARE__)) :\ - ((__COMPAREUNIT__) == HRTIM_COMPAREUNIT_3) ? ((__HANDLE__)->Instance->sTimerxRegs[(__TIMER__)].CMP3xR = (__COMPARE__)) :\ - ((__HANDLE__)->Instance->sTimerxRegs[(__TIMER__)].CMP4xR = (__COMPARE__)))) + (((__TIMER__) == HRTIM_TIMERINDEX_MASTER) ? \ + (((__COMPAREUNIT__) == HRTIM_COMPAREUNIT_1) ? ((__HANDLE__)->Instance->sMasterRegs.MCMP1R = (__COMPARE__)) :\ + ((__COMPAREUNIT__) == HRTIM_COMPAREUNIT_2) ? ((__HANDLE__)->Instance->sMasterRegs.MCMP2R = (__COMPARE__)) :\ + ((__COMPAREUNIT__) == HRTIM_COMPAREUNIT_3) ? ((__HANDLE__)->Instance->sMasterRegs.MCMP3R = (__COMPARE__)) :\ + ((__HANDLE__)->Instance->sMasterRegs.MCMP4R = (__COMPARE__))) \ + : \ + (((__COMPAREUNIT__) == HRTIM_COMPAREUNIT_1) ? ((__HANDLE__)->Instance->sTimerxRegs[(__TIMER__)].CMP1xR = (__COMPARE__)) :\ + ((__COMPAREUNIT__) == HRTIM_COMPAREUNIT_2) ? ((__HANDLE__)->Instance->sTimerxRegs[(__TIMER__)].CMP2xR = (__COMPARE__)) :\ + ((__COMPAREUNIT__) == HRTIM_COMPAREUNIT_3) ? ((__HANDLE__)->Instance->sTimerxRegs[(__TIMER__)].CMP3xR = (__COMPARE__)) :\ + ((__HANDLE__)->Instance->sTimerxRegs[(__TIMER__)].CMP4xR = (__COMPARE__)))) /** @brief Gets the HRTIM timer Compare Register value on runtime * @param __HANDLE__ HRTIM Handle. @@ -3202,16 +3222,16 @@ typedef void (* pHRTIM_TIMxCallbackTypeDef)(HRTIM_HandleTypeDef *hhrtim, /*!< * @retval Compare value */ #define __HAL_HRTIM_GETCOMPARE(__HANDLE__, __TIMER__, __COMPAREUNIT__) \ - (((__TIMER__) == HRTIM_TIMERINDEX_MASTER) ? \ - (((__COMPAREUNIT__) == HRTIM_COMPAREUNIT_1) ? ((__HANDLE__)->Instance->sMasterRegs.MCMP1R) :\ - ((__COMPAREUNIT__) == HRTIM_COMPAREUNIT_2) ? ((__HANDLE__)->Instance->sMasterRegs.MCMP2R) :\ - ((__COMPAREUNIT__) == HRTIM_COMPAREUNIT_3) ? ((__HANDLE__)->Instance->sMasterRegs.MCMP3R) :\ - ((__HANDLE__)->Instance->sMasterRegs.MCMP4R)) \ - : \ - (((__COMPAREUNIT__) == HRTIM_COMPAREUNIT_1) ? ((__HANDLE__)->Instance->sTimerxRegs[(__TIMER__)].CMP1xR) :\ - ((__COMPAREUNIT__) == HRTIM_COMPAREUNIT_2) ? ((__HANDLE__)->Instance->sTimerxRegs[(__TIMER__)].CMP2xR) :\ - ((__COMPAREUNIT__) == HRTIM_COMPAREUNIT_3) ? ((__HANDLE__)->Instance->sTimerxRegs[(__TIMER__)].CMP3xR) :\ - ((__HANDLE__)->Instance->sTimerxRegs[(__TIMER__)].CMP4xR))) + (((__TIMER__) == HRTIM_TIMERINDEX_MASTER) ? \ + (((__COMPAREUNIT__) == HRTIM_COMPAREUNIT_1) ? ((__HANDLE__)->Instance->sMasterRegs.MCMP1R) :\ + ((__COMPAREUNIT__) == HRTIM_COMPAREUNIT_2) ? ((__HANDLE__)->Instance->sMasterRegs.MCMP2R) :\ + ((__COMPAREUNIT__) == HRTIM_COMPAREUNIT_3) ? ((__HANDLE__)->Instance->sMasterRegs.MCMP3R) :\ + ((__HANDLE__)->Instance->sMasterRegs.MCMP4R)) \ + : \ + (((__COMPAREUNIT__) == HRTIM_COMPAREUNIT_1) ? ((__HANDLE__)->Instance->sTimerxRegs[(__TIMER__)].CMP1xR) :\ + ((__COMPAREUNIT__) == HRTIM_COMPAREUNIT_2) ? ((__HANDLE__)->Instance->sTimerxRegs[(__TIMER__)].CMP2xR) :\ + ((__COMPAREUNIT__) == HRTIM_COMPAREUNIT_3) ? ((__HANDLE__)->Instance->sTimerxRegs[(__TIMER__)].CMP3xR) :\ + ((__HANDLE__)->Instance->sTimerxRegs[(__TIMER__)].CMP4xR))) /** * @} @@ -3219,17 +3239,17 @@ typedef void (* pHRTIM_TIMxCallbackTypeDef)(HRTIM_HandleTypeDef *hhrtim, /*!< /* Exported functions --------------------------------------------------------*/ /** @addtogroup HRTIM_Exported_Functions -* @{ -*/ + * @{ + */ /** @addtogroup HRTIM_Exported_Functions_Group1 -* @{ -*/ + * @{ + */ /* Initialization and Configuration functions ********************************/ HAL_StatusTypeDef HAL_HRTIM_Init(HRTIM_HandleTypeDef *hhrtim); -HAL_StatusTypeDef HAL_HRTIM_DeInit (HRTIM_HandleTypeDef *hhrtim); +HAL_StatusTypeDef HAL_HRTIM_DeInit(HRTIM_HandleTypeDef *hhrtim); void HAL_HRTIM_MspInit(HRTIM_HandleTypeDef *hhrtim); @@ -3237,7 +3257,7 @@ void HAL_HRTIM_MspDeInit(HRTIM_HandleTypeDef *hhrtim); HAL_StatusTypeDef HAL_HRTIM_TimeBaseConfig(HRTIM_HandleTypeDef *hhrtim, uint32_t TimerIdx, - const HRTIM_TimeBaseCfgTypeDef * pTimeBaseCfg); + const HRTIM_TimeBaseCfgTypeDef *pTimeBaseCfg); HAL_StatusTypeDef HAL_HRTIM_DLLCalibrationStart(HRTIM_HandleTypeDef *hhrtim, uint32_t CalibrationRate); @@ -3253,238 +3273,238 @@ HAL_StatusTypeDef HAL_HRTIM_PollForDLLCalibration(HRTIM_HandleTypeDef *hhrtim, */ /** @addtogroup HRTIM_Exported_Functions_Group2 -* @{ -*/ + * @{ + */ /* Simple time base related functions *****************************************/ HAL_StatusTypeDef HAL_HRTIM_SimpleBaseStart(HRTIM_HandleTypeDef *hhrtim, - uint32_t TimerIdx); + uint32_t TimerIdx); HAL_StatusTypeDef HAL_HRTIM_SimpleBaseStop(HRTIM_HandleTypeDef *hhrtim, - uint32_t TimerIdx); + uint32_t TimerIdx); HAL_StatusTypeDef HAL_HRTIM_SimpleBaseStart_IT(HRTIM_HandleTypeDef *hhrtim, - uint32_t TimerIdx); + uint32_t TimerIdx); HAL_StatusTypeDef HAL_HRTIM_SimpleBaseStop_IT(HRTIM_HandleTypeDef *hhrtim, - uint32_t TimerIdx); + uint32_t TimerIdx); HAL_StatusTypeDef HAL_HRTIM_SimpleBaseStart_DMA(HRTIM_HandleTypeDef *hhrtim, - uint32_t TimerIdx, - uint32_t SrcAddr, - uint32_t DestAddr, - uint32_t Length); + uint32_t TimerIdx, + uint32_t SrcAddr, + uint32_t DestAddr, + uint32_t Length); HAL_StatusTypeDef HAL_HRTIM_SimpleBaseStop_DMA(HRTIM_HandleTypeDef *hhrtim, - uint32_t TimerIdx); + uint32_t TimerIdx); /** * @} */ /** @addtogroup HRTIM_Exported_Functions_Group3 -* @{ -*/ + * @{ + */ /* Simple output compare related functions ************************************/ HAL_StatusTypeDef HAL_HRTIM_SimpleOCChannelConfig(HRTIM_HandleTypeDef *hhrtim, - uint32_t TimerIdx, - uint32_t OCChannel, - const HRTIM_SimpleOCChannelCfgTypeDef* pSimpleOCChannelCfg); + uint32_t TimerIdx, + uint32_t OCChannel, + const HRTIM_SimpleOCChannelCfgTypeDef *pSimpleOCChannelCfg); HAL_StatusTypeDef HAL_HRTIM_SimpleOCStart(HRTIM_HandleTypeDef *hhrtim, - uint32_t TimerIdx, - uint32_t OCChannel); + uint32_t TimerIdx, + uint32_t OCChannel); HAL_StatusTypeDef HAL_HRTIM_SimpleOCStop(HRTIM_HandleTypeDef *hhrtim, - uint32_t TimerIdx, - uint32_t OCChannel); + uint32_t TimerIdx, + uint32_t OCChannel); HAL_StatusTypeDef HAL_HRTIM_SimpleOCStart_IT(HRTIM_HandleTypeDef *hhrtim, - uint32_t TimerIdx, - uint32_t OCChannel); + uint32_t TimerIdx, + uint32_t OCChannel); HAL_StatusTypeDef HAL_HRTIM_SimpleOCStop_IT(HRTIM_HandleTypeDef *hhrtim, - uint32_t TimerIdx, - uint32_t OCChannel); + uint32_t TimerIdx, + uint32_t OCChannel); HAL_StatusTypeDef HAL_HRTIM_SimpleOCStart_DMA(HRTIM_HandleTypeDef *hhrtim, - uint32_t TimerIdx, - uint32_t OCChannel, - uint32_t SrcAddr, - uint32_t DestAddr, - uint32_t Length); + uint32_t TimerIdx, + uint32_t OCChannel, + uint32_t SrcAddr, + uint32_t DestAddr, + uint32_t Length); HAL_StatusTypeDef HAL_HRTIM_SimpleOCStop_DMA(HRTIM_HandleTypeDef *hhrtim, - uint32_t TimerIdx, - uint32_t OCChannel); + uint32_t TimerIdx, + uint32_t OCChannel); /** * @} */ /** @addtogroup HRTIM_Exported_Functions_Group4 -* @{ -*/ + * @{ + */ /* Simple PWM output related functions ****************************************/ HAL_StatusTypeDef HAL_HRTIM_SimplePWMChannelConfig(HRTIM_HandleTypeDef *hhrtim, - uint32_t TimerIdx, - uint32_t PWMChannel, - const HRTIM_SimplePWMChannelCfgTypeDef* pSimplePWMChannelCfg); + uint32_t TimerIdx, + uint32_t PWMChannel, + const HRTIM_SimplePWMChannelCfgTypeDef *pSimplePWMChannelCfg); HAL_StatusTypeDef HAL_HRTIM_SimplePWMStart(HRTIM_HandleTypeDef *hhrtim, - uint32_t TimerIdx, - uint32_t PWMChannel); + uint32_t TimerIdx, + uint32_t PWMChannel); HAL_StatusTypeDef HAL_HRTIM_SimplePWMStop(HRTIM_HandleTypeDef *hhrtim, - uint32_t TimerIdx, - uint32_t PWMChannel); + uint32_t TimerIdx, + uint32_t PWMChannel); HAL_StatusTypeDef HAL_HRTIM_SimplePWMStart_IT(HRTIM_HandleTypeDef *hhrtim, - uint32_t TimerIdx, - uint32_t PWMChannel); + uint32_t TimerIdx, + uint32_t PWMChannel); HAL_StatusTypeDef HAL_HRTIM_SimplePWMStop_IT(HRTIM_HandleTypeDef *hhrtim, - uint32_t TimerIdx, - uint32_t PWMChannel); + uint32_t TimerIdx, + uint32_t PWMChannel); HAL_StatusTypeDef HAL_HRTIM_SimplePWMStart_DMA(HRTIM_HandleTypeDef *hhrtim, - uint32_t TimerIdx, - uint32_t PWMChannel, - uint32_t SrcAddr, - uint32_t DestAddr, - uint32_t Length); + uint32_t TimerIdx, + uint32_t PWMChannel, + uint32_t SrcAddr, + uint32_t DestAddr, + uint32_t Length); HAL_StatusTypeDef HAL_HRTIM_SimplePWMStop_DMA(HRTIM_HandleTypeDef *hhrtim, - uint32_t TimerIdx, - uint32_t PWMChannel); + uint32_t TimerIdx, + uint32_t PWMChannel); /** * @} */ /** @addtogroup HRTIM_Exported_Functions_Group5 -* @{ -*/ + * @{ + */ /* Simple capture related functions *******************************************/ HAL_StatusTypeDef HAL_HRTIM_SimpleCaptureChannelConfig(HRTIM_HandleTypeDef *hhrtim, - uint32_t TimerIdx, - uint32_t CaptureChannel, - const HRTIM_SimpleCaptureChannelCfgTypeDef* pSimpleCaptureChannelCfg); + uint32_t TimerIdx, + uint32_t CaptureChannel, + const HRTIM_SimpleCaptureChannelCfgTypeDef *pSimpleCaptureChannelCfg); HAL_StatusTypeDef HAL_HRTIM_SimpleCaptureStart(HRTIM_HandleTypeDef *hhrtim, - uint32_t TimerIdx, - uint32_t CaptureChannel); + uint32_t TimerIdx, + uint32_t CaptureChannel); HAL_StatusTypeDef HAL_HRTIM_SimpleCaptureStop(HRTIM_HandleTypeDef *hhrtim, - uint32_t TimerIdx, - uint32_t CaptureChannel); + uint32_t TimerIdx, + uint32_t CaptureChannel); HAL_StatusTypeDef HAL_HRTIM_SimpleCaptureStart_IT(HRTIM_HandleTypeDef *hhrtim, - uint32_t TimerIdx, - uint32_t CaptureChannel); + uint32_t TimerIdx, + uint32_t CaptureChannel); HAL_StatusTypeDef HAL_HRTIM_SimpleCaptureStop_IT(HRTIM_HandleTypeDef *hhrtim, - uint32_t TimerIdx, - uint32_t CaptureChannel); + uint32_t TimerIdx, + uint32_t CaptureChannel); HAL_StatusTypeDef HAL_HRTIM_SimpleCaptureStart_DMA(HRTIM_HandleTypeDef *hhrtim, - uint32_t TimerIdx, - uint32_t CaptureChannel, - uint32_t SrcAddr, - uint32_t DestAddr, - uint32_t Length); + uint32_t TimerIdx, + uint32_t CaptureChannel, + uint32_t SrcAddr, + uint32_t DestAddr, + uint32_t Length); HAL_StatusTypeDef HAL_HRTIM_SimpleCaptureStop_DMA(HRTIM_HandleTypeDef *hhrtim, - uint32_t TimerIdx, - uint32_t CaptureChannel); + uint32_t TimerIdx, + uint32_t CaptureChannel); /** * @} */ /** @addtogroup HRTIM_Exported_Functions_Group6 -* @{ -*/ + * @{ + */ /* Simple one pulse related functions *****************************************/ HAL_StatusTypeDef HAL_HRTIM_SimpleOnePulseChannelConfig(HRTIM_HandleTypeDef *hhrtim, - uint32_t TimerIdx, - uint32_t OnePulseChannel, - const HRTIM_SimpleOnePulseChannelCfgTypeDef* pSimpleOnePulseChannelCfg); + uint32_t TimerIdx, + uint32_t OnePulseChannel, + const HRTIM_SimpleOnePulseChannelCfgTypeDef *pSimpleOnePulseChannelCfg); HAL_StatusTypeDef HAL_HRTIM_SimpleOnePulseStart(HRTIM_HandleTypeDef *hhrtim, - uint32_t TimerIdx, - uint32_t OnePulseChannel); + uint32_t TimerIdx, + uint32_t OnePulseChannel); HAL_StatusTypeDef HAL_HRTIM_SimpleOnePulseStop(HRTIM_HandleTypeDef *hhrtim, - uint32_t TimerIdx, - uint32_t OnePulseChannel); + uint32_t TimerIdx, + uint32_t OnePulseChannel); HAL_StatusTypeDef HAL_HRTIM_SimpleOnePulseStart_IT(HRTIM_HandleTypeDef *hhrtim, - uint32_t TimerIdx, - uint32_t OnePulseChannel); + uint32_t TimerIdx, + uint32_t OnePulseChannel); HAL_StatusTypeDef HAL_HRTIM_SimpleOnePulseStop_IT(HRTIM_HandleTypeDef *hhrtim, - uint32_t TimerIdx, - uint32_t OnePulseChannel); + uint32_t TimerIdx, + uint32_t OnePulseChannel); /** * @} */ /** @addtogroup HRTIM_Exported_Functions_Group7 -* @{ -*/ + * @{ + */ HAL_StatusTypeDef HAL_HRTIM_BurstModeConfig(HRTIM_HandleTypeDef *hhrtim, - const HRTIM_BurstModeCfgTypeDef* pBurstModeCfg); + const HRTIM_BurstModeCfgTypeDef *pBurstModeCfg); HAL_StatusTypeDef HAL_HRTIM_EventConfig(HRTIM_HandleTypeDef *hhrtim, uint32_t Event, - const HRTIM_EventCfgTypeDef* pEventCfg); + const HRTIM_EventCfgTypeDef *pEventCfg); HAL_StatusTypeDef HAL_HRTIM_EventPrescalerConfig(HRTIM_HandleTypeDef *hhrtim, uint32_t Prescaler); HAL_StatusTypeDef HAL_HRTIM_FaultConfig(HRTIM_HandleTypeDef *hhrtim, uint32_t Fault, - const HRTIM_FaultCfgTypeDef* pFaultCfg); + const HRTIM_FaultCfgTypeDef *pFaultCfg); HAL_StatusTypeDef HAL_HRTIM_FaultPrescalerConfig(HRTIM_HandleTypeDef *hhrtim, uint32_t Prescaler); -void HAL_HRTIM_FaultModeCtl(HRTIM_HandleTypeDef * hhrtim, +void HAL_HRTIM_FaultModeCtl(HRTIM_HandleTypeDef *hhrtim, uint32_t Faults, uint32_t Enable); HAL_StatusTypeDef HAL_HRTIM_ADCTriggerConfig(HRTIM_HandleTypeDef *hhrtim, uint32_t ADCTrigger, - const HRTIM_ADCTriggerCfgTypeDef* pADCTriggerCfg); + const HRTIM_ADCTriggerCfgTypeDef *pADCTriggerCfg); /** * @} */ /** @addtogroup HRTIM_Exported_Functions_Group8 -* @{ -*/ + * @{ + */ /* Waveform related functions *************************************************/ HAL_StatusTypeDef HAL_HRTIM_WaveformTimerConfig(HRTIM_HandleTypeDef *hhrtim, uint32_t TimerIdx, - const HRTIM_TimerCfgTypeDef * pTimerCfg); + const HRTIM_TimerCfgTypeDef *pTimerCfg); HAL_StatusTypeDef HAL_HRTIM_WaveformCompareConfig(HRTIM_HandleTypeDef *hhrtim, uint32_t TimerIdx, uint32_t CompareUnit, - const HRTIM_CompareCfgTypeDef* pCompareCfg); + const HRTIM_CompareCfgTypeDef *pCompareCfg); HAL_StatusTypeDef HAL_HRTIM_WaveformCaptureConfig(HRTIM_HandleTypeDef *hhrtim, uint32_t TimerIdx, uint32_t CaptureUnit, - const HRTIM_CaptureCfgTypeDef* pCaptureCfg); + const HRTIM_CaptureCfgTypeDef *pCaptureCfg); HAL_StatusTypeDef HAL_HRTIM_WaveformOutputConfig(HRTIM_HandleTypeDef *hhrtim, uint32_t TimerIdx, uint32_t Output, - const HRTIM_OutputCfgTypeDef * pOutputCfg); + const HRTIM_OutputCfgTypeDef *pOutputCfg); HAL_StatusTypeDef HAL_HRTIM_WaveformSetOutputLevel(HRTIM_HandleTypeDef *hhrtim, uint32_t TimerIdx, @@ -3494,15 +3514,15 @@ HAL_StatusTypeDef HAL_HRTIM_WaveformSetOutputLevel(HRTIM_HandleTypeDef *hhrtim, HAL_StatusTypeDef HAL_HRTIM_TimerEventFilteringConfig(HRTIM_HandleTypeDef *hhrtim, uint32_t TimerIdx, uint32_t Event, - const HRTIM_TimerEventFilteringCfgTypeDef * pTimerEventFilteringCfg); + const HRTIM_TimerEventFilteringCfgTypeDef *pTimerEventFilteringCfg); HAL_StatusTypeDef HAL_HRTIM_DeadTimeConfig(HRTIM_HandleTypeDef *hhrtim, uint32_t TimerIdx, - const HRTIM_DeadTimeCfgTypeDef* pDeadTimeCfg); + const HRTIM_DeadTimeCfgTypeDef *pDeadTimeCfg); HAL_StatusTypeDef HAL_HRTIM_ChopperModeConfig(HRTIM_HandleTypeDef *hhrtim, uint32_t TimerIdx, - const HRTIM_ChopperModeCfgTypeDef* pChopperModeCfg); + const HRTIM_ChopperModeCfgTypeDef *pChopperModeCfg); HAL_StatusTypeDef HAL_HRTIM_BurstDMAConfig(HRTIM_HandleTypeDef *hhrtim, uint32_t TimerIdx, @@ -3510,22 +3530,22 @@ HAL_StatusTypeDef HAL_HRTIM_BurstDMAConfig(HRTIM_HandleTypeDef *hhrtim, HAL_StatusTypeDef HAL_HRTIM_WaveformCountStart(HRTIM_HandleTypeDef *hhrtim, - uint32_t Timers); + uint32_t Timers); HAL_StatusTypeDef HAL_HRTIM_WaveformCountStop(HRTIM_HandleTypeDef *hhrtim, - uint32_t Timers); + uint32_t Timers); HAL_StatusTypeDef HAL_HRTIM_WaveformCountStart_IT(HRTIM_HandleTypeDef *hhrtim, - uint32_t Timers); + uint32_t Timers); HAL_StatusTypeDef HAL_HRTIM_WaveformCountStop_IT(HRTIM_HandleTypeDef *hhrtim, uint32_t Timers); HAL_StatusTypeDef HAL_HRTIM_WaveformCountStart_DMA(HRTIM_HandleTypeDef *hhrtim, - uint32_t Timers); + uint32_t Timers); HAL_StatusTypeDef HAL_HRTIM_WaveformCountStop_DMA(HRTIM_HandleTypeDef *hhrtim, - uint32_t Timers); + uint32_t Timers); HAL_StatusTypeDef HAL_HRTIM_WaveformOutputStart(HRTIM_HandleTypeDef *hhrtim, uint32_t OutputsToStart); @@ -3554,7 +3574,7 @@ HAL_StatusTypeDef HAL_HRTIM_BurstDMATransfer(HRTIM_HandleTypeDef *hhrtim, uint32_t BurstBufferLength); HAL_StatusTypeDef HAL_HRTIM_UpdateEnable(HRTIM_HandleTypeDef *hhrtim, - uint32_t Timers); + uint32_t Timers); HAL_StatusTypeDef HAL_HRTIM_UpdateDisable(HRTIM_HandleTypeDef *hhrtim, uint32_t Timers); @@ -3564,12 +3584,12 @@ HAL_StatusTypeDef HAL_HRTIM_UpdateDisable(HRTIM_HandleTypeDef *hhrtim, */ /** @addtogroup HRTIM_Exported_Functions_Group9 -* @{ -*/ + * @{ + */ /* HRTIM peripheral state functions */ -HAL_HRTIM_StateTypeDef HAL_HRTIM_GetState(const HRTIM_HandleTypeDef* hhrtim); +HAL_HRTIM_StateTypeDef HAL_HRTIM_GetState(const HRTIM_HandleTypeDef *hhrtim); -uint32_t HAL_HRTIM_GetCapturedValue(const HRTIM_HandleTypeDef * hhrtim, +uint32_t HAL_HRTIM_GetCapturedValue(const HRTIM_HandleTypeDef *hhrtim, uint32_t TimerIdx, uint32_t CaptureUnit); @@ -3577,7 +3597,7 @@ uint32_t HAL_HRTIM_WaveformGetOutputLevel(const HRTIM_HandleTypeDef *hhrtim, uint32_t TimerIdx, uint32_t Output); -uint32_t HAL_HRTIM_WaveformGetOutputState(const HRTIM_HandleTypeDef * hhrtim, +uint32_t HAL_HRTIM_WaveformGetOutputState(const HRTIM_HandleTypeDef *hhrtim, uint32_t TimerIdx, uint32_t Output); @@ -3598,8 +3618,8 @@ uint32_t HAL_HRTIM_GetIdlePushPullStatus(const HRTIM_HandleTypeDef *hhrtim, */ /** @addtogroup HRTIM_Exported_Functions_Group10 -* @{ -*/ + * @{ + */ /* IRQ handler */ void HAL_HRTIM_IRQHandler(HRTIM_HandleTypeDef *hhrtim, uint32_t TimerIdx); @@ -3617,50 +3637,50 @@ void HAL_HRTIM_SynchronizationEventCallback(HRTIM_HandleTypeDef *hhrtim); /* Timer events related callback functions */ void HAL_HRTIM_RegistersUpdateCallback(HRTIM_HandleTypeDef *hhrtim, - uint32_t TimerIdx); + uint32_t TimerIdx); void HAL_HRTIM_RepetitionEventCallback(HRTIM_HandleTypeDef *hhrtim, - uint32_t TimerIdx); + uint32_t TimerIdx); void HAL_HRTIM_Compare1EventCallback(HRTIM_HandleTypeDef *hhrtim, - uint32_t TimerIdx); + uint32_t TimerIdx); void HAL_HRTIM_Compare2EventCallback(HRTIM_HandleTypeDef *hhrtim, - uint32_t TimerIdx); + uint32_t TimerIdx); void HAL_HRTIM_Compare3EventCallback(HRTIM_HandleTypeDef *hhrtim, - uint32_t TimerIdx); + uint32_t TimerIdx); void HAL_HRTIM_Compare4EventCallback(HRTIM_HandleTypeDef *hhrtim, - uint32_t TimerIdx); + uint32_t TimerIdx); void HAL_HRTIM_Capture1EventCallback(HRTIM_HandleTypeDef *hhrtim, - uint32_t TimerIdx); + uint32_t TimerIdx); void HAL_HRTIM_Capture2EventCallback(HRTIM_HandleTypeDef *hhrtim, - uint32_t TimerIdx); + uint32_t TimerIdx); void HAL_HRTIM_DelayedProtectionCallback(HRTIM_HandleTypeDef *hhrtim, - uint32_t TimerIdx); + uint32_t TimerIdx); void HAL_HRTIM_CounterResetCallback(HRTIM_HandleTypeDef *hhrtim, - uint32_t TimerIdx); + uint32_t TimerIdx); void HAL_HRTIM_Output1SetCallback(HRTIM_HandleTypeDef *hhrtim, - uint32_t TimerIdx); + uint32_t TimerIdx); void HAL_HRTIM_Output1ResetCallback(HRTIM_HandleTypeDef *hhrtim, - uint32_t TimerIdx); + uint32_t TimerIdx); void HAL_HRTIM_Output2SetCallback(HRTIM_HandleTypeDef *hhrtim, - uint32_t TimerIdx); + uint32_t TimerIdx); void HAL_HRTIM_Output2ResetCallback(HRTIM_HandleTypeDef *hhrtim, - uint32_t TimerIdx); + uint32_t TimerIdx); void HAL_HRTIM_BurstDMATransferCallback(HRTIM_HandleTypeDef *hhrtim, - uint32_t TimerIdx); + uint32_t TimerIdx); void HAL_HRTIM_ErrorCallback(HRTIM_HandleTypeDef *hhrtim); #if (USE_HAL_HRTIM_REGISTER_CALLBACKS == 1) -HAL_StatusTypeDef HAL_HRTIM_RegisterCallback(HRTIM_HandleTypeDef * hhrtim, +HAL_StatusTypeDef HAL_HRTIM_RegisterCallback(HRTIM_HandleTypeDef *hhrtim, HAL_HRTIM_CallbackIDTypeDef CallbackID, pHRTIM_CallbackTypeDef pCallback); -HAL_StatusTypeDef HAL_HRTIM_UnRegisterCallback(HRTIM_HandleTypeDef * hhrtim, +HAL_StatusTypeDef HAL_HRTIM_UnRegisterCallback(HRTIM_HandleTypeDef *hhrtim, HAL_HRTIM_CallbackIDTypeDef CallbackID); -HAL_StatusTypeDef HAL_HRTIM_TIMxRegisterCallback(HRTIM_HandleTypeDef * hhrtim, +HAL_StatusTypeDef HAL_HRTIM_TIMxRegisterCallback(HRTIM_HandleTypeDef *hhrtim, HAL_HRTIM_CallbackIDTypeDef CallbackID, pHRTIM_TIMxCallbackTypeDef pCallback); -HAL_StatusTypeDef HAL_HRTIM_TIMxUnRegisterCallback(HRTIM_HandleTypeDef * hhrtim, +HAL_StatusTypeDef HAL_HRTIM_TIMxUnRegisterCallback(HRTIM_HandleTypeDef *hhrtim, HAL_HRTIM_CallbackIDTypeDef CallbackID); #endif /* USE_HAL_HRTIM_REGISTER_CALLBACKS */ diff --git a/system/Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_i2s.h b/system/Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_i2s.h index a057535522..af8458fbc5 100644 --- a/system/Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_i2s.h +++ b/system/Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_i2s.h @@ -480,8 +480,8 @@ void HAL_I2S_ErrorCallback(I2S_HandleTypeDef *hi2s); * @{ */ /* Peripheral Control and State functions ************************************/ -HAL_I2S_StateTypeDef HAL_I2S_GetState(I2S_HandleTypeDef *hi2s); -uint32_t HAL_I2S_GetError(I2S_HandleTypeDef *hi2s); +HAL_I2S_StateTypeDef HAL_I2S_GetState(const I2S_HandleTypeDef *hi2s); +uint32_t HAL_I2S_GetError(const I2S_HandleTypeDef *hi2s); /** * @} */ diff --git a/system/Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_nand.h b/system/Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_nand.h index 9554233202..d3f6b7e9cd 100644 --- a/system/Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_nand.h +++ b/system/Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_nand.h @@ -194,7 +194,7 @@ HAL_StatusTypeDef HAL_NAND_Init(NAND_HandleTypeDef *hnand, FMC_NAND_PCC_TimingT FMC_NAND_PCC_TimingTypeDef *AttSpace_Timing); HAL_StatusTypeDef HAL_NAND_DeInit(NAND_HandleTypeDef *hnand); -HAL_StatusTypeDef HAL_NAND_ConfigDevice(NAND_HandleTypeDef *hnand, NAND_DeviceConfigTypeDef *pDeviceConfig); +HAL_StatusTypeDef HAL_NAND_ConfigDevice(NAND_HandleTypeDef *hnand, const NAND_DeviceConfigTypeDef *pDeviceConfig); HAL_StatusTypeDef HAL_NAND_Read_ID(NAND_HandleTypeDef *hnand, NAND_IDTypeDef *pNAND_ID); diff --git a/system/Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_nor.h b/system/Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_nor.h index 992613fb5d..b17c0e8740 100644 --- a/system/Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_nor.h +++ b/system/Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_nor.h @@ -294,6 +294,13 @@ HAL_NOR_StatusTypeDef HAL_NOR_GetStatus(NOR_HandleTypeDef *hnor, uint32_t Addres ((uint32_t)((__NOR_ADDRESS) + (2U * (__ADDRESS__)))): \ ((uint32_t)((__NOR_ADDRESS) + (__ADDRESS__))))) +/** + * @brief NOR memory read data from specified address. + * @param __ADDRESS__ NOR memory address + * @retval Read data + */ +#define NOR_READ(__ADDRESS__) (*(__IO uint16_t *)((uint32_t)(__ADDRESS__))) + /** * @brief NOR memory write data to specified address. * @param __ADDRESS__ NOR memory address diff --git a/system/Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_pccard.h b/system/Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_pccard.h index 0e645017b7..63d910b6de 100644 --- a/system/Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_pccard.h +++ b/system/Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_pccard.h @@ -68,7 +68,7 @@ typedef enum typedef struct __PCCARD_HandleTypeDef #else typedef struct -#endif /* USE_HAL_PCCARD_REGISTER_CALLBACKS */ +#endif /* USE_HAL_PCCARD_REGISTER_CALLBACKS */ { FMC_PCCARD_TypeDef *Instance; /*!< Register base address for PCCARD device */ @@ -82,7 +82,7 @@ typedef struct void (* MspInitCallback)(struct __PCCARD_HandleTypeDef *hpccard); /*!< PCCARD Msp Init callback */ void (* MspDeInitCallback)(struct __PCCARD_HandleTypeDef *hpccard); /*!< PCCARD Msp DeInit callback */ void (* ItCallback)(struct __PCCARD_HandleTypeDef *hpccard); /*!< PCCARD IT callback */ -#endif +#endif /* USE_HAL_PCCARD_REGISTER_CALLBACKS */ } PCCARD_HandleTypeDef; #if (USE_HAL_PCCARD_REGISTER_CALLBACKS == 1) @@ -100,7 +100,7 @@ typedef enum * @brief HAL PCCARD Callback pointer definition */ typedef void (*pPCCARD_CallbackTypeDef)(PCCARD_HandleTypeDef *hpccard); -#endif +#endif /* USE_HAL_PCCARD_REGISTER_CALLBACKS */ /** * @} */ @@ -122,7 +122,7 @@ typedef void (*pPCCARD_CallbackTypeDef)(PCCARD_HandleTypeDef *hpccard); } while(0) #else #define __HAL_PCCARD_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_PCCARD_STATE_RESET) -#endif +#endif /* USE_HAL_PCCARD_REGISTER_CALLBACKS */ /** * @} */ @@ -137,7 +137,8 @@ typedef void (*pPCCARD_CallbackTypeDef)(PCCARD_HandleTypeDef *hpccard); */ /* Initialization/de-initialization functions **********************************/ HAL_StatusTypeDef HAL_PCCARD_Init(PCCARD_HandleTypeDef *hpccard, FMC_NAND_PCC_TimingTypeDef *ComSpaceTiming, - FMC_NAND_PCC_TimingTypeDef *AttSpaceTiming, FMC_NAND_PCC_TimingTypeDef *IOSpaceTiming); + FMC_NAND_PCC_TimingTypeDef *AttSpaceTiming, + FMC_NAND_PCC_TimingTypeDef *IOSpaceTiming); HAL_StatusTypeDef HAL_PCCARD_DeInit(PCCARD_HandleTypeDef *hpccard); void HAL_PCCARD_MspInit(PCCARD_HandleTypeDef *hpccard); void HAL_PCCARD_MspDeInit(PCCARD_HandleTypeDef *hpccard); @@ -165,7 +166,7 @@ HAL_StatusTypeDef HAL_PCCARD_RegisterCallback(PCCARD_HandleTypeDef *hpccard, HA pPCCARD_CallbackTypeDef pCallback); HAL_StatusTypeDef HAL_PCCARD_UnRegisterCallback(PCCARD_HandleTypeDef *hpccard, HAL_PCCARD_CallbackIDTypeDef CallbackId); -#endif +#endif /* USE_HAL_PCCARD_REGISTER_CALLBACKS */ /** * @} */ diff --git a/system/Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_pcd.h b/system/Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_pcd.h index 2d70b912db..422db44178 100644 --- a/system/Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_pcd.h +++ b/system/Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_pcd.h @@ -81,9 +81,6 @@ typedef enum } PCD_BCD_MsgTypeDef; - - - typedef USB_TypeDef PCD_TypeDef; typedef USB_CfgTypeDef PCD_InitTypeDef; typedef USB_EPTypeDef PCD_EPTypeDef; @@ -109,7 +106,7 @@ typedef struct uint32_t Setup[12]; /*!< Setup packet buffer */ PCD_LPM_StateTypeDef LPM_State; /*!< LPM State */ uint32_t BESL; - + uint32_t FrameNumber; /*!< Store Current Frame number */ void *pData; /*!< Pointer to upper stack Handler */ #if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U) @@ -156,6 +153,7 @@ typedef struct */ #define PCD_PHY_ULPI 1U #define PCD_PHY_EMBEDDED 2U +#define PCD_HS_PHY_EMBEDDED 3U #define PCD_PHY_UTMI 3U /** * @} @@ -204,7 +202,6 @@ typedef struct } while(0U) - /** * @} */ @@ -361,7 +358,7 @@ PCD_StateTypeDef HAL_PCD_GetState(PCD_HandleTypeDef const *hpcd); */ -#define USB_WAKEUP_EXTI_LINE (0x1U << 18) /*!< USB FS EXTI Line WakeUp Interrupt */ +#define USB_WAKEUP_EXTI_LINE (0x1UL << 18) /*!< USB FS EXTI Line WakeUp Interrupt */ /** @@ -413,8 +410,8 @@ PCD_StateTypeDef HAL_PCD_GetState(PCD_HandleTypeDef const *hpcd); */ /******************** Bit definition for USB_COUNTn_RX register *************/ -#define USB_CNTRX_NBLK_MSK (0x1FU << 10) -#define USB_CNTRX_BLSIZE (0x1U << 15) +#define USB_CNTRX_NBLK_MSK (0x1FUL << 10) +#define USB_CNTRX_BLSIZE (0x1UL << 15) /* SetENDPOINT */ #define PCD_SET_ENDPOINT(USBx, bEpNum, wRegValue) \ @@ -798,21 +795,21 @@ PCD_StateTypeDef HAL_PCD_GetState(PCD_HandleTypeDef const *hpcd); #define PCD_SET_EP_CNT_RX_REG(pdwReg, wCount) \ do { \ uint32_t wNBlocks; \ - \ - *(pdwReg) &= 0x3FFU; \ + uint16_t wRegVal = (uint16_t)(*(pdwReg) & 0x3FFU); \ \ if ((wCount) == 0U) \ { \ - *(pdwReg) |= USB_CNTRX_BLSIZE; \ + wRegVal |= (uint16_t)USB_CNTRX_BLSIZE; \ } \ else if ((wCount) <= 62U) \ { \ - PCD_CALC_BLK2((pdwReg), (wCount), wNBlocks); \ + PCD_CALC_BLK2(&wRegVal, (wCount), wNBlocks); \ } \ else \ { \ - PCD_CALC_BLK32((pdwReg), (wCount), wNBlocks); \ + PCD_CALC_BLK32(&wRegVal, (wCount), wNBlocks); \ } \ + *(pdwReg) = wRegVal; \ } while(0) /* PCD_SET_EP_CNT_RX_REG */ #define PCD_SET_EP_RX_DBUF0_CNT(USBx, bEpNum, wCount) \ @@ -965,7 +962,6 @@ PCD_StateTypeDef HAL_PCD_GetState(PCD_HandleTypeDef const *hpcd); #define PCD_GET_EP_DBUF1_CNT(USBx, bEpNum) (PCD_GET_EP_RX_CNT((USBx), (bEpNum))) - /** * @} */ diff --git a/system/Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_pcd_ex.h b/system/Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_pcd_ex.h index 4a14977654..6716ede880 100644 --- a/system/Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_pcd_ex.h +++ b/system/Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_pcd_ex.h @@ -47,7 +47,6 @@ extern "C" { */ - HAL_StatusTypeDef HAL_PCDEx_PMAConfig(PCD_HandleTypeDef *hpcd, uint16_t ep_addr, uint16_t ep_kind, uint32_t pmaadress); diff --git a/system/Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_rcc.h b/system/Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_rcc.h index f083587779..8afff3186c 100644 --- a/system/Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_rcc.h +++ b/system/Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_rcc.h @@ -1686,8 +1686,8 @@ typedef struct /* Initialization and de-initialization functions ******************************/ HAL_StatusTypeDef HAL_RCC_DeInit(void); -HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct); -HAL_StatusTypeDef HAL_RCC_ClockConfig(RCC_ClkInitTypeDef *RCC_ClkInitStruct, uint32_t FLatency); +HAL_StatusTypeDef HAL_RCC_OscConfig(const RCC_OscInitTypeDef *RCC_OscInitStruct); +HAL_StatusTypeDef HAL_RCC_ClockConfig(const RCC_ClkInitTypeDef *RCC_ClkInitStruct, uint32_t FLatency); /** * @} diff --git a/system/Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_smartcard.h b/system/Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_smartcard.h index 1c042778dd..71ca4b6448 100644 --- a/system/Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_smartcard.h +++ b/system/Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_smartcard.h @@ -666,13 +666,13 @@ typedef enum */ #define __HAL_SMARTCARD_DISABLE_IT(__HANDLE__, __INTERRUPT__) (((((__INTERRUPT__) & SMARTCARD_CR_MASK) >>\ SMARTCARD_CR_POS) == 1U)?\ - ((__HANDLE__)->Instance->CR1 &= ~ (1U <<\ + ((__HANDLE__)->Instance->CR1 &= ~ (1UL <<\ ((__INTERRUPT__) & SMARTCARD_IT_MASK))): \ ((((__INTERRUPT__) & SMARTCARD_CR_MASK) >>\ SMARTCARD_CR_POS) == 2U)?\ - ((__HANDLE__)->Instance->CR2 &= ~ (1U <<\ + ((__HANDLE__)->Instance->CR2 &= ~ (1UL <<\ ((__INTERRUPT__) & SMARTCARD_IT_MASK))): \ - ((__HANDLE__)->Instance->CR3 &= ~ (1U <<\ + ((__HANDLE__)->Instance->CR3 &= ~ (1UL <<\ ((__INTERRUPT__) & SMARTCARD_IT_MASK)))) /** @brief Check whether the specified SmartCard interrupt has occurred or not. diff --git a/system/Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_spi.h b/system/Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_spi.h index 0b0e79e9fb..8ac00b0682 100644 --- a/system/Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_spi.h +++ b/system/Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_spi.h @@ -118,7 +118,7 @@ typedef struct __SPI_HandleTypeDef SPI_InitTypeDef Init; /*!< SPI communication parameters */ - uint8_t *pTxBuffPtr; /*!< Pointer to SPI Tx transfer Buffer */ + const uint8_t *pTxBuffPtr; /*!< Pointer to SPI Tx transfer Buffer */ uint16_t TxXferSize; /*!< SPI Tx Transfer size */ @@ -426,11 +426,12 @@ typedef void (*pSPI_CallbackTypeDef)(SPI_HandleTypeDef *hspi); /*!< pointer to * @retval None */ #if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U) -#define __HAL_SPI_RESET_HANDLE_STATE(__HANDLE__) do{ \ - (__HANDLE__)->State = HAL_SPI_STATE_RESET; \ - (__HANDLE__)->MspInitCallback = NULL; \ - (__HANDLE__)->MspDeInitCallback = NULL; \ - } while(0) +#define __HAL_SPI_RESET_HANDLE_STATE(__HANDLE__) \ + do{ \ + (__HANDLE__)->State = HAL_SPI_STATE_RESET; \ + (__HANDLE__)->MspInitCallback = NULL; \ + (__HANDLE__)->MspDeInitCallback = NULL; \ + } while(0) #else #define __HAL_SPI_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_SPI_STATE_RESET) #endif /* USE_HAL_SPI_REGISTER_CALLBACKS */ @@ -533,7 +534,7 @@ typedef void (*pSPI_CallbackTypeDef)(SPI_HandleTypeDef *hspi); /*!< pointer to __IO uint32_t tmpreg_fre = 0x00U; \ tmpreg_fre = (__HANDLE__)->Instance->SR; \ UNUSED(tmpreg_fre); \ - }while(0U) + } while(0U) /** @brief Enable the SPI peripheral. * @param __HANDLE__ specifies the SPI Handle. @@ -577,8 +578,11 @@ typedef void (*pSPI_CallbackTypeDef)(SPI_HandleTypeDef *hspi); /*!< pointer to * This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral. * @retval None */ -#define SPI_RESET_CRC(__HANDLE__) do{CLEAR_BIT((__HANDLE__)->Instance->CR1, SPI_CR1_CRCEN);\ - SET_BIT((__HANDLE__)->Instance->CR1, SPI_CR1_CRCEN);}while(0U) +#define SPI_RESET_CRC(__HANDLE__) \ + do{ \ + CLEAR_BIT((__HANDLE__)->Instance->CR1, SPI_CR1_CRCEN); \ + SET_BIT((__HANDLE__)->Instance->CR1, SPI_CR1_CRCEN); \ + } while(0U) /** @brief Check whether the specified SPI flag is set or not. * @param __SR__ copy of SPI SR register. @@ -596,7 +600,7 @@ typedef void (*pSPI_CallbackTypeDef)(SPI_HandleTypeDef *hspi); /*!< pointer to * @retval SET or RESET. */ #define SPI_CHECK_FLAG(__SR__, __FLAG__) ((((__SR__) & ((__FLAG__) & SPI_FLAG_MASK)) == \ - ((__FLAG__) & SPI_FLAG_MASK)) ? SET : RESET) + ((__FLAG__) & SPI_FLAG_MASK)) ? SET : RESET) /** @brief Check whether the specified SPI Interrupt is set or not. * @param __CR2__ copy of SPI CR2 register. @@ -608,7 +612,7 @@ typedef void (*pSPI_CallbackTypeDef)(SPI_HandleTypeDef *hspi); /*!< pointer to * @retval SET or RESET. */ #define SPI_CHECK_IT_SOURCE(__CR2__, __INTERRUPT__) ((((__CR2__) & (__INTERRUPT__)) == \ - (__INTERRUPT__)) ? SET : RESET) + (__INTERRUPT__)) ? SET : RESET) /** @brief Checks if SPI Mode parameter is in allowed range. * @param __MODE__ specifies the SPI Mode. @@ -746,7 +750,7 @@ typedef void (*pSPI_CallbackTypeDef)(SPI_HandleTypeDef *hspi); /*!< pointer to */ #define IS_SPI_CRC_POLYNOMIAL(__POLYNOMIAL__) (((__POLYNOMIAL__) >= 0x1U) && \ ((__POLYNOMIAL__) <= 0xFFFFU) && \ - (((__POLYNOMIAL__)&0x1U) != 0U)) + (((__POLYNOMIAL__)&0x1U) != 0U)) /** @brief Checks if DMA handle is valid. * @param __HANDLE__ specifies a DMA Handle. @@ -789,17 +793,17 @@ HAL_StatusTypeDef HAL_SPI_UnRegisterCallback(SPI_HandleTypeDef *hspi, HAL_SPI_Ca * @{ */ /* I/O operation functions ***************************************************/ -HAL_StatusTypeDef HAL_SPI_Transmit(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size, uint32_t Timeout); +HAL_StatusTypeDef HAL_SPI_Transmit(SPI_HandleTypeDef *hspi, const uint8_t *pData, uint16_t Size, uint32_t Timeout); HAL_StatusTypeDef HAL_SPI_Receive(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size, uint32_t Timeout); -HAL_StatusTypeDef HAL_SPI_TransmitReceive(SPI_HandleTypeDef *hspi, uint8_t *pTxData, uint8_t *pRxData, uint16_t Size, - uint32_t Timeout); -HAL_StatusTypeDef HAL_SPI_Transmit_IT(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size); +HAL_StatusTypeDef HAL_SPI_TransmitReceive(SPI_HandleTypeDef *hspi, const uint8_t *pTxData, uint8_t *pRxData, + uint16_t Size, uint32_t Timeout); +HAL_StatusTypeDef HAL_SPI_Transmit_IT(SPI_HandleTypeDef *hspi, const uint8_t *pData, uint16_t Size); HAL_StatusTypeDef HAL_SPI_Receive_IT(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size); -HAL_StatusTypeDef HAL_SPI_TransmitReceive_IT(SPI_HandleTypeDef *hspi, uint8_t *pTxData, uint8_t *pRxData, +HAL_StatusTypeDef HAL_SPI_TransmitReceive_IT(SPI_HandleTypeDef *hspi, const uint8_t *pTxData, uint8_t *pRxData, uint16_t Size); -HAL_StatusTypeDef HAL_SPI_Transmit_DMA(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size); +HAL_StatusTypeDef HAL_SPI_Transmit_DMA(SPI_HandleTypeDef *hspi, const uint8_t *pData, uint16_t Size); HAL_StatusTypeDef HAL_SPI_Receive_DMA(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size); -HAL_StatusTypeDef HAL_SPI_TransmitReceive_DMA(SPI_HandleTypeDef *hspi, uint8_t *pTxData, uint8_t *pRxData, +HAL_StatusTypeDef HAL_SPI_TransmitReceive_DMA(SPI_HandleTypeDef *hspi, const uint8_t *pTxData, uint8_t *pRxData, uint16_t Size); HAL_StatusTypeDef HAL_SPI_DMAPause(SPI_HandleTypeDef *hspi); HAL_StatusTypeDef HAL_SPI_DMAResume(SPI_HandleTypeDef *hspi); @@ -825,8 +829,8 @@ void HAL_SPI_AbortCpltCallback(SPI_HandleTypeDef *hspi); * @{ */ /* Peripheral State and Error functions ***************************************/ -HAL_SPI_StateTypeDef HAL_SPI_GetState(SPI_HandleTypeDef *hspi); -uint32_t HAL_SPI_GetError(SPI_HandleTypeDef *hspi); +HAL_SPI_StateTypeDef HAL_SPI_GetState(const SPI_HandleTypeDef *hspi); +uint32_t HAL_SPI_GetError(const SPI_HandleTypeDef *hspi); /** * @} */ diff --git a/system/Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_tim.h b/system/Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_tim.h index 316110182f..0f3d9d1955 100644 --- a/system/Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_tim.h +++ b/system/Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_tim.h @@ -294,6 +294,7 @@ typedef struct uint32_t Break2Filter; /*!< TIM break2 input filter.This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */ #endif /*TIM_BDTR_BK2E */ + uint32_t AutomaticOutput; /*!< TIM Automatic Output Enable state, This parameter can be a value of @ref TIM_AOE_Bit_Set_Reset */ } TIM_BreakDeadTimeConfigTypeDef; @@ -1328,8 +1329,8 @@ typedef void (*pTIM_CallbackTypeDef)(TIM_HandleTypeDef *htim); /*!< pointer to * @arg TIM_FLAG_CC2: Capture/Compare 2 interrupt flag * @arg TIM_FLAG_CC3: Capture/Compare 3 interrupt flag * @arg TIM_FLAG_CC4: Capture/Compare 4 interrupt flag - * @arg TIM_FLAG_CC5: Capture/Compare 5 interrupt flag (*) - * @arg TIM_FLAG_CC6: Capture/Compare 6 interrupt flag (*) + * @arg TIM_FLAG_CC5: Compare 5 interrupt flag (*) + * @arg TIM_FLAG_CC6: Compare 6 interrupt flag (*) * @arg TIM_FLAG_COM: Commutation interrupt flag * @arg TIM_FLAG_TRIGGER: Trigger interrupt flag * @arg TIM_FLAG_BREAK: Break interrupt flag @@ -1352,8 +1353,8 @@ typedef void (*pTIM_CallbackTypeDef)(TIM_HandleTypeDef *htim); /*!< pointer to * @arg TIM_FLAG_CC2: Capture/Compare 2 interrupt flag * @arg TIM_FLAG_CC3: Capture/Compare 3 interrupt flag * @arg TIM_FLAG_CC4: Capture/Compare 4 interrupt flag - * @arg TIM_FLAG_CC5: Capture/Compare 5 interrupt flag (*) - * @arg TIM_FLAG_CC6: Capture/Compare 6 interrupt flag (*) + * @arg TIM_FLAG_CC5: Compare 5 interrupt flag (*) + * @arg TIM_FLAG_CC6: Compare 6 interrupt flag (*) * @arg TIM_FLAG_COM: Commutation interrupt flag * @arg TIM_FLAG_TRIGGER: Trigger interrupt flag * @arg TIM_FLAG_BREAK: Break interrupt flag @@ -1810,7 +1811,12 @@ mode. */ /* The counter of a timer instance is disabled only if all the CCx and CCxN channels have been disabled */ +#if defined(TIM_CCER_CC5E) && defined(TIM_CCER_CC6E) +#define TIM_CCER_CCxE_MASK ((uint32_t)(TIM_CCER_CC1E | TIM_CCER_CC2E | TIM_CCER_CC3E | TIM_CCER_CC4E | \ + TIM_CCER_CC5E | TIM_CCER_CC6E)) +#else #define TIM_CCER_CCxE_MASK ((uint32_t)(TIM_CCER_CC1E | TIM_CCER_CC2E | TIM_CCER_CC3E | TIM_CCER_CC4E)) +#endif /* TIM_CCER_CC5E && TIM_CCER_CC6E */ #define TIM_CCER_CCxNE_MASK ((uint32_t)(TIM_CCER_CC1NE | TIM_CCER_CC2NE | TIM_CCER_CC3NE)) /** * @} @@ -2223,20 +2229,15 @@ mode. ((__CHANNEL__) == TIM_CHANNEL_5) ? ((__HANDLE__)->ChannelState[4] = (__CHANNEL_STATE__)) :\ ((__HANDLE__)->ChannelState[5] = (__CHANNEL_STATE__))) -#define TIM_CHANNEL_STATE_SET_ALL(__HANDLE__, __CHANNEL_STATE__) do { \ - (__HANDLE__)->ChannelState[0] = \ - (__CHANNEL_STATE__); \ - (__HANDLE__)->ChannelState[1] = \ - (__CHANNEL_STATE__); \ - (__HANDLE__)->ChannelState[2] = \ - (__CHANNEL_STATE__); \ - (__HANDLE__)->ChannelState[3] = \ - (__CHANNEL_STATE__); \ - (__HANDLE__)->ChannelState[4] = \ - (__CHANNEL_STATE__); \ - (__HANDLE__)->ChannelState[5] = \ - (__CHANNEL_STATE__); \ - } while(0) +#define TIM_CHANNEL_STATE_SET_ALL(__HANDLE__, __CHANNEL_STATE__)\ + do {\ + (__HANDLE__)->ChannelState[0] = (__CHANNEL_STATE__); \ + (__HANDLE__)->ChannelState[1] = (__CHANNEL_STATE__); \ + (__HANDLE__)->ChannelState[2] = (__CHANNEL_STATE__); \ + (__HANDLE__)->ChannelState[3] = (__CHANNEL_STATE__); \ + (__HANDLE__)->ChannelState[4] = (__CHANNEL_STATE__); \ + (__HANDLE__)->ChannelState[5] = (__CHANNEL_STATE__); \ + } while(0) #else #define TIM_CHANNEL_STATE_GET(__HANDLE__, __CHANNEL__)\ (((__CHANNEL__) == TIM_CHANNEL_1) ? (__HANDLE__)->ChannelState[0] :\ @@ -2250,12 +2251,13 @@ mode. ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->ChannelState[2] = (__CHANNEL_STATE__)) :\ ((__HANDLE__)->ChannelState[3] = (__CHANNEL_STATE__))) -#define TIM_CHANNEL_STATE_SET_ALL(__HANDLE__, __CHANNEL_STATE__) do { \ - (__HANDLE__)->ChannelState[0] = (__CHANNEL_STATE__); \ - (__HANDLE__)->ChannelState[1] = (__CHANNEL_STATE__); \ - (__HANDLE__)->ChannelState[2] = (__CHANNEL_STATE__); \ - (__HANDLE__)->ChannelState[3] = (__CHANNEL_STATE__); \ - } while(0) +#define TIM_CHANNEL_STATE_SET_ALL(__HANDLE__, __CHANNEL_STATE__)\ + do {\ + (__HANDLE__)->ChannelState[0] = (__CHANNEL_STATE__);\ + (__HANDLE__)->ChannelState[1] = (__CHANNEL_STATE__);\ + (__HANDLE__)->ChannelState[2] = (__CHANNEL_STATE__);\ + (__HANDLE__)->ChannelState[3] = (__CHANNEL_STATE__);\ + } while(0) #endif /* TIM_CCER_CC5E && TIM_CCER_CC6E */ #define TIM_CHANNEL_N_STATE_GET(__HANDLE__, __CHANNEL__)\ @@ -2270,16 +2272,13 @@ mode. ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->ChannelNState[2] = (__CHANNEL_STATE__)) :\ ((__HANDLE__)->ChannelNState[3] = (__CHANNEL_STATE__))) -#define TIM_CHANNEL_N_STATE_SET_ALL(__HANDLE__, __CHANNEL_STATE__) do { \ - (__HANDLE__)->ChannelNState[0] = \ - (__CHANNEL_STATE__); \ - (__HANDLE__)->ChannelNState[1] = \ - (__CHANNEL_STATE__); \ - (__HANDLE__)->ChannelNState[2] = \ - (__CHANNEL_STATE__); \ - (__HANDLE__)->ChannelNState[3] = \ - (__CHANNEL_STATE__); \ - } while(0) +#define TIM_CHANNEL_N_STATE_SET_ALL(__HANDLE__, __CHANNEL_STATE__)\ + do {\ + (__HANDLE__)->ChannelNState[0] = (__CHANNEL_STATE__); \ + (__HANDLE__)->ChannelNState[1] = (__CHANNEL_STATE__); \ + (__HANDLE__)->ChannelNState[2] = (__CHANNEL_STATE__); \ + (__HANDLE__)->ChannelNState[3] = (__CHANNEL_STATE__); \ + } while(0) /** * @} diff --git a/system/Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_uart.h b/system/Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_uart.h index d57ae55924..bddac1c78d 100644 --- a/system/Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_uart.h +++ b/system/Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_uart.h @@ -1165,7 +1165,7 @@ typedef void (*pUART_RxEventCallbackTypeDef) * divided by the smallest oversampling used on the USART (i.e. 8) * @retval SET (__BAUDRATE__ is valid) or RESET (__BAUDRATE__ is invalid) */ -#define IS_UART_BAUDRATE(__BAUDRATE__) ((__BAUDRATE__) < 9000001U) +#define IS_UART_BAUDRATE(__BAUDRATE__) ((__BAUDRATE__) <= 9000000U) /** @brief Check UART assertion time. * @param __TIME__ 5-bit value assertion time. diff --git a/system/Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_usart.h b/system/Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_usart.h index a55d1cc90f..7586321974 100644 --- a/system/Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_usart.h +++ b/system/Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_usart.h @@ -483,10 +483,10 @@ typedef void (*pUSART_CallbackTypeDef)(USART_HandleTypeDef *husart); /*!< poin */ #define __HAL_USART_ENABLE_IT(__HANDLE__, __INTERRUPT__)\ (((((__INTERRUPT__) & USART_CR_MASK) >> USART_CR_POS) == 1U)?\ - ((__HANDLE__)->Instance->CR1 |= (1U << ((__INTERRUPT__) & USART_IT_MASK))): \ + ((__HANDLE__)->Instance->CR1 |= (1UL << ((__INTERRUPT__) & USART_IT_MASK))): \ ((((__INTERRUPT__) & USART_CR_MASK) >> USART_CR_POS) == 2U)?\ - ((__HANDLE__)->Instance->CR2 |= (1U << ((__INTERRUPT__) & USART_IT_MASK))): \ - ((__HANDLE__)->Instance->CR3 |= (1U << ((__INTERRUPT__) & USART_IT_MASK)))) + ((__HANDLE__)->Instance->CR2 |= (1UL << ((__INTERRUPT__) & USART_IT_MASK))): \ + ((__HANDLE__)->Instance->CR3 |= (1UL << ((__INTERRUPT__) & USART_IT_MASK)))) /** @brief Disable the specified USART interrupt. * @param __HANDLE__ specifies the USART Handle. @@ -502,10 +502,10 @@ typedef void (*pUSART_CallbackTypeDef)(USART_HandleTypeDef *husart); /*!< poin */ #define __HAL_USART_DISABLE_IT(__HANDLE__, __INTERRUPT__)\ (((((__INTERRUPT__) & USART_CR_MASK) >> USART_CR_POS) == 1U)?\ - ((__HANDLE__)->Instance->CR1 &= ~ (1U << ((__INTERRUPT__) & USART_IT_MASK))): \ + ((__HANDLE__)->Instance->CR1 &= ~ (1UL << ((__INTERRUPT__) & USART_IT_MASK))): \ ((((__INTERRUPT__) & USART_CR_MASK) >> USART_CR_POS) == 2U)?\ - ((__HANDLE__)->Instance->CR2 &= ~ (1U << ((__INTERRUPT__) & USART_IT_MASK))): \ - ((__HANDLE__)->Instance->CR3 &= ~ (1U << ((__INTERRUPT__) & USART_IT_MASK)))) + ((__HANDLE__)->Instance->CR2 &= ~ (1UL << ((__INTERRUPT__) & USART_IT_MASK))): \ + ((__HANDLE__)->Instance->CR3 &= ~ (1UL << ((__INTERRUPT__) & USART_IT_MASK)))) /** @brief Check whether the specified USART interrupt has occurred or not. * @param __HANDLE__ specifies the USART Handle. diff --git a/system/Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_wwdg.h b/system/Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_wwdg.h index 1513db6d48..8343237e82 100644 --- a/system/Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_wwdg.h +++ b/system/Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_wwdg.h @@ -183,7 +183,7 @@ typedef void (*pWWDG_CallbackTypeDef)(WWDG_HandleTypeDef *hppp); /*!< pointer t /** * @brief Enable the WWDG early wakeup interrupt. - * @param __HANDLE__: WWDG handle + * @param __HANDLE__ WWDG handle * @param __INTERRUPT__ specifies the interrupt to enable. * This parameter can be one of the following values: * @arg WWDG_IT_EWI: Early wakeup interrupt diff --git a/system/Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_ll_adc.h b/system/Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_ll_adc.h index 59017b5e22..ed24fca9ba 100644 --- a/system/Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_ll_adc.h +++ b/system/Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_ll_adc.h @@ -1630,13 +1630,13 @@ typedef struct (((__DECIMAL_NB__) <= 9U) \ ? ( \ ((__DECIMAL_NB__) << ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS) | \ - (ADC_AWD2CR_AWD2CH_0 << (__DECIMAL_NB__)) | \ + (0x00000001UL << (__DECIMAL_NB__)) | \ (ADC_SMPR1_REGOFFSET | (((uint32_t) (3U * (__DECIMAL_NB__))) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) \ ) \ : \ ( \ ((__DECIMAL_NB__) << ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS) | \ - (ADC_AWD2CR_AWD2CH_0 << (__DECIMAL_NB__)) | \ + (0x00000001UL << (__DECIMAL_NB__)) | \ (ADC_SMPR2_REGOFFSET | (((uint32_t) (3U * ((__DECIMAL_NB__) - 10U))) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) \ ) \ ) diff --git a/system/Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_ll_cortex.h b/system/Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_ll_cortex.h index a16dc6275b..0dbd0ada2a 100644 --- a/system/Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_ll_cortex.h +++ b/system/Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_ll_cortex.h @@ -587,7 +587,7 @@ __STATIC_INLINE void LL_MPU_ConfigRegion(uint32_t Region, uint32_t SubRegionDisa /* Set base address */ WRITE_REG(MPU->RBAR, (Address & 0xFFFFFFE0U)); /* Configure MPU */ - WRITE_REG(MPU->RASR, (MPU_RASR_ENABLE_Msk | Attributes | SubRegionDisable << MPU_RASR_SRD_Pos)); + WRITE_REG(MPU->RASR, (MPU_RASR_ENABLE_Msk | Attributes | (SubRegionDisable << MPU_RASR_SRD_Pos))); } /** diff --git a/system/Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_ll_fmc.h b/system/Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_ll_fmc.h index 6b1328ddfb..395f76a490 100644 --- a/system/Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_ll_fmc.h +++ b/system/Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_ll_fmc.h @@ -61,7 +61,7 @@ extern "C" { #define IS_FMC_WAIT_POLARITY(__POLARITY__) (((__POLARITY__) == FMC_WAIT_SIGNAL_POLARITY_LOW) || \ ((__POLARITY__) == FMC_WAIT_SIGNAL_POLARITY_HIGH)) #define IS_FMC_WRAP_MODE(__MODE__) (((__MODE__) == FMC_WRAP_MODE_DISABLE) || \ - ((__MODE__) == FMC_WRAP_MODE_ENABLE)) + ((__MODE__) == FMC_WRAP_MODE_ENABLE)) #define IS_FMC_WAIT_SIGNAL_ACTIVE(__ACTIVE__) (((__ACTIVE__) == FMC_WAIT_TIMING_BEFORE_WS) || \ ((__ACTIVE__) == FMC_WAIT_TIMING_DURING_WS)) #define IS_FMC_WRITE_OPERATION(__OPERATION__) (((__OPERATION__) == FMC_WRITE_OPERATION_DISABLE) || \ @@ -91,9 +91,9 @@ extern "C" { #define IS_FMC_NAND_BANK(__BANK__) ((__BANK__) == FMC_NAND_BANK3) #define IS_FMC_WAIT_FEATURE(__FEATURE__) (((__FEATURE__) == FMC_NAND_PCC_WAIT_FEATURE_DISABLE) || \ - ((__FEATURE__) == FMC_NAND_PCC_WAIT_FEATURE_ENABLE)) + ((__FEATURE__) == FMC_NAND_PCC_WAIT_FEATURE_ENABLE)) #define IS_FMC_NAND_MEMORY_WIDTH(__WIDTH__) (((__WIDTH__) == FMC_NAND_PCC_MEM_BUS_WIDTH_8) || \ - ((__WIDTH__) == FMC_NAND_PCC_MEM_BUS_WIDTH_16)) + ((__WIDTH__) == FMC_NAND_PCC_MEM_BUS_WIDTH_16)) #define IS_FMC_ECC_STATE(__STATE__) (((__STATE__) == FMC_NAND_ECC_DISABLE) || \ ((__STATE__) == FMC_NAND_ECC_ENABLE)) @@ -156,57 +156,58 @@ extern "C" { typedef struct { uint32_t NSBank; /*!< Specifies the NORSRAM memory device that will be used. - This parameter can be a value of @ref FMC_NORSRAM_Bank */ + This parameter can be a value of @ref FMC_NORSRAM_Bank */ uint32_t DataAddressMux; /*!< Specifies whether the address and data values are multiplexed on the data bus or not. - This parameter can be a value of @ref FMC_Data_Address_Bus_Multiplexing */ + This parameter can be a value of @ref FMC_Data_Address_Bus_Multiplexing*/ uint32_t MemoryType; /*!< Specifies the type of external memory attached to the corresponding memory device. - This parameter can be a value of @ref FMC_Memory_Type */ + This parameter can be a value of @ref FMC_Memory_Type */ uint32_t MemoryDataWidth; /*!< Specifies the external memory device width. - This parameter can be a value of @ref FMC_NORSRAM_Data_Width */ + This parameter can be a value of @ref FMC_NORSRAM_Data_Width */ uint32_t BurstAccessMode; /*!< Enables or disables the burst access mode for Flash memory, valid only with synchronous burst Flash memories. - This parameter can be a value of @ref FMC_Burst_Access_Mode */ + This parameter can be a value of @ref FMC_Burst_Access_Mode */ uint32_t WaitSignalPolarity; /*!< Specifies the wait signal polarity, valid only when accessing the Flash memory in burst mode. - This parameter can be a value of @ref FMC_Wait_Signal_Polarity */ + This parameter can be a value of @ref FMC_Wait_Signal_Polarity */ uint32_t WrapMode; /*!< Enables or disables the Wrapped burst access mode for Flash memory, valid only when accessing Flash memories in burst mode. - This parameter can be a value of @ref FMC_Wrap_Mode */ + This parameter can be a value of @ref FMC_Wrap_Mode */ uint32_t WaitSignalActive; /*!< Specifies if the wait signal is asserted by the memory one clock cycle before the wait state or during the wait state, valid only when accessing memories in burst mode. - This parameter can be a value of @ref FMC_Wait_Timing */ + This parameter can be a value of @ref FMC_Wait_Timing */ - uint32_t WriteOperation; /*!< Enables or disables the write operation in the selected device by the FMC. - This parameter can be a value of @ref FMC_Write_Operation */ + uint32_t WriteOperation; /*!< Enables or disables the write operation in the selected device + by the FMC. + This parameter can be a value of @ref FMC_Write_Operation */ uint32_t WaitSignal; /*!< Enables or disables the wait state insertion via wait signal, valid for Flash memory access in burst mode. - This parameter can be a value of @ref FMC_Wait_Signal */ + This parameter can be a value of @ref FMC_Wait_Signal */ uint32_t ExtendedMode; /*!< Enables or disables the extended mode. - This parameter can be a value of @ref FMC_Extended_Mode */ + This parameter can be a value of @ref FMC_Extended_Mode */ uint32_t AsynchronousWait; /*!< Enables or disables wait signal during asynchronous transfers, valid only with asynchronous Flash memories. - This parameter can be a value of @ref FMC_AsynchronousWait */ + This parameter can be a value of @ref FMC_AsynchronousWait */ uint32_t WriteBurst; /*!< Enables or disables the write burst operation. - This parameter can be a value of @ref FMC_Write_Burst */ + This parameter can be a value of @ref FMC_Write_Burst */ uint32_t ContinuousClock; /*!< Enables or disables the FMC clock output to external memory devices. This parameter is only enabled through the FMC_BCR1 register, and don't care through FMC_BCR2..4 registers. - This parameter can be a value of @ref FMC_Continous_Clock */ + This parameter can be a value of @ref FMC_Continous_Clock */ } FMC_NORSRAM_InitTypeDef; /** @@ -250,7 +251,7 @@ typedef struct in NOR Flash memories with synchronous burst mode enable */ uint32_t AccessMode; /*!< Specifies the asynchronous access mode. - This parameter can be a value of @ref FMC_Access_Mode */ + This parameter can be a value of @ref FMC_Access_Mode */ } FMC_NORSRAM_TimingTypeDef; #endif /* FMC_BANK1 */ @@ -334,7 +335,7 @@ typedef struct uint32_t TARSetupTime; /*!< Defines the number of HCLK cycles to configure the delay between ALE low and RE low. This parameter can be a number between Min_Data = 0 and Max_Data = 255 */ -}FMC_PCCARD_InitTypeDef; +} FMC_PCCARD_InitTypeDef; #endif /* FMC_BANK4 */ /** @@ -655,8 +656,9 @@ typedef struct * @param __BANK__ FMC_NAND Bank * @retval None */ -#define __FMC_NAND_ENABLE(__INSTANCE__, __BANK__) (((__BANK__) == FMC_NAND_BANK2)? ((__INSTANCE__)->PCR2 |= FMC_PCRx_PBKEN): \ - ((__INSTANCE__)->PCR3 |= FMC_PCRx_PBKEN)) +#define __FMC_NAND_ENABLE(__INSTANCE__, __BANK__) (((__BANK__) == FMC_NAND_BANK2) ? \ + ((__INSTANCE__)->PCR2 |= FMC_PCRx_PBKEN) : \ + ((__INSTANCE__)->PCR3 |= FMC_PCRx_PBKEN)) /** * @brief Disable the NAND device access. @@ -664,8 +666,9 @@ typedef struct * @param __BANK__ FMC_NAND Bank * @retval None */ -#define __FMC_NAND_DISABLE(__INSTANCE__, __BANK__) (((__BANK__) == FMC_NAND_BANK2)? CLEAR_BIT((__INSTANCE__)->PCR2, FMC_PCRx_PBKEN): \ - CLEAR_BIT((__INSTANCE__)->PCR3, FMC_PCRx_PBKEN)) +#define __FMC_NAND_DISABLE(__INSTANCE__, __BANK__) (((__BANK__) == FMC_NAND_BANK2) ? \ + CLEAR_BIT((__INSTANCE__)->PCR2, FMC_PCRx_PBKEN) : \ + CLEAR_BIT((__INSTANCE__)->PCR3, FMC_PCRx_PBKEN)) /** * @} @@ -694,7 +697,7 @@ typedef struct * @} */ -#endif +#endif /* FMC_BANK4 */ #if defined(FMC_BANK3) /** @defgroup FMC_LL_NAND_Interrupt FMC NAND Interrupt * @brief macros to handle NAND interrupts @@ -712,8 +715,9 @@ typedef struct * @arg FMC_IT_FALLING_EDGE: Interrupt falling edge. * @retval None */ -#define __FMC_NAND_ENABLE_IT(__INSTANCE__, __BANK__, __INTERRUPT__) (((__BANK__) == FMC_NAND_BANK2)? ((__INSTANCE__)->SR2 |= (__INTERRUPT__)): \ - ((__INSTANCE__)->SR3 |= (__INTERRUPT__))) +#define __FMC_NAND_ENABLE_IT(__INSTANCE__, __BANK__, __INTERRUPT__) (((__BANK__) == FMC_NAND_BANK2) ? \ + ((__INSTANCE__)->SR2 |= (__INTERRUPT__)) : \ + ((__INSTANCE__)->SR3 |= (__INTERRUPT__))) /** * @brief Disable the NAND device interrupt. @@ -726,8 +730,9 @@ typedef struct * @arg FMC_IT_FALLING_EDGE: Interrupt falling edge. * @retval None */ -#define __FMC_NAND_DISABLE_IT(__INSTANCE__, __BANK__, __INTERRUPT__) (((__BANK__) == FMC_NAND_BANK2)? ((__INSTANCE__)->SR2 &= ~(__INTERRUPT__)): \ - ((__INSTANCE__)->SR3 &= ~(__INTERRUPT__))) +#define __FMC_NAND_DISABLE_IT(__INSTANCE__, __BANK__, __INTERRUPT__) (((__BANK__) == FMC_NAND_BANK2) ? \ + ((__INSTANCE__)->SR2 &= ~(__INTERRUPT__)) : \ + ((__INSTANCE__)->SR3 &= ~(__INTERRUPT__))) /** * @brief Get flag status of the NAND device. @@ -741,8 +746,9 @@ typedef struct * @arg FMC_FLAG_FEMPT: FIFO empty flag. * @retval The state of FLAG (SET or RESET). */ -#define __FMC_NAND_GET_FLAG(__INSTANCE__, __BANK__, __FLAG__) (((__BANK__) == FMC_NAND_BANK2)? (((__INSTANCE__)->SR2 &(__FLAG__)) == (__FLAG__)): \ - (((__INSTANCE__)->SR3 &(__FLAG__)) == (__FLAG__))) +#define __FMC_NAND_GET_FLAG(__INSTANCE__, __BANK__, __FLAG__) (((__BANK__) == FMC_NAND_BANK2) ? \ + (((__INSTANCE__)->SR2 &(__FLAG__)) == (__FLAG__)) : \ + (((__INSTANCE__)->SR3 &(__FLAG__)) == (__FLAG__))) /** * @brief Clear flag status of the NAND device. @@ -756,8 +762,9 @@ typedef struct * @arg FMC_FLAG_FEMPT: FIFO empty flag. * @retval None */ -#define __FMC_NAND_CLEAR_FLAG(__INSTANCE__, __BANK__, __FLAG__) (((__BANK__) == FMC_NAND_BANK2)? ((__INSTANCE__)->SR2 &= ~(__FLAG__)): \ - ((__INSTANCE__)->SR3 &= ~(__FLAG__))) +#define __FMC_NAND_CLEAR_FLAG(__INSTANCE__, __BANK__, __FLAG__) (((__BANK__) == FMC_NAND_BANK2) ? \ + ((__INSTANCE__)->SR2 &= ~(__FLAG__)) : \ + ((__INSTANCE__)->SR3 &= ~(__FLAG__))) /** * @} @@ -823,7 +830,7 @@ typedef struct /** * @} */ -#endif +#endif /* FMC_BANK4 */ /** * @} @@ -837,8 +844,8 @@ typedef struct /** @defgroup FMC_LL_Private_Functions FMC LL Private Functions * @{ */ - #if defined(FMC_BANK1) + /** @defgroup FMC_LL_NORSRAM NOR SRAM * @{ */ @@ -846,11 +853,11 @@ typedef struct * @{ */ HAL_StatusTypeDef FMC_NORSRAM_Init(FMC_NORSRAM_TypeDef *Device, - FMC_NORSRAM_InitTypeDef *Init); + const FMC_NORSRAM_InitTypeDef *Init); HAL_StatusTypeDef FMC_NORSRAM_Timing_Init(FMC_NORSRAM_TypeDef *Device, - FMC_NORSRAM_TimingTypeDef *Timing, uint32_t Bank); + const FMC_NORSRAM_TimingTypeDef *Timing, uint32_t Bank); HAL_StatusTypeDef FMC_NORSRAM_Extended_Timing_Init(FMC_NORSRAM_EXTENDED_TypeDef *Device, - FMC_NORSRAM_TimingTypeDef *Timing, uint32_t Bank, + const FMC_NORSRAM_TimingTypeDef *Timing, uint32_t Bank, uint32_t ExtendedMode); HAL_StatusTypeDef FMC_NORSRAM_DeInit(FMC_NORSRAM_TypeDef *Device, FMC_NORSRAM_EXTENDED_TypeDef *ExDevice, uint32_t Bank); @@ -870,19 +877,19 @@ HAL_StatusTypeDef FMC_NORSRAM_WriteOperation_Disable(FMC_NORSRAM_TypeDef *Devic * @} */ #endif /* FMC_BANK1 */ - #if defined(FMC_BANK3) + /** @defgroup FMC_LL_NAND NAND * @{ */ /** @defgroup FMC_LL_NAND_Private_Functions_Group1 NAND Initialization/de-initialization functions * @{ */ -HAL_StatusTypeDef FMC_NAND_Init(FMC_NAND_TypeDef *Device, FMC_NAND_InitTypeDef *Init); +HAL_StatusTypeDef FMC_NAND_Init(FMC_NAND_TypeDef *Device, const FMC_NAND_InitTypeDef *Init); HAL_StatusTypeDef FMC_NAND_CommonSpace_Timing_Init(FMC_NAND_TypeDef *Device, - FMC_NAND_PCC_TimingTypeDef *Timing, uint32_t Bank); + const FMC_NAND_PCC_TimingTypeDef *Timing, uint32_t Bank); HAL_StatusTypeDef FMC_NAND_AttributeSpace_Timing_Init(FMC_NAND_TypeDef *Device, - FMC_NAND_PCC_TimingTypeDef *Timing, uint32_t Bank); + const FMC_NAND_PCC_TimingTypeDef *Timing, uint32_t Bank); HAL_StatusTypeDef FMC_NAND_DeInit(FMC_NAND_TypeDef *Device, uint32_t Bank); /** * @} @@ -893,7 +900,7 @@ HAL_StatusTypeDef FMC_NAND_DeInit(FMC_NAND_TypeDef *Device, uint32_t Bank); */ HAL_StatusTypeDef FMC_NAND_ECC_Enable(FMC_NAND_TypeDef *Device, uint32_t Bank); HAL_StatusTypeDef FMC_NAND_ECC_Disable(FMC_NAND_TypeDef *Device, uint32_t Bank); -HAL_StatusTypeDef FMC_NAND_GetECC(FMC_NAND_TypeDef *Device, uint32_t *ECCval, uint32_t Bank, +HAL_StatusTypeDef FMC_NAND_GetECC(const FMC_NAND_TypeDef *Device, uint32_t *ECCval, uint32_t Bank, uint32_t Timeout); /** * @} @@ -902,21 +909,21 @@ HAL_StatusTypeDef FMC_NAND_GetECC(FMC_NAND_TypeDef *Device, uint32_t *ECCval, u * @} */ #endif /* FMC_BANK3 */ - #if defined(FMC_BANK4) + /** @defgroup FMC_LL_PCCARD PCCARD * @{ */ /** @defgroup FMC_LL_PCCARD_Private_Functions_Group1 PCCARD Initialization/de-initialization functions * @{ */ -HAL_StatusTypeDef FMC_PCCARD_Init(FMC_PCCARD_TypeDef *Device, FMC_PCCARD_InitTypeDef *Init); +HAL_StatusTypeDef FMC_PCCARD_Init(FMC_PCCARD_TypeDef *Device, const FMC_PCCARD_InitTypeDef *Init); HAL_StatusTypeDef FMC_PCCARD_CommonSpace_Timing_Init(FMC_PCCARD_TypeDef *Device, - FMC_NAND_PCC_TimingTypeDef *Timing); + const FMC_NAND_PCC_TimingTypeDef *Timing); HAL_StatusTypeDef FMC_PCCARD_AttributeSpace_Timing_Init(FMC_PCCARD_TypeDef *Device, - FMC_NAND_PCC_TimingTypeDef *Timing); + const FMC_NAND_PCC_TimingTypeDef *Timing); HAL_StatusTypeDef FMC_PCCARD_IOSpace_Timing_Init(FMC_PCCARD_TypeDef *Device, - FMC_NAND_PCC_TimingTypeDef *Timing); + const FMC_NAND_PCC_TimingTypeDef *Timing); HAL_StatusTypeDef FMC_PCCARD_DeInit(FMC_PCCARD_TypeDef *Device); /** * @} @@ -926,7 +933,6 @@ HAL_StatusTypeDef FMC_PCCARD_DeInit(FMC_PCCARD_TypeDef *Device); */ #endif /* FMC_BANK4 */ - /** * @} */ diff --git a/system/Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_ll_gpio.h b/system/Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_ll_gpio.h index 3de597099b..2499e85124 100644 --- a/system/Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_ll_gpio.h +++ b/system/Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_ll_gpio.h @@ -936,7 +936,7 @@ __STATIC_INLINE void LL_GPIO_ResetOutputPin(GPIO_TypeDef *GPIOx, uint32_t PinMas __STATIC_INLINE void LL_GPIO_TogglePin(GPIO_TypeDef *GPIOx, uint32_t PinMask) { uint32_t odr = READ_REG(GPIOx->ODR); - WRITE_REG(GPIOx->BSRR, ((odr & PinMask) << 16u) | (~odr & PinMask)); + WRITE_REG(GPIOx->BSRR, ((odr & PinMask) << 16U) | (~odr & PinMask)); } /** diff --git a/system/Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_ll_hrtim.h b/system/Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_ll_hrtim.h index 218f8e41b3..6ce134ae86 100644 --- a/system/Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_ll_hrtim.h +++ b/system/Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_ll_hrtim.h @@ -922,16 +922,25 @@ static const uint8_t REG_SHIFT_TAB_FLTxE[] = /** @defgroup HRTIM_LL_EC_DT_PRESCALER DEADTIME PRESCALER * @{ - * @brief Constants defining division ratio between the timer clock frequency (fHRTIM) and the deadtime generator clock (fDTG). - */ -#define LL_HRTIM_DT_PRESCALER_MUL8 0x00000000U /*!< fDTG = fHRTIM * 8 */ -#define LL_HRTIM_DT_PRESCALER_MUL4 (HRTIM_DTR_DTPRSC_0) /*!< fDTG = fHRTIM * 4 */ -#define LL_HRTIM_DT_PRESCALER_MUL2 (HRTIM_DTR_DTPRSC_1) /*!< fDTG = fHRTIM * 2 */ -#define LL_HRTIM_DT_PRESCALER_DIV1 (HRTIM_DTR_DTPRSC_1 | HRTIM_DTR_DTPRSC_0) /*!< fDTG = fHRTIM */ -#define LL_HRTIM_DT_PRESCALER_DIV2 (HRTIM_DTR_DTPRSC_2) /*!< fDTG = fHRTIM / 2 */ -#define LL_HRTIM_DT_PRESCALER_DIV4 (HRTIM_DTR_DTPRSC_2 | HRTIM_DTR_DTPRSC_0) /*!< fDTG = fHRTIM / 4 */ -#define LL_HRTIM_DT_PRESCALER_DIV8 (HRTIM_DTR_DTPRSC_2 | HRTIM_DTR_DTPRSC_1) /*!< fDTG = fHRTIM / 8 */ -#define LL_HRTIM_DT_PRESCALER_DIV16 (HRTIM_DTR_DTPRSC_2 | HRTIM_DTR_DTPRSC_1 | HRTIM_DTR_DTPRSC_0) /*!< fDTG = fHRTIM / 16 */ + * @brief Constants defining the prescaler value for the deadtime generator time step (tDTG) relative to the + * HR-Timer clock period (tHRTIM). + * @note A customer reported that the HRTIM deadtime prescaler defines in + * stm32f3xx_ll_hrtim.h were swapped between the multiplication (MUL) and + * division (DIV) settings (for example, MUL8 and DIV8 values were reversed). + * The legacy naming is intentionally kept for backward compatibility, even + * though it does not strictly match the reference manual. Renaming these + * constants would introduce a breaking API change, which may lead to + * incorrect deadtime programming and potential safety issues due to deadtime + * violations in existing applications. + */ +#define LL_HRTIM_DT_PRESCALER_MUL8 0x00000000U /*!< tDTG = tHRTIM / 8 */ +#define LL_HRTIM_DT_PRESCALER_MUL4 (HRTIM_DTR_DTPRSC_0) /*!< tDTG = tHRTIM / 4 */ +#define LL_HRTIM_DT_PRESCALER_MUL2 (HRTIM_DTR_DTPRSC_1) /*!< tDTG = tHRTIM / 2 */ +#define LL_HRTIM_DT_PRESCALER_DIV1 (HRTIM_DTR_DTPRSC_1 | HRTIM_DTR_DTPRSC_0) /*!< tDTG = tHRTIM */ +#define LL_HRTIM_DT_PRESCALER_DIV2 (HRTIM_DTR_DTPRSC_2) /*!< tDTG = tHRTIM * 2 */ +#define LL_HRTIM_DT_PRESCALER_DIV4 (HRTIM_DTR_DTPRSC_2 | HRTIM_DTR_DTPRSC_0) /*!< tDTG = tHRTIM * 4 */ +#define LL_HRTIM_DT_PRESCALER_DIV8 (HRTIM_DTR_DTPRSC_2 | HRTIM_DTR_DTPRSC_1) /*!< tDTG = tHRTIM * 8 */ +#define LL_HRTIM_DT_PRESCALER_DIV16 (HRTIM_DTR_DTPRSC_2 | HRTIM_DTR_DTPRSC_1 | HRTIM_DTR_DTPRSC_0) /*!< tDTG = tHRTIM * 16 */ /** * @} */ @@ -2001,7 +2010,7 @@ __STATIC_INLINE void LL_HRTIM_ConfigADCTrig(HRTIM_TypeDef *HRTIMx, uint32_t ADCT { uint32_t shift = ((3U * ADCTrig) & 0x1FU); __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sCommonRegs.ADC1R) + - REG_OFFSET_TAB_ADCxR[ADCTrig])); + REG_OFFSET_TAB_ADCxR[ADCTrig])); MODIFY_REG(HRTIMx->sCommonRegs.CR1, (HRTIM_CR1_ADC1USRC << shift), (Update << shift)); WRITE_REG(*pReg, Src); } @@ -2273,10 +2282,10 @@ __STATIC_INLINE uint32_t LL_HRTIM_GetADCTrigUpdate(const HRTIM_TypeDef *HRTIMx, * * @retval None */ -__STATIC_INLINE void LL_HRTIM_SetADCTrigSrc(HRTIM_TypeDef *HRTIMx, uint32_t ADCTrig, uint32_t Src) +__STATIC_INLINE void LL_HRTIM_SetADCTrigSrc(const HRTIM_TypeDef *HRTIMx, uint32_t ADCTrig, uint32_t Src) { __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sCommonRegs.ADC1R) + - REG_OFFSET_TAB_ADCxR[ADCTrig])); + REG_OFFSET_TAB_ADCxR[ADCTrig])); WRITE_REG(*pReg, Src); } @@ -2489,11 +2498,11 @@ __STATIC_INLINE void LL_HRTIM_SetADCTrigSrc(HRTIM_TypeDef *HRTIMx, uint32_t ADCT * @arg @ref LL_HRTIM_ADCTRIG_SRC24_TIMECMP3 * @arg @ref LL_HRTIM_ADCTRIG_SRC24_TIMECMP4 * @arg @ref LL_HRTIM_ADCTRIG_SRC24_TIMERST - */ + */ __STATIC_INLINE uint32_t LL_HRTIM_GetADCTrigSrc(const HRTIM_TypeDef *HRTIMx, uint32_t ADCTrig) { const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sCommonRegs.ADC1R) + - REG_OFFSET_TAB_ADCxR[ADCTrig])); + REG_OFFSET_TAB_ADCxR[ADCTrig])); return (*pReg); } @@ -2632,7 +2641,7 @@ __STATIC_INLINE uint32_t LL_HRTIM_TIM_IsCounterEnabled(const HRTIM_TypeDef *HRTI * @arg @ref LL_HRTIM_PRESCALERRATIO_DIV4 * @retval None */ -__STATIC_INLINE void LL_HRTIM_TIM_SetPrescaler(HRTIM_TypeDef *HRTIMx, uint32_t Timer, uint32_t Prescaler) +__STATIC_INLINE void LL_HRTIM_TIM_SetPrescaler(const HRTIM_TypeDef *HRTIMx, uint32_t Timer, uint32_t Prescaler) { uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MCR) + REG_OFFSET_TAB_TIMER[iTimer])); @@ -2688,7 +2697,7 @@ __STATIC_INLINE uint32_t LL_HRTIM_TIM_GetPrescaler(const HRTIM_TypeDef *HRTIMx, * @arg @ref LL_HRTIM_MODE_RETRIGGERABLE * @retval None */ -__STATIC_INLINE void LL_HRTIM_TIM_SetCounterMode(HRTIM_TypeDef *HRTIMx, uint32_t Timer, uint32_t Mode) +__STATIC_INLINE void LL_HRTIM_TIM_SetCounterMode(const HRTIM_TypeDef *HRTIMx, uint32_t Timer, uint32_t Mode) { uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MCR) + REG_OFFSET_TAB_TIMER[iTimer])); @@ -2738,7 +2747,7 @@ __STATIC_INLINE uint32_t LL_HRTIM_TIM_GetCounterMode(const HRTIM_TypeDef *HRTIMx * @arg @ref LL_HRTIM_TIMER_E * @retval None */ -__STATIC_INLINE void LL_HRTIM_TIM_EnableHalfMode(HRTIM_TypeDef *HRTIMx, uint32_t Timer) +__STATIC_INLINE void LL_HRTIM_TIM_EnableHalfMode(const HRTIM_TypeDef *HRTIMx, uint32_t Timer) { uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MCR) + REG_OFFSET_TAB_TIMER[iTimer])); @@ -2759,7 +2768,7 @@ __STATIC_INLINE void LL_HRTIM_TIM_EnableHalfMode(HRTIM_TypeDef *HRTIMx, uint32_t * @arg @ref LL_HRTIM_TIMER_E * @retval None */ -__STATIC_INLINE void LL_HRTIM_TIM_DisableHalfMode(HRTIM_TypeDef *HRTIMx, uint32_t Timer) +__STATIC_INLINE void LL_HRTIM_TIM_DisableHalfMode(const HRTIM_TypeDef *HRTIMx, uint32_t Timer) { uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MCR) + REG_OFFSET_TAB_TIMER[iTimer])); @@ -2801,7 +2810,7 @@ __STATIC_INLINE uint32_t LL_HRTIM_TIM_IsEnabledHalfMode(const HRTIM_TypeDef *HRT * @arg @ref LL_HRTIM_TIMER_E * @retval None */ -__STATIC_INLINE void LL_HRTIM_TIM_EnableStartOnSync(HRTIM_TypeDef *HRTIMx, uint32_t Timer) +__STATIC_INLINE void LL_HRTIM_TIM_EnableStartOnSync(const HRTIM_TypeDef *HRTIMx, uint32_t Timer) { uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MCR) + REG_OFFSET_TAB_TIMER[iTimer])); @@ -2822,7 +2831,7 @@ __STATIC_INLINE void LL_HRTIM_TIM_EnableStartOnSync(HRTIM_TypeDef *HRTIMx, uint3 * @arg @ref LL_HRTIM_TIMER_E * @retval None */ -__STATIC_INLINE void LL_HRTIM_TIM_DisableStartOnSync(HRTIM_TypeDef *HRTIMx, uint32_t Timer) +__STATIC_INLINE void LL_HRTIM_TIM_DisableStartOnSync(const HRTIM_TypeDef *HRTIMx, uint32_t Timer) { uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MCR) + REG_OFFSET_TAB_TIMER[iTimer])); @@ -2865,7 +2874,7 @@ __STATIC_INLINE uint32_t LL_HRTIM_TIM_IsEnabledStartOnSync(const HRTIM_TypeDef * * @arg @ref LL_HRTIM_TIMER_E * @retval None */ -__STATIC_INLINE void LL_HRTIM_TIM_EnableResetOnSync(HRTIM_TypeDef *HRTIMx, uint32_t Timer) +__STATIC_INLINE void LL_HRTIM_TIM_EnableResetOnSync(const HRTIM_TypeDef *HRTIMx, uint32_t Timer) { uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MCR) + REG_OFFSET_TAB_TIMER[iTimer])); @@ -2886,7 +2895,7 @@ __STATIC_INLINE void LL_HRTIM_TIM_EnableResetOnSync(HRTIM_TypeDef *HRTIMx, uint3 * @arg @ref LL_HRTIM_TIMER_E * @retval None */ -__STATIC_INLINE void LL_HRTIM_TIM_DisableResetOnSync(HRTIM_TypeDef *HRTIMx, uint32_t Timer) +__STATIC_INLINE void LL_HRTIM_TIM_DisableResetOnSync(const HRTIM_TypeDef *HRTIMx, uint32_t Timer) { uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MCR) + REG_OFFSET_TAB_TIMER[iTimer])); @@ -2934,7 +2943,7 @@ __STATIC_INLINE uint32_t LL_HRTIM_TIM_IsEnabledResetOnSync(const HRTIM_TypeDef * * @arg @ref LL_HRTIM_DACTRIG_DACTRIGOUT_3 * @retval None */ -__STATIC_INLINE void LL_HRTIM_TIM_SetDACTrig(HRTIM_TypeDef *HRTIMx, uint32_t Timer, uint32_t DACTrig) +__STATIC_INLINE void LL_HRTIM_TIM_SetDACTrig(const HRTIM_TypeDef *HRTIMx, uint32_t Timer, uint32_t DACTrig) { uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MCR) + REG_OFFSET_TAB_TIMER[iTimer])); @@ -2983,7 +2992,7 @@ __STATIC_INLINE uint32_t LL_HRTIM_TIM_GetDACTrig(const HRTIM_TypeDef *HRTIMx, ui * @arg @ref LL_HRTIM_TIMER_E * @retval None */ -__STATIC_INLINE void LL_HRTIM_TIM_EnablePreload(HRTIM_TypeDef *HRTIMx, uint32_t Timer) +__STATIC_INLINE void LL_HRTIM_TIM_EnablePreload(const HRTIM_TypeDef *HRTIMx, uint32_t Timer) { uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MCR) + REG_OFFSET_TAB_TIMER[iTimer])); @@ -3004,7 +3013,7 @@ __STATIC_INLINE void LL_HRTIM_TIM_EnablePreload(HRTIM_TypeDef *HRTIMx, uint32_t * @arg @ref LL_HRTIM_TIMER_E * @retval None */ -__STATIC_INLINE void LL_HRTIM_TIM_DisablePreload(HRTIM_TypeDef *HRTIMx, uint32_t Timer) +__STATIC_INLINE void LL_HRTIM_TIM_DisablePreload(const HRTIM_TypeDef *HRTIMx, uint32_t Timer) { uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MCR) + REG_OFFSET_TAB_TIMER[iTimer])); @@ -3069,7 +3078,7 @@ __STATIC_INLINE uint32_t LL_HRTIM_TIM_IsEnabledPreload(const HRTIM_TypeDef *HRTI * @arg @ref LL_HRTIM_UPDATETRIG_RESET * @retval None */ -__STATIC_INLINE void LL_HRTIM_TIM_SetUpdateTrig(HRTIM_TypeDef *HRTIMx, uint32_t Timer, uint32_t UpdateTrig) +__STATIC_INLINE void LL_HRTIM_TIM_SetUpdateTrig(const HRTIM_TypeDef *HRTIMx, uint32_t Timer, uint32_t UpdateTrig) { uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MCR) + REG_OFFSET_TAB_TIMER[iTimer])); @@ -3148,7 +3157,7 @@ __STATIC_INLINE uint32_t LL_HRTIM_TIM_GetUpdateTrig(const HRTIM_TypeDef *HRTIMx, * @arg @ref LL_HRTIM_UPDATEGATING_UPDEN3_UPDATE * @retval None */ -__STATIC_INLINE void LL_HRTIM_TIM_SetUpdateGating(HRTIM_TypeDef *HRTIMx, uint32_t Timer, uint32_t UpdateGating) +__STATIC_INLINE void LL_HRTIM_TIM_SetUpdateGating(const HRTIM_TypeDef *HRTIMx, uint32_t Timer, uint32_t UpdateGating) { uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MCR) + REG_OFFSET_TAB_TIMER[iTimer])); @@ -3204,11 +3213,11 @@ __STATIC_INLINE uint32_t LL_HRTIM_TIM_GetUpdateGating(const HRTIM_TypeDef *HRTIM * @arg @ref LL_HRTIM_TIMER_E * @retval None */ -__STATIC_INLINE void LL_HRTIM_TIM_EnablePushPullMode(HRTIM_TypeDef *HRTIMx, uint32_t Timer) +__STATIC_INLINE void LL_HRTIM_TIM_EnablePushPullMode(const HRTIM_TypeDef *HRTIMx, uint32_t Timer) { uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos); __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].TIMxCR) + - REG_OFFSET_TAB_TIMER[iTimer])); + REG_OFFSET_TAB_TIMER[iTimer])); SET_BIT(*pReg, HRTIM_TIMCR_PSHPLL); } @@ -3224,11 +3233,11 @@ __STATIC_INLINE void LL_HRTIM_TIM_EnablePushPullMode(HRTIM_TypeDef *HRTIMx, uint * @arg @ref LL_HRTIM_TIMER_E * @retval None */ -__STATIC_INLINE void LL_HRTIM_TIM_DisablePushPullMode(HRTIM_TypeDef *HRTIMx, uint32_t Timer) +__STATIC_INLINE void LL_HRTIM_TIM_DisablePushPullMode(const HRTIM_TypeDef *HRTIMx, uint32_t Timer) { uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos); __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].TIMxCR) + - REG_OFFSET_TAB_TIMER[iTimer])); + REG_OFFSET_TAB_TIMER[iTimer])); CLEAR_BIT(*pReg, HRTIM_TIMCR_PSHPLL); } @@ -3248,7 +3257,7 @@ __STATIC_INLINE uint32_t LL_HRTIM_TIM_IsEnabledPushPullMode(const HRTIM_TypeDef { uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos); const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].TIMxCR) + - REG_OFFSET_TAB_TIMER[iTimer])); + REG_OFFSET_TAB_TIMER[iTimer])); return ((READ_BIT(*pReg, HRTIM_TIMCR_PSHPLL) == (HRTIM_TIMCR_PSHPLL)) ? 1UL : 0UL); } @@ -3274,12 +3283,12 @@ __STATIC_INLINE uint32_t LL_HRTIM_TIM_IsEnabledPushPullMode(const HRTIM_TypeDef * @arg @ref LL_HRTIM_COMPAREMODE_DELAY_CMP3 * @retval None */ -__STATIC_INLINE void LL_HRTIM_TIM_SetCompareMode(HRTIM_TypeDef *HRTIMx, uint32_t Timer, uint32_t CompareUnit, +__STATIC_INLINE void LL_HRTIM_TIM_SetCompareMode(const HRTIM_TypeDef *HRTIMx, uint32_t Timer, uint32_t CompareUnit, uint32_t Mode) { uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos); __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].TIMxCR) + - REG_OFFSET_TAB_TIMER[iTimer])); + REG_OFFSET_TAB_TIMER[iTimer])); uint32_t shift = (((uint32_t)POSITION_VAL(CompareUnit) - (uint32_t)POSITION_VAL(LL_HRTIM_COMPAREUNIT_2)) & 0x1FU); MODIFY_REG(* pReg, (HRTIM_TIMCR_DELCMP2 << shift), (Mode << shift)); } @@ -3308,7 +3317,7 @@ __STATIC_INLINE uint32_t LL_HRTIM_TIM_GetCompareMode(const HRTIM_TypeDef *HRTIMx { uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos); const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].TIMxCR) + - REG_OFFSET_TAB_TIMER[iTimer])); + REG_OFFSET_TAB_TIMER[iTimer])); uint32_t shift = (((uint32_t)POSITION_VAL(CompareUnit) - (uint32_t)POSITION_VAL(LL_HRTIM_COMPAREUNIT_2)) & 0x1FU); return (READ_BIT(*pReg, (HRTIM_TIMCR_DELCMP2 << shift)) >> shift); } @@ -3334,11 +3343,11 @@ __STATIC_INLINE uint32_t LL_HRTIM_TIM_GetCompareMode(const HRTIM_TypeDef *HRTIMx * @param Counter Value between 0 and 0xFFFF * @retval None */ -__STATIC_INLINE void LL_HRTIM_TIM_SetCounter(HRTIM_TypeDef *HRTIMx, uint32_t Timer, uint32_t Counter) +__STATIC_INLINE void LL_HRTIM_TIM_SetCounter(const HRTIM_TypeDef *HRTIMx, uint32_t Timer, uint32_t Counter) { uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MCNTR) + - REG_OFFSET_TAB_TIMER[iTimer])); + REG_OFFSET_TAB_TIMER[iTimer])); MODIFY_REG(* pReg, HRTIM_MCNTR_MCNTR, Counter); } @@ -3360,7 +3369,7 @@ __STATIC_INLINE uint32_t LL_HRTIM_TIM_GetCounter(const HRTIM_TypeDef *HRTIMx, ui { uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MCNTR) + - REG_OFFSET_TAB_TIMER[iTimer])); + REG_OFFSET_TAB_TIMER[iTimer])); return (READ_BIT(*pReg, HRTIM_MCNTR_MCNTR)); } @@ -3379,11 +3388,11 @@ __STATIC_INLINE uint32_t LL_HRTIM_TIM_GetCounter(const HRTIM_TypeDef *HRTIMx, ui * @param Period Value between 0 and 0xFFFF * @retval None */ -__STATIC_INLINE void LL_HRTIM_TIM_SetPeriod(HRTIM_TypeDef *HRTIMx, uint32_t Timer, uint32_t Period) +__STATIC_INLINE void LL_HRTIM_TIM_SetPeriod(const HRTIM_TypeDef *HRTIMx, uint32_t Timer, uint32_t Period) { uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MPER) + - REG_OFFSET_TAB_TIMER[iTimer])); + REG_OFFSET_TAB_TIMER[iTimer])); MODIFY_REG(* pReg, HRTIM_MPER_MPER, Period); } @@ -3405,7 +3414,7 @@ __STATIC_INLINE uint32_t LL_HRTIM_TIM_GetPeriod(const HRTIM_TypeDef *HRTIMx, uin { uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MPER) + - REG_OFFSET_TAB_TIMER[iTimer])); + REG_OFFSET_TAB_TIMER[iTimer])); return (READ_BIT(*pReg, HRTIM_MPER_MPER)); } @@ -3424,11 +3433,11 @@ __STATIC_INLINE uint32_t LL_HRTIM_TIM_GetPeriod(const HRTIM_TypeDef *HRTIMx, uin * @param Repetition Value between 0 and 0xFF * @retval None */ -__STATIC_INLINE void LL_HRTIM_TIM_SetRepetition(HRTIM_TypeDef *HRTIMx, uint32_t Timer, uint32_t Repetition) +__STATIC_INLINE void LL_HRTIM_TIM_SetRepetition(const HRTIM_TypeDef *HRTIMx, uint32_t Timer, uint32_t Repetition) { uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MREP) + - REG_OFFSET_TAB_TIMER[iTimer])); + REG_OFFSET_TAB_TIMER[iTimer])); MODIFY_REG(* pReg, HRTIM_MREP_MREP, Repetition); } @@ -3450,7 +3459,7 @@ __STATIC_INLINE uint32_t LL_HRTIM_TIM_GetRepetition(const HRTIM_TypeDef *HRTIMx, { uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MREP) + - REG_OFFSET_TAB_TIMER[iTimer])); + REG_OFFSET_TAB_TIMER[iTimer])); return (READ_BIT(*pReg, HRTIM_MREP_MREP)); } @@ -3471,11 +3480,11 @@ __STATIC_INLINE uint32_t LL_HRTIM_TIM_GetRepetition(const HRTIM_TypeDef *HRTIMx, * 0x30 if CKPSC[2:0] = 1, 0x18 if CKPSC[2:0] = 2,... * @retval None */ -__STATIC_INLINE void LL_HRTIM_TIM_SetCompare1(HRTIM_TypeDef *HRTIMx, uint32_t Timer, uint32_t CompareValue) +__STATIC_INLINE void LL_HRTIM_TIM_SetCompare1(const HRTIM_TypeDef *HRTIMx, uint32_t Timer, uint32_t CompareValue) { uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MCMP1R) + - REG_OFFSET_TAB_TIMER[iTimer])); + REG_OFFSET_TAB_TIMER[iTimer])); MODIFY_REG(* pReg, HRTIM_MCMP1R_MCMP1R, CompareValue); } @@ -3499,7 +3508,7 @@ __STATIC_INLINE uint32_t LL_HRTIM_TIM_GetCompare1(const HRTIM_TypeDef *HRTIMx, u { uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MCMP1R) + - REG_OFFSET_TAB_TIMER[iTimer])); + REG_OFFSET_TAB_TIMER[iTimer])); return (READ_BIT(*pReg, HRTIM_MCMP1R_MCMP1R)); } @@ -3520,11 +3529,11 @@ __STATIC_INLINE uint32_t LL_HRTIM_TIM_GetCompare1(const HRTIM_TypeDef *HRTIMx, u * 0x30 if CKPSC[2:0] = 1, 0x18 if CKPSC[2:0] = 2,... * @retval None */ -__STATIC_INLINE void LL_HRTIM_TIM_SetCompare2(HRTIM_TypeDef *HRTIMx, uint32_t Timer, uint32_t CompareValue) +__STATIC_INLINE void LL_HRTIM_TIM_SetCompare2(const HRTIM_TypeDef *HRTIMx, uint32_t Timer, uint32_t CompareValue) { uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MCMP2R) + - REG_OFFSET_TAB_TIMER[iTimer])); + REG_OFFSET_TAB_TIMER[iTimer])); MODIFY_REG(* pReg, HRTIM_MCMP1R_MCMP2R, CompareValue); } @@ -3548,7 +3557,7 @@ __STATIC_INLINE uint32_t LL_HRTIM_TIM_GetCompare2(const HRTIM_TypeDef *HRTIMx, u { uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MCMP2R) + - REG_OFFSET_TAB_TIMER[iTimer])); + REG_OFFSET_TAB_TIMER[iTimer])); return (READ_BIT(*pReg, HRTIM_MCMP1R_MCMP2R)); } @@ -3569,11 +3578,11 @@ __STATIC_INLINE uint32_t LL_HRTIM_TIM_GetCompare2(const HRTIM_TypeDef *HRTIMx, u * 0x30 if CKPSC[2:0] = 1, 0x18 if CKPSC[2:0] = 2,... * @retval None */ -__STATIC_INLINE void LL_HRTIM_TIM_SetCompare3(HRTIM_TypeDef *HRTIMx, uint32_t Timer, uint32_t CompareValue) +__STATIC_INLINE void LL_HRTIM_TIM_SetCompare3(const HRTIM_TypeDef *HRTIMx, uint32_t Timer, uint32_t CompareValue) { uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MCMP3R) + - REG_OFFSET_TAB_TIMER[iTimer])); + REG_OFFSET_TAB_TIMER[iTimer])); MODIFY_REG(* pReg, HRTIM_MCMP1R_MCMP3R, CompareValue); } @@ -3597,7 +3606,7 @@ __STATIC_INLINE uint32_t LL_HRTIM_TIM_GetCompare3(const HRTIM_TypeDef *HRTIMx, u { uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MCMP3R) + - REG_OFFSET_TAB_TIMER[iTimer])); + REG_OFFSET_TAB_TIMER[iTimer])); return (READ_BIT(*pReg, HRTIM_MCMP1R_MCMP3R)); } @@ -3618,11 +3627,11 @@ __STATIC_INLINE uint32_t LL_HRTIM_TIM_GetCompare3(const HRTIM_TypeDef *HRTIMx, u * 0x30 if CKPSC[2:0] = 1, 0x18 if CKPSC[2:0] = 2,... * @retval None */ -__STATIC_INLINE void LL_HRTIM_TIM_SetCompare4(HRTIM_TypeDef *HRTIMx, uint32_t Timer, uint32_t CompareValue) +__STATIC_INLINE void LL_HRTIM_TIM_SetCompare4(const HRTIM_TypeDef *HRTIMx, uint32_t Timer, uint32_t CompareValue) { uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MCMP4R) + - REG_OFFSET_TAB_TIMER[iTimer])); + REG_OFFSET_TAB_TIMER[iTimer])); MODIFY_REG(* pReg, HRTIM_MCMP1R_MCMP4R, CompareValue); } @@ -3646,7 +3655,7 @@ __STATIC_INLINE uint32_t LL_HRTIM_TIM_GetCompare4(const HRTIM_TypeDef *HRTIMx, u { uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MCMP4R) + - REG_OFFSET_TAB_TIMER[iTimer])); + REG_OFFSET_TAB_TIMER[iTimer])); return (READ_BIT(*pReg, HRTIM_MCMP1R_MCMP4R)); } @@ -3729,11 +3738,11 @@ __STATIC_INLINE uint32_t LL_HRTIM_TIM_GetCompare4(const HRTIM_TypeDef *HRTIMx, u * @arg @ref LL_HRTIM_RESETTRIG_OTHER4_CMP4 * @retval None */ -__STATIC_INLINE void LL_HRTIM_TIM_SetResetTrig(HRTIM_TypeDef *HRTIMx, uint32_t Timer, uint32_t ResetTrig) +__STATIC_INLINE void LL_HRTIM_TIM_SetResetTrig(const HRTIM_TypeDef *HRTIMx, uint32_t Timer, uint32_t ResetTrig) { uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos); __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].RSTxR) + - REG_OFFSET_TAB_TIMER[iTimer])); + REG_OFFSET_TAB_TIMER[iTimer])); WRITE_REG(*pReg, ResetTrig); } @@ -3813,7 +3822,7 @@ __STATIC_INLINE uint32_t LL_HRTIM_TIM_GetResetTrig(const HRTIM_TypeDef *HRTIMx, { uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos); const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].RSTxR) + - REG_OFFSET_TAB_TIMER[iTimer])); + REG_OFFSET_TAB_TIMER[iTimer])); return (READ_REG(*pReg)); } @@ -3833,7 +3842,7 @@ __STATIC_INLINE uint32_t LL_HRTIM_TIM_GetCapture1(const HRTIM_TypeDef *HRTIMx, u { uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos); const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].CPT1xR) + - REG_OFFSET_TAB_TIMER[iTimer])); + REG_OFFSET_TAB_TIMER[iTimer])); return (READ_REG(*pReg)); } @@ -3853,7 +3862,7 @@ __STATIC_INLINE uint32_t LL_HRTIM_TIM_GetCapture2(const HRTIM_TypeDef *HRTIMx, u { uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos); const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].CPT2xR) + - REG_OFFSET_TAB_TIMER[iTimer])); + REG_OFFSET_TAB_TIMER[iTimer])); return (READ_REG(*pReg)); } @@ -3936,12 +3945,12 @@ __STATIC_INLINE uint32_t LL_HRTIM_TIM_GetCapture2(const HRTIM_TypeDef *HRTIMx, u * @arg @ref LL_HRTIM_CAPTURETRIG_TIME_CMP2 * @retval None */ -__STATIC_INLINE void LL_HRTIM_TIM_SetCaptureTrig(HRTIM_TypeDef *HRTIMx, uint32_t Timer, uint32_t CaptureUnit, +__STATIC_INLINE void LL_HRTIM_TIM_SetCaptureTrig(const HRTIM_TypeDef *HRTIMx, uint32_t Timer, uint32_t CaptureUnit, uint32_t CaptureTrig) { uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos); __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0U].CPT1xCR) + - REG_OFFSET_TAB_TIMER[iTimer] + (CaptureUnit * 4U))); + REG_OFFSET_TAB_TIMER[iTimer] + (CaptureUnit * 4U))); WRITE_REG(*pReg, CaptureTrig); } @@ -4027,7 +4036,7 @@ __STATIC_INLINE uint32_t LL_HRTIM_TIM_GetCaptureTrig(const HRTIM_TypeDef *HRTIMx { uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos); const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0U].CPT1xCR) + - REG_OFFSET_TAB_TIMER[iTimer] + (CaptureUnit * 4U))); + REG_OFFSET_TAB_TIMER[iTimer] + (CaptureUnit * 4U))); return (READ_REG(*pReg)); } @@ -4043,11 +4052,11 @@ __STATIC_INLINE uint32_t LL_HRTIM_TIM_GetCaptureTrig(const HRTIM_TypeDef *HRTIMx * @arg @ref LL_HRTIM_TIMER_E * @retval None */ -__STATIC_INLINE void LL_HRTIM_TIM_EnableDeadTime(HRTIM_TypeDef *HRTIMx, uint32_t Timer) +__STATIC_INLINE void LL_HRTIM_TIM_EnableDeadTime(const HRTIM_TypeDef *HRTIMx, uint32_t Timer) { uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos); __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].OUTxR) + - REG_OFFSET_TAB_TIMER[iTimer])); + REG_OFFSET_TAB_TIMER[iTimer])); SET_BIT(*pReg, HRTIM_OUTR_DTEN); } @@ -4063,11 +4072,11 @@ __STATIC_INLINE void LL_HRTIM_TIM_EnableDeadTime(HRTIM_TypeDef *HRTIMx, uint32_t * @arg @ref LL_HRTIM_TIMER_E * @retval None */ -__STATIC_INLINE void LL_HRTIM_TIM_DisableDeadTime(HRTIM_TypeDef *HRTIMx, uint32_t Timer) +__STATIC_INLINE void LL_HRTIM_TIM_DisableDeadTime(const HRTIM_TypeDef *HRTIMx, uint32_t Timer) { uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos); __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].OUTxR) + - REG_OFFSET_TAB_TIMER[iTimer])); + REG_OFFSET_TAB_TIMER[iTimer])); CLEAR_BIT(*pReg, HRTIM_OUTR_DTEN); } @@ -4087,7 +4096,7 @@ __STATIC_INLINE uint32_t LL_HRTIM_TIM_IsEnabledDeadTime(const HRTIM_TypeDef *HRT { uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos); const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].OUTxR) + - REG_OFFSET_TAB_TIMER[iTimer])); + REG_OFFSET_TAB_TIMER[iTimer])); return ((READ_BIT(*pReg, HRTIM_OUTR_DTEN) == (HRTIM_OUTR_DTEN)) ? 1UL : 0UL); } @@ -4128,11 +4137,11 @@ __STATIC_INLINE uint32_t LL_HRTIM_TIM_IsEnabledDeadTime(const HRTIM_TypeDef *HRT * @arg @ref LL_HRTIM_DLYPRT_BALANCED_EEV9 * @retval None */ -__STATIC_INLINE void LL_HRTIM_TIM_SetDLYPRTMode(HRTIM_TypeDef *HRTIMx, uint32_t Timer, uint32_t DLYPRTMode) +__STATIC_INLINE void LL_HRTIM_TIM_SetDLYPRTMode(const HRTIM_TypeDef *HRTIMx, uint32_t Timer, uint32_t DLYPRTMode) { uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos); __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].OUTxR) + - REG_OFFSET_TAB_TIMER[iTimer])); + REG_OFFSET_TAB_TIMER[iTimer])); MODIFY_REG(*pReg, HRTIM_OUTR_DLYPRT, DLYPRTMode); } @@ -4173,7 +4182,7 @@ __STATIC_INLINE uint32_t LL_HRTIM_TIM_GetDLYPRTMode(const HRTIM_TypeDef *HRTIMx, { uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos); const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].OUTxR) + - REG_OFFSET_TAB_TIMER[iTimer])); + REG_OFFSET_TAB_TIMER[iTimer])); return (READ_BIT(*pReg, HRTIM_OUTR_DLYPRT)); } @@ -4190,11 +4199,11 @@ __STATIC_INLINE uint32_t LL_HRTIM_TIM_GetDLYPRTMode(const HRTIM_TypeDef *HRTIMx, * @arg @ref LL_HRTIM_TIMER_E * @retval None */ -__STATIC_INLINE void LL_HRTIM_TIM_EnableDLYPRT(HRTIM_TypeDef *HRTIMx, uint32_t Timer) +__STATIC_INLINE void LL_HRTIM_TIM_EnableDLYPRT(const HRTIM_TypeDef *HRTIMx, uint32_t Timer) { uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos); __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].OUTxR) + - REG_OFFSET_TAB_TIMER[iTimer])); + REG_OFFSET_TAB_TIMER[iTimer])); SET_BIT(*pReg, HRTIM_OUTR_DLYPRTEN); } @@ -4211,11 +4220,11 @@ __STATIC_INLINE void LL_HRTIM_TIM_EnableDLYPRT(HRTIM_TypeDef *HRTIMx, uint32_t T * @arg @ref LL_HRTIM_TIMER_E * @retval None */ -__STATIC_INLINE void LL_HRTIM_TIM_DisableDLYPRT(HRTIM_TypeDef *HRTIMx, uint32_t Timer) +__STATIC_INLINE void LL_HRTIM_TIM_DisableDLYPRT(const HRTIM_TypeDef *HRTIMx, uint32_t Timer) { uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos); __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].OUTxR) + - REG_OFFSET_TAB_TIMER[iTimer])); + REG_OFFSET_TAB_TIMER[iTimer])); CLEAR_BIT(*pReg, HRTIM_OUTR_DLYPRTEN); } @@ -4235,7 +4244,7 @@ __STATIC_INLINE uint32_t LL_HRTIM_TIM_IsEnabledDLYPRT(const HRTIM_TypeDef *HRTIM { uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos); const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].OUTxR) + - REG_OFFSET_TAB_TIMER[iTimer])); + REG_OFFSET_TAB_TIMER[iTimer])); return ((READ_BIT(*pReg, HRTIM_OUTR_DLYPRTEN) == (HRTIM_OUTR_DLYPRTEN)) ? 1UL : 0UL); } @@ -4261,11 +4270,11 @@ __STATIC_INLINE uint32_t LL_HRTIM_TIM_IsEnabledDLYPRT(const HRTIM_TypeDef *HRTIM * @arg @ref LL_HRTIM_FAULT_5 * @retval None */ -__STATIC_INLINE void LL_HRTIM_TIM_EnableFault(HRTIM_TypeDef *HRTIMx, uint32_t Timer, uint32_t Faults) +__STATIC_INLINE void LL_HRTIM_TIM_EnableFault(const HRTIM_TypeDef *HRTIMx, uint32_t Timer, uint32_t Faults) { uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos); __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].FLTxR) + - REG_OFFSET_TAB_TIMER[iTimer])); + REG_OFFSET_TAB_TIMER[iTimer])); SET_BIT(*pReg, Faults); } @@ -4291,11 +4300,11 @@ __STATIC_INLINE void LL_HRTIM_TIM_EnableFault(HRTIM_TypeDef *HRTIMx, uint32_t Ti * @arg @ref LL_HRTIM_FAULT_5 * @retval None */ -__STATIC_INLINE void LL_HRTIM_TIM_DisableFault(HRTIM_TypeDef *HRTIMx, uint32_t Timer, uint32_t Faults) +__STATIC_INLINE void LL_HRTIM_TIM_DisableFault(const HRTIM_TypeDef *HRTIMx, uint32_t Timer, uint32_t Faults) { uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos); __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].FLTxR) + - REG_OFFSET_TAB_TIMER[iTimer])); + REG_OFFSET_TAB_TIMER[iTimer])); CLEAR_BIT(*pReg, Faults); } @@ -4325,7 +4334,7 @@ __STATIC_INLINE uint32_t LL_HRTIM_TIM_IsEnabledFault(const HRTIM_TypeDef *HRTIMx { uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos); const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].FLTxR) + - REG_OFFSET_TAB_TIMER[iTimer])); + REG_OFFSET_TAB_TIMER[iTimer])); return ((READ_BIT(*pReg, Fault) == (Fault)) ? 1UL : 0UL); } @@ -4343,11 +4352,11 @@ __STATIC_INLINE uint32_t LL_HRTIM_TIM_IsEnabledFault(const HRTIM_TypeDef *HRTIMx * @arg @ref LL_HRTIM_TIMER_E * @retval None */ -__STATIC_INLINE void LL_HRTIM_TIM_LockFault(HRTIM_TypeDef *HRTIMx, uint32_t Timer) +__STATIC_INLINE void LL_HRTIM_TIM_LockFault(const HRTIM_TypeDef *HRTIMx, uint32_t Timer) { uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos); __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].FLTxR) + - REG_OFFSET_TAB_TIMER[iTimer])); + REG_OFFSET_TAB_TIMER[iTimer])); SET_BIT(*pReg, HRTIM_FLTR_FLTLCK); } @@ -4485,7 +4494,7 @@ __STATIC_INLINE uint32_t LL_HRTIM_TIM_GetBurstModeOption(const HRTIM_TypeDef *HR * @arg @ref LL_HRTIM_BURSTDMA_TIMFLTR * @retval None */ -__STATIC_INLINE void LL_HRTIM_TIM_ConfigBurstDMA(HRTIM_TypeDef *HRTIMx, uint32_t Timer, uint32_t Registers) +__STATIC_INLINE void LL_HRTIM_TIM_ConfigBurstDMA(const HRTIM_TypeDef *HRTIMx, uint32_t Timer, uint32_t Registers) { uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); @@ -4512,7 +4521,7 @@ __STATIC_INLINE uint32_t LL_HRTIM_TIM_GetCurrentPushPullStatus(const HRTIM_TypeD { uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MISR) + - REG_OFFSET_TAB_TIMER[iTimer])); + REG_OFFSET_TAB_TIMER[iTimer])); return (READ_BIT(*pReg, HRTIM_TIMISR_CPPSTAT)); } @@ -4534,7 +4543,7 @@ __STATIC_INLINE uint32_t LL_HRTIM_TIM_GetIdlePushPullStatus(const HRTIM_TypeDef { uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MISR) + - REG_OFFSET_TAB_TIMER[iTimer])); + REG_OFFSET_TAB_TIMER[iTimer])); return (READ_BIT(*pReg, HRTIM_TIMISR_IPPSTAT)); } @@ -4589,12 +4598,13 @@ __STATIC_INLINE uint32_t LL_HRTIM_TIM_GetIdlePushPullStatus(const HRTIM_TypeDef * @retval None */ -__STATIC_INLINE void LL_HRTIM_TIM_SetEventFilter(HRTIM_TypeDef *HRTIMx, uint32_t Timer, uint32_t Event, uint32_t Filter) +__STATIC_INLINE void LL_HRTIM_TIM_SetEventFilter(const HRTIM_TypeDef *HRTIMx, uint32_t Timer, uint32_t Event, + uint32_t Filter) { uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - POSITION_VAL(LL_HRTIM_TIMER_A)); uint32_t iEvent = (uint8_t)(POSITION_VAL(Event) - POSITION_VAL(LL_HRTIM_EVENT_1)); __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].EEFxR1) + - REG_OFFSET_TAB_TIMER[iTimer] + REG_OFFSET_TAB_EECR[iEvent])); + REG_OFFSET_TAB_TIMER[iTimer] + REG_OFFSET_TAB_EECR[iEvent])); MODIFY_REG(*pReg, (HRTIM_EEFR1_EE1FLTR << REG_SHIFT_TAB_EExSRC[iEvent]), (Filter << REG_SHIFT_TAB_EExSRC[iEvent])); } @@ -4651,7 +4661,7 @@ __STATIC_INLINE uint32_t LL_HRTIM_TIM_GetEventFilter(const HRTIM_TypeDef *HRTIMx uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - POSITION_VAL(LL_HRTIM_TIMER_A)); uint32_t iEvent = (uint8_t)(POSITION_VAL(Event) - POSITION_VAL(LL_HRTIM_EVENT_1)); const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].EEFxR1) + - REG_OFFSET_TAB_TIMER[iTimer] + REG_OFFSET_TAB_EECR[iEvent])); + REG_OFFSET_TAB_TIMER[iTimer] + REG_OFFSET_TAB_EECR[iEvent])); return (READ_BIT(*pReg, (uint32_t)(HRTIM_EEFR1_EE1FLTR) << (REG_SHIFT_TAB_EExSRC[iEvent])) >> (REG_SHIFT_TAB_EExSRC[iEvent])); } @@ -4691,13 +4701,13 @@ __STATIC_INLINE uint32_t LL_HRTIM_TIM_GetEventFilter(const HRTIM_TypeDef *HRTIMx * @arg @ref LL_HRTIM_EELATCH_ENABLED * @retval None */ -__STATIC_INLINE void LL_HRTIM_TIM_SetEventLatchStatus(HRTIM_TypeDef *HRTIMx, uint32_t Timer, uint32_t Event, +__STATIC_INLINE void LL_HRTIM_TIM_SetEventLatchStatus(const HRTIM_TypeDef *HRTIMx, uint32_t Timer, uint32_t Event, uint32_t LatchStatus) { uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - POSITION_VAL(LL_HRTIM_TIMER_A)); uint32_t iEvent = (uint8_t)(POSITION_VAL(Event) - POSITION_VAL(LL_HRTIM_EVENT_1)); __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].EEFxR1) + - REG_OFFSET_TAB_TIMER[iTimer] + REG_OFFSET_TAB_EECR[iEvent])); + REG_OFFSET_TAB_TIMER[iTimer] + REG_OFFSET_TAB_EECR[iEvent])); MODIFY_REG(*pReg, (HRTIM_EEFR1_EE1LTCH << REG_SHIFT_TAB_EExSRC[iEvent]), (LatchStatus << REG_SHIFT_TAB_EExSRC[iEvent])); } @@ -4740,7 +4750,7 @@ __STATIC_INLINE uint32_t LL_HRTIM_TIM_GetEventLatchStatus(const HRTIM_TypeDef *H uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - POSITION_VAL(LL_HRTIM_TIMER_A)); uint32_t iEvent = (uint8_t)(POSITION_VAL(Event) - POSITION_VAL(LL_HRTIM_EVENT_1)); const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].EEFxR1) + - REG_OFFSET_TAB_TIMER[iTimer] + REG_OFFSET_TAB_EECR[iEvent])); + REG_OFFSET_TAB_TIMER[iTimer] + REG_OFFSET_TAB_EECR[iEvent])); return (READ_BIT(*pReg, (uint32_t)(HRTIM_EEFR1_EE1LTCH) << REG_SHIFT_TAB_EExSRC[iEvent]) >> (REG_SHIFT_TAB_EExSRC[iEvent])); } @@ -4770,11 +4780,11 @@ __STATIC_INLINE uint32_t LL_HRTIM_TIM_GetEventLatchStatus(const HRTIM_TypeDef *H * @arg @ref LL_HRTIM_DT_FALLING_POSITIVE or @ref LL_HRTIM_DT_FALLING_NEGATIVE * @retval None */ -__STATIC_INLINE void LL_HRTIM_DT_Config(HRTIM_TypeDef *HRTIMx, uint32_t Timer, uint32_t Configuration) +__STATIC_INLINE void LL_HRTIM_DT_Config(const HRTIM_TypeDef *HRTIMx, uint32_t Timer, uint32_t Configuration) { uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos); __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].DTxR) + - REG_OFFSET_TAB_TIMER[iTimer])); + REG_OFFSET_TAB_TIMER[iTimer])); MODIFY_REG(*pReg, HRTIM_DTR_SDTF | HRTIM_DTR_DTPRSC | HRTIM_DTR_SDTR, Configuration); } @@ -4799,11 +4809,11 @@ __STATIC_INLINE void LL_HRTIM_DT_Config(HRTIM_TypeDef *HRTIMx, uint32_t Timer, u * @arg @ref LL_HRTIM_DT_PRESCALER_DIV16 * @retval None */ -__STATIC_INLINE void LL_HRTIM_DT_SetPrescaler(HRTIM_TypeDef *HRTIMx, uint32_t Timer, uint32_t Prescaler) +__STATIC_INLINE void LL_HRTIM_DT_SetPrescaler(const HRTIM_TypeDef *HRTIMx, uint32_t Timer, uint32_t Prescaler) { uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos); __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].DTxR) + - REG_OFFSET_TAB_TIMER[iTimer])); + REG_OFFSET_TAB_TIMER[iTimer])); MODIFY_REG(*pReg, HRTIM_DTR_DTPRSC, Prescaler); } @@ -4831,7 +4841,7 @@ __STATIC_INLINE uint32_t LL_HRTIM_DT_GetPrescaler(const HRTIM_TypeDef *HRTIMx, u { uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos); const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].DTxR) + - REG_OFFSET_TAB_TIMER[iTimer])); + REG_OFFSET_TAB_TIMER[iTimer])); return (READ_BIT(*pReg, HRTIM_DTR_DTPRSC)); } @@ -4848,11 +4858,11 @@ __STATIC_INLINE uint32_t LL_HRTIM_DT_GetPrescaler(const HRTIM_TypeDef *HRTIMx, u * @param RisingValue Value between 0 and 0x1FF * @retval None */ -__STATIC_INLINE void LL_HRTIM_DT_SetRisingValue(HRTIM_TypeDef *HRTIMx, uint32_t Timer, uint32_t RisingValue) +__STATIC_INLINE void LL_HRTIM_DT_SetRisingValue(const HRTIM_TypeDef *HRTIMx, uint32_t Timer, uint32_t RisingValue) { uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos); __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].DTxR) + - REG_OFFSET_TAB_TIMER[iTimer])); + REG_OFFSET_TAB_TIMER[iTimer])); MODIFY_REG(*pReg, HRTIM_DTR_DTR, RisingValue); } @@ -4872,7 +4882,7 @@ __STATIC_INLINE uint32_t LL_HRTIM_DT_GetRisingValue(const HRTIM_TypeDef *HRTIMx, { uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos); const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].DTxR) + - REG_OFFSET_TAB_TIMER[iTimer])); + REG_OFFSET_TAB_TIMER[iTimer])); return (READ_BIT(*pReg, HRTIM_DTR_DTR)); } @@ -4891,11 +4901,11 @@ __STATIC_INLINE uint32_t LL_HRTIM_DT_GetRisingValue(const HRTIM_TypeDef *HRTIMx, * @arg @ref LL_HRTIM_DT_RISING_NEGATIVE * @retval None */ -__STATIC_INLINE void LL_HRTIM_DT_SetRisingSign(HRTIM_TypeDef *HRTIMx, uint32_t Timer, uint32_t RisingSign) +__STATIC_INLINE void LL_HRTIM_DT_SetRisingSign(const HRTIM_TypeDef *HRTIMx, uint32_t Timer, uint32_t RisingSign) { uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos); __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].DTxR) + - REG_OFFSET_TAB_TIMER[iTimer])); + REG_OFFSET_TAB_TIMER[iTimer])); MODIFY_REG(*pReg, HRTIM_DTR_SDTR, RisingSign); } @@ -4917,7 +4927,7 @@ __STATIC_INLINE uint32_t LL_HRTIM_DT_GetRisingSign(const HRTIM_TypeDef *HRTIMx, { uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos); const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].DTxR) + - REG_OFFSET_TAB_TIMER[iTimer])); + REG_OFFSET_TAB_TIMER[iTimer])); return (READ_BIT(*pReg, HRTIM_DTR_SDTR)); } @@ -4934,11 +4944,11 @@ __STATIC_INLINE uint32_t LL_HRTIM_DT_GetRisingSign(const HRTIM_TypeDef *HRTIMx, * @param FallingValue Value between 0 and 0x1FF * @retval None */ -__STATIC_INLINE void LL_HRTIM_DT_SetFallingValue(HRTIM_TypeDef *HRTIMx, uint32_t Timer, uint32_t FallingValue) +__STATIC_INLINE void LL_HRTIM_DT_SetFallingValue(const HRTIM_TypeDef *HRTIMx, uint32_t Timer, uint32_t FallingValue) { uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos); __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].DTxR) + - REG_OFFSET_TAB_TIMER[iTimer])); + REG_OFFSET_TAB_TIMER[iTimer])); MODIFY_REG(*pReg, HRTIM_DTR_DTF, FallingValue << HRTIM_DTR_DTF_Pos); } @@ -4958,7 +4968,7 @@ __STATIC_INLINE uint32_t LL_HRTIM_DT_GetFallingValue(const HRTIM_TypeDef *HRTIMx { uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos); const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].DTxR) + - REG_OFFSET_TAB_TIMER[iTimer])); + REG_OFFSET_TAB_TIMER[iTimer])); return ((READ_BIT(*pReg, HRTIM_DTR_DTF)) >> HRTIM_DTR_DTF_Pos); } @@ -4977,11 +4987,11 @@ __STATIC_INLINE uint32_t LL_HRTIM_DT_GetFallingValue(const HRTIM_TypeDef *HRTIMx * @arg @ref LL_HRTIM_DT_FALLING_NEGATIVE * @retval None */ -__STATIC_INLINE void LL_HRTIM_DT_SetFallingSign(HRTIM_TypeDef *HRTIMx, uint32_t Timer, uint32_t FallingSign) +__STATIC_INLINE void LL_HRTIM_DT_SetFallingSign(const HRTIM_TypeDef *HRTIMx, uint32_t Timer, uint32_t FallingSign) { uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos); __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].DTxR) + - REG_OFFSET_TAB_TIMER[iTimer])); + REG_OFFSET_TAB_TIMER[iTimer])); MODIFY_REG(*pReg, HRTIM_DTR_SDTF, FallingSign); } @@ -5003,7 +5013,7 @@ __STATIC_INLINE uint32_t LL_HRTIM_DT_GetFallingSign(const HRTIM_TypeDef *HRTIMx, { uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos); const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].DTxR) + - REG_OFFSET_TAB_TIMER[iTimer])); + REG_OFFSET_TAB_TIMER[iTimer])); return (READ_BIT(*pReg, HRTIM_DTR_SDTF)); } @@ -5023,7 +5033,7 @@ __STATIC_INLINE void LL_HRTIM_DT_LockRising(const HRTIM_TypeDef *HRTIMx, uint32_ { uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos); __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].DTxR) + - REG_OFFSET_TAB_TIMER[iTimer])); + REG_OFFSET_TAB_TIMER[iTimer])); SET_BIT(*pReg, HRTIM_DTR_DTRLK); } @@ -5039,11 +5049,11 @@ __STATIC_INLINE void LL_HRTIM_DT_LockRising(const HRTIM_TypeDef *HRTIMx, uint32_ * @arg @ref LL_HRTIM_TIMER_E * @retval None */ -__STATIC_INLINE void LL_HRTIM_DT_LockRisingSign(HRTIM_TypeDef *HRTIMx, uint32_t Timer) +__STATIC_INLINE void LL_HRTIM_DT_LockRisingSign(const HRTIM_TypeDef *HRTIMx, uint32_t Timer) { uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos); __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].DTxR) + - REG_OFFSET_TAB_TIMER[iTimer])); + REG_OFFSET_TAB_TIMER[iTimer])); SET_BIT(*pReg, HRTIM_DTR_DTRSLK); } @@ -5059,11 +5069,11 @@ __STATIC_INLINE void LL_HRTIM_DT_LockRisingSign(HRTIM_TypeDef *HRTIMx, uint32_t * @arg @ref LL_HRTIM_TIMER_E * @retval None */ -__STATIC_INLINE void LL_HRTIM_DT_LockFalling(HRTIM_TypeDef *HRTIMx, uint32_t Timer) +__STATIC_INLINE void LL_HRTIM_DT_LockFalling(const HRTIM_TypeDef *HRTIMx, uint32_t Timer) { uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos); __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].DTxR) + - REG_OFFSET_TAB_TIMER[iTimer])); + REG_OFFSET_TAB_TIMER[iTimer])); SET_BIT(*pReg, HRTIM_DTR_DTFLK); } @@ -5079,11 +5089,11 @@ __STATIC_INLINE void LL_HRTIM_DT_LockFalling(HRTIM_TypeDef *HRTIMx, uint32_t Tim * @arg @ref LL_HRTIM_TIMER_E * @retval None */ -__STATIC_INLINE void LL_HRTIM_DT_LockFallingSign(HRTIM_TypeDef *HRTIMx, uint32_t Timer) +__STATIC_INLINE void LL_HRTIM_DT_LockFallingSign(const HRTIM_TypeDef *HRTIMx, uint32_t Timer) { uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos); __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].DTxR) + - REG_OFFSET_TAB_TIMER[iTimer])); + REG_OFFSET_TAB_TIMER[iTimer])); SET_BIT(*pReg, HRTIM_DTR_DTFSLK); } @@ -5115,11 +5125,11 @@ __STATIC_INLINE void LL_HRTIM_DT_LockFallingSign(HRTIM_TypeDef *HRTIMx, uint32_t * @arg @ref LL_HRTIM_CHP_PULSEWIDTH_16 or ... or @ref LL_HRTIM_CHP_PULSEWIDTH_256 * @retval None */ -__STATIC_INLINE void LL_HRTIM_CHP_Config(HRTIM_TypeDef *HRTIMx, uint32_t Timer, uint32_t Configuration) +__STATIC_INLINE void LL_HRTIM_CHP_Config(const HRTIM_TypeDef *HRTIMx, uint32_t Timer, uint32_t Configuration) { uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos); __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].CHPxR) + - REG_OFFSET_TAB_TIMER[iTimer])); + REG_OFFSET_TAB_TIMER[iTimer])); MODIFY_REG(*pReg, HRTIM_CHPR_STRPW | HRTIM_CHPR_CARDTY | HRTIM_CHPR_CARFRQ, Configuration); } @@ -5155,11 +5165,11 @@ __STATIC_INLINE void LL_HRTIM_CHP_Config(HRTIM_TypeDef *HRTIMx, uint32_t Timer, * @arg @ref LL_HRTIM_CHP_PRESCALER_DIV256 * @retval None */ -__STATIC_INLINE void LL_HRTIM_CHP_SetPrescaler(HRTIM_TypeDef *HRTIMx, uint32_t Timer, uint32_t Prescaler) +__STATIC_INLINE void LL_HRTIM_CHP_SetPrescaler(const HRTIM_TypeDef *HRTIMx, uint32_t Timer, uint32_t Prescaler) { uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos); __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].CHPxR) + - REG_OFFSET_TAB_TIMER[iTimer])); + REG_OFFSET_TAB_TIMER[iTimer])); MODIFY_REG(*pReg, HRTIM_CHPR_CARFRQ, Prescaler); } @@ -5195,7 +5205,7 @@ __STATIC_INLINE uint32_t LL_HRTIM_CHP_GetPrescaler(const HRTIM_TypeDef *HRTIMx, { uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos); const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].CHPxR) + - REG_OFFSET_TAB_TIMER[iTimer])); + REG_OFFSET_TAB_TIMER[iTimer])); return (READ_BIT(*pReg, HRTIM_CHPR_CARFRQ)); } @@ -5223,11 +5233,11 @@ __STATIC_INLINE uint32_t LL_HRTIM_CHP_GetPrescaler(const HRTIM_TypeDef *HRTIMx, * @arg @ref LL_HRTIM_CHP_DUTYCYCLE_875 * @retval None */ -__STATIC_INLINE void LL_HRTIM_CHP_SetDutyCycle(HRTIM_TypeDef *HRTIMx, uint32_t Timer, uint32_t DutyCycle) +__STATIC_INLINE void LL_HRTIM_CHP_SetDutyCycle(const HRTIM_TypeDef *HRTIMx, uint32_t Timer, uint32_t DutyCycle) { uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos); __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].CHPxR) + - REG_OFFSET_TAB_TIMER[iTimer])); + REG_OFFSET_TAB_TIMER[iTimer])); MODIFY_REG(*pReg, HRTIM_CHPR_CARDTY, DutyCycle); } @@ -5255,7 +5265,7 @@ __STATIC_INLINE uint32_t LL_HRTIM_CHP_GetDutyCycle(const HRTIM_TypeDef *HRTIMx, { uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos); const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].CHPxR) + - REG_OFFSET_TAB_TIMER[iTimer])); + REG_OFFSET_TAB_TIMER[iTimer])); return (READ_BIT(*pReg, HRTIM_CHPR_CARDTY)); } @@ -5290,11 +5300,11 @@ __STATIC_INLINE uint32_t LL_HRTIM_CHP_GetDutyCycle(const HRTIM_TypeDef *HRTIMx, * @arg @ref LL_HRTIM_CHP_PULSEWIDTH_256 * @retval None */ -__STATIC_INLINE void LL_HRTIM_CHP_SetPulseWidth(HRTIM_TypeDef *HRTIMx, uint32_t Timer, uint32_t PulseWidth) +__STATIC_INLINE void LL_HRTIM_CHP_SetPulseWidth(const HRTIM_TypeDef *HRTIMx, uint32_t Timer, uint32_t PulseWidth) { uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos); __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].CHPxR) + - REG_OFFSET_TAB_TIMER[iTimer])); + REG_OFFSET_TAB_TIMER[iTimer])); MODIFY_REG(*pReg, HRTIM_CHPR_STRPW, PulseWidth); } @@ -5330,7 +5340,7 @@ __STATIC_INLINE uint32_t LL_HRTIM_CHP_GetPulseWidth(const HRTIM_TypeDef *HRTIMx, { uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos); const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].CHPxR) + - REG_OFFSET_TAB_TIMER[iTimer])); + REG_OFFSET_TAB_TIMER[iTimer])); return (READ_BIT(*pReg, HRTIM_CHPR_STRPW)); } @@ -5455,11 +5465,11 @@ __STATIC_INLINE uint32_t LL_HRTIM_CHP_GetPulseWidth(const HRTIM_TypeDef *HRTIMx, * @arg @ref LL_HRTIM_CROSSBAR_UPDATE * @retval None */ -__STATIC_INLINE void LL_HRTIM_OUT_SetOutputSetSrc(HRTIM_TypeDef *HRTIMx, uint32_t Output, uint32_t SetSrc) +__STATIC_INLINE void LL_HRTIM_OUT_SetOutputSetSrc(const HRTIM_TypeDef *HRTIMx, uint32_t Output, uint32_t SetSrc) { uint32_t iOutput = (uint8_t)(POSITION_VAL(Output) - POSITION_VAL(LL_HRTIM_OUTPUT_TA1)); __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].SETx1R) + - REG_OFFSET_TAB_SETxR[iOutput])); + REG_OFFSET_TAB_SETxR[iOutput])); WRITE_REG(*pReg, SetSrc); } @@ -5579,7 +5589,7 @@ __STATIC_INLINE uint32_t LL_HRTIM_OUT_GetOutputSetSrc(const HRTIM_TypeDef *HRTIM { uint32_t iOutput = (uint8_t)(POSITION_VAL(Output) - POSITION_VAL(LL_HRTIM_OUTPUT_TA1)); const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].SETx1R) + - REG_OFFSET_TAB_SETxR[iOutput])); + REG_OFFSET_TAB_SETxR[iOutput])); return (uint32_t) READ_REG(*pReg); } @@ -5696,11 +5706,11 @@ __STATIC_INLINE uint32_t LL_HRTIM_OUT_GetOutputSetSrc(const HRTIM_TypeDef *HRTIM * @arg @ref LL_HRTIM_CROSSBAR_UPDATE * @retval None */ -__STATIC_INLINE void LL_HRTIM_OUT_SetOutputResetSrc(HRTIM_TypeDef *HRTIMx, uint32_t Output, uint32_t ResetSrc) +__STATIC_INLINE void LL_HRTIM_OUT_SetOutputResetSrc(const HRTIM_TypeDef *HRTIMx, uint32_t Output, uint32_t ResetSrc) { uint32_t iOutput = (uint8_t)(POSITION_VAL(Output) - POSITION_VAL(LL_HRTIM_OUTPUT_TA1)); __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].RSTx1R) + - REG_OFFSET_TAB_SETxR[iOutput])); + REG_OFFSET_TAB_SETxR[iOutput])); WRITE_REG(*pReg, ResetSrc); } @@ -5820,7 +5830,7 @@ __STATIC_INLINE uint32_t LL_HRTIM_OUT_GetOutputResetSrc(const HRTIM_TypeDef *HRT { uint32_t iOutput = (uint8_t)(POSITION_VAL(Output) - POSITION_VAL(LL_HRTIM_OUTPUT_TA1)); const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].RSTx1R) + - REG_OFFSET_TAB_SETxR[iOutput])); + REG_OFFSET_TAB_SETxR[iOutput])); return (uint32_t) READ_REG(*pReg); } @@ -5859,11 +5869,11 @@ __STATIC_INLINE uint32_t LL_HRTIM_OUT_GetOutputResetSrc(const HRTIM_TypeDef *HRT * @arg @ref LL_HRTIM_OUT_BM_ENTRYMODE_REGULAR or @ref LL_HRTIM_OUT_BM_ENTRYMODE_DELAYED * @retval None */ -__STATIC_INLINE void LL_HRTIM_OUT_Config(HRTIM_TypeDef *HRTIMx, uint32_t Output, uint32_t Configuration) +__STATIC_INLINE void LL_HRTIM_OUT_Config(const HRTIM_TypeDef *HRTIMx, uint32_t Output, uint32_t Configuration) { uint32_t iOutput = (uint8_t)(POSITION_VAL(Output) - POSITION_VAL(LL_HRTIM_OUTPUT_TA1)); __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].OUTxR) + - REG_OFFSET_TAB_OUTxR[iOutput])); + REG_OFFSET_TAB_OUTxR[iOutput])); MODIFY_REG(*pReg, (HRTIM_OUT_CONFIG_MASK << REG_SHIFT_TAB_OUTxR[iOutput]), (Configuration << REG_SHIFT_TAB_OUTxR[iOutput])); } @@ -5889,11 +5899,11 @@ __STATIC_INLINE void LL_HRTIM_OUT_Config(HRTIM_TypeDef *HRTIMx, uint32_t Output, * @arg @ref LL_HRTIM_OUT_NEGATIVE_POLARITY * @retval None */ -__STATIC_INLINE void LL_HRTIM_OUT_SetPolarity(HRTIM_TypeDef *HRTIMx, uint32_t Output, uint32_t Polarity) +__STATIC_INLINE void LL_HRTIM_OUT_SetPolarity(const HRTIM_TypeDef *HRTIMx, uint32_t Output, uint32_t Polarity) { uint32_t iOutput = (uint8_t)(POSITION_VAL(Output) - POSITION_VAL(LL_HRTIM_OUTPUT_TA1)); __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].OUTxR) + - REG_OFFSET_TAB_OUTxR[iOutput])); + REG_OFFSET_TAB_OUTxR[iOutput])); MODIFY_REG(*pReg, (HRTIM_OUTR_POL1 << REG_SHIFT_TAB_OUTxR[iOutput]), (Polarity << REG_SHIFT_TAB_OUTxR[iOutput])); } @@ -5921,7 +5931,7 @@ __STATIC_INLINE uint32_t LL_HRTIM_OUT_GetPolarity(const HRTIM_TypeDef *HRTIMx, u { uint32_t iOutput = (uint8_t)(POSITION_VAL(Output) - POSITION_VAL(LL_HRTIM_OUTPUT_TA1)); const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].OUTxR) + - REG_OFFSET_TAB_OUTxR[iOutput])); + REG_OFFSET_TAB_OUTxR[iOutput])); return (READ_BIT(*pReg, (uint32_t)(HRTIM_OUTR_POL1) << REG_SHIFT_TAB_OUTxR[iOutput]) >> REG_SHIFT_TAB_OUTxR[iOutput]); } @@ -5947,11 +5957,11 @@ __STATIC_INLINE uint32_t LL_HRTIM_OUT_GetPolarity(const HRTIM_TypeDef *HRTIMx, u * @arg @ref LL_HRTIM_OUT_IDLE_WHEN_BURST * @retval None */ -__STATIC_INLINE void LL_HRTIM_OUT_SetIdleMode(HRTIM_TypeDef *HRTIMx, uint32_t Output, uint32_t IdleMode) +__STATIC_INLINE void LL_HRTIM_OUT_SetIdleMode(const HRTIM_TypeDef *HRTIMx, uint32_t Output, uint32_t IdleMode) { uint32_t iOutput = (uint8_t)(POSITION_VAL(Output) - POSITION_VAL(LL_HRTIM_OUTPUT_TA1)); __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].OUTxR) + - REG_OFFSET_TAB_OUTxR[iOutput])); + REG_OFFSET_TAB_OUTxR[iOutput])); MODIFY_REG(*pReg, (HRTIM_OUTR_IDLM1 << (REG_SHIFT_TAB_OUTxR[iOutput])), (IdleMode << (REG_SHIFT_TAB_OUTxR[iOutput]))); } @@ -5979,7 +5989,7 @@ __STATIC_INLINE uint32_t LL_HRTIM_OUT_GetIdleMode(const HRTIM_TypeDef *HRTIMx, u { uint32_t iOutput = (uint8_t)(POSITION_VAL(Output) - POSITION_VAL(LL_HRTIM_OUTPUT_TA1)); const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].OUTxR) + - REG_OFFSET_TAB_OUTxR[iOutput])); + REG_OFFSET_TAB_OUTxR[iOutput])); return (READ_BIT(*pReg, (uint32_t)(HRTIM_OUTR_IDLM1) << REG_SHIFT_TAB_OUTxR[iOutput]) >> REG_SHIFT_TAB_OUTxR[iOutput]); } @@ -6006,11 +6016,11 @@ __STATIC_INLINE uint32_t LL_HRTIM_OUT_GetIdleMode(const HRTIM_TypeDef *HRTIMx, u * @arg @ref LL_HRTIM_OUT_IDLELEVEL_ACTIVE * @retval None */ -__STATIC_INLINE void LL_HRTIM_OUT_SetIdleLevel(HRTIM_TypeDef *HRTIMx, uint32_t Output, uint32_t IdleLevel) +__STATIC_INLINE void LL_HRTIM_OUT_SetIdleLevel(const HRTIM_TypeDef *HRTIMx, uint32_t Output, uint32_t IdleLevel) { uint32_t iOutput = (uint8_t)(POSITION_VAL(Output) - POSITION_VAL(LL_HRTIM_OUTPUT_TA1)); __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].OUTxR) + - REG_OFFSET_TAB_OUTxR[iOutput])); + REG_OFFSET_TAB_OUTxR[iOutput])); MODIFY_REG(*pReg, (HRTIM_OUTR_IDLES1 << REG_SHIFT_TAB_OUTxR[iOutput]), (IdleLevel << REG_SHIFT_TAB_OUTxR[iOutput])); } @@ -6038,7 +6048,7 @@ __STATIC_INLINE uint32_t LL_HRTIM_OUT_GetIdleLevel(const HRTIM_TypeDef *HRTIMx, { uint32_t iOutput = (uint8_t)(POSITION_VAL(Output) - POSITION_VAL(LL_HRTIM_OUTPUT_TA1)); const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].OUTxR) + - REG_OFFSET_TAB_OUTxR[iOutput])); + REG_OFFSET_TAB_OUTxR[iOutput])); return (READ_BIT(*pReg, (uint32_t)(HRTIM_OUTR_IDLES1) << REG_SHIFT_TAB_OUTxR[iOutput]) >> REG_SHIFT_TAB_OUTxR[iOutput]); } @@ -6067,11 +6077,11 @@ __STATIC_INLINE uint32_t LL_HRTIM_OUT_GetIdleLevel(const HRTIM_TypeDef *HRTIMx, * @arg @ref LL_HRTIM_OUT_FAULTSTATE_HIGHZ * @retval None */ -__STATIC_INLINE void LL_HRTIM_OUT_SetFaultState(HRTIM_TypeDef *HRTIMx, uint32_t Output, uint32_t FaultState) +__STATIC_INLINE void LL_HRTIM_OUT_SetFaultState(const HRTIM_TypeDef *HRTIMx, uint32_t Output, uint32_t FaultState) { uint32_t iOutput = (uint8_t)(POSITION_VAL(Output) - POSITION_VAL(LL_HRTIM_OUTPUT_TA1)); __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].OUTxR) + - REG_OFFSET_TAB_OUTxR[iOutput])); + REG_OFFSET_TAB_OUTxR[iOutput])); MODIFY_REG(*pReg, (HRTIM_OUTR_FAULT1 << REG_SHIFT_TAB_OUTxR[iOutput]), (FaultState << REG_SHIFT_TAB_OUTxR[iOutput])); } @@ -6101,7 +6111,7 @@ __STATIC_INLINE uint32_t LL_HRTIM_OUT_GetFaultState(const HRTIM_TypeDef *HRTIMx, { uint32_t iOutput = (uint8_t)(POSITION_VAL(Output) - POSITION_VAL(LL_HRTIM_OUTPUT_TA1)); const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].OUTxR) + - REG_OFFSET_TAB_OUTxR[iOutput])); + REG_OFFSET_TAB_OUTxR[iOutput])); return (READ_BIT(*pReg, (uint32_t)(HRTIM_OUTR_FAULT1) << REG_SHIFT_TAB_OUTxR[iOutput]) >> REG_SHIFT_TAB_OUTxR[iOutput]); } @@ -6127,11 +6137,11 @@ __STATIC_INLINE uint32_t LL_HRTIM_OUT_GetFaultState(const HRTIM_TypeDef *HRTIMx, * @arg @ref LL_HRTIM_OUT_CHOPPERMODE_ENABLED * @retval None */ -__STATIC_INLINE void LL_HRTIM_OUT_SetChopperMode(HRTIM_TypeDef *HRTIMx, uint32_t Output, uint32_t ChopperMode) +__STATIC_INLINE void LL_HRTIM_OUT_SetChopperMode(const HRTIM_TypeDef *HRTIMx, uint32_t Output, uint32_t ChopperMode) { uint32_t iOutput = (uint8_t)(POSITION_VAL(Output) - POSITION_VAL(LL_HRTIM_OUTPUT_TA1)); __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].OUTxR) + - REG_OFFSET_TAB_OUTxR[iOutput])); + REG_OFFSET_TAB_OUTxR[iOutput])); MODIFY_REG(*pReg, (HRTIM_OUTR_CHP1 << REG_SHIFT_TAB_OUTxR[iOutput]), (ChopperMode << REG_SHIFT_TAB_OUTxR[iOutput])); } @@ -6159,7 +6169,7 @@ __STATIC_INLINE uint32_t LL_HRTIM_OUT_GetChopperMode(const HRTIM_TypeDef *HRTIMx { uint32_t iOutput = (uint8_t)(POSITION_VAL(Output) - POSITION_VAL(LL_HRTIM_OUTPUT_TA1)); const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].OUTxR) + - REG_OFFSET_TAB_OUTxR[iOutput])); + REG_OFFSET_TAB_OUTxR[iOutput])); return (READ_BIT(*pReg, (uint32_t)(HRTIM_OUTR_CHP1) << REG_SHIFT_TAB_OUTxR[iOutput]) >> REG_SHIFT_TAB_OUTxR[iOutput]); } @@ -6185,11 +6195,11 @@ __STATIC_INLINE uint32_t LL_HRTIM_OUT_GetChopperMode(const HRTIM_TypeDef *HRTIMx * @arg @ref LL_HRTIM_OUT_BM_ENTRYMODE_DELAYED * @retval None */ -__STATIC_INLINE void LL_HRTIM_OUT_SetBMEntryMode(HRTIM_TypeDef *HRTIMx, uint32_t Output, uint32_t BMEntryMode) +__STATIC_INLINE void LL_HRTIM_OUT_SetBMEntryMode(const HRTIM_TypeDef *HRTIMx, uint32_t Output, uint32_t BMEntryMode) { uint32_t iOutput = (uint8_t)(POSITION_VAL(Output) - POSITION_VAL(LL_HRTIM_OUTPUT_TA1)); __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].OUTxR) + - REG_OFFSET_TAB_OUTxR[iOutput])); + REG_OFFSET_TAB_OUTxR[iOutput])); MODIFY_REG(*pReg, (HRTIM_OUTR_DIDL1 << REG_SHIFT_TAB_OUTxR[iOutput]), (BMEntryMode << REG_SHIFT_TAB_OUTxR[iOutput])); } @@ -6217,7 +6227,7 @@ __STATIC_INLINE uint32_t LL_HRTIM_OUT_GetBMEntryMode(const HRTIM_TypeDef *HRTIMx { uint32_t iOutput = (uint8_t)(POSITION_VAL(Output) - POSITION_VAL(LL_HRTIM_OUTPUT_TA1)); const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].OUTxR) + - REG_OFFSET_TAB_OUTxR[iOutput])); + REG_OFFSET_TAB_OUTxR[iOutput])); return (READ_BIT(*pReg, (uint32_t)(HRTIM_OUTR_DIDL1) << REG_SHIFT_TAB_OUTxR[iOutput]) >> REG_SHIFT_TAB_OUTxR[iOutput]); } @@ -6246,7 +6256,7 @@ __STATIC_INLINE uint32_t LL_HRTIM_OUT_GetDLYPRTOutStatus(const HRTIM_TypeDef *HR { uint32_t iOutput = (uint8_t)(POSITION_VAL(Output) - POSITION_VAL(LL_HRTIM_OUTPUT_TA1)); const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].TIMxISR) + - REG_OFFSET_TAB_OUTxR[iOutput])); + REG_OFFSET_TAB_OUTxR[iOutput])); return ((READ_BIT(*pReg, (uint32_t)(HRTIM_TIMISR_O1STAT) << REG_SHIFT_TAB_OxSTAT[iOutput]) >> REG_SHIFT_TAB_OxSTAT[iOutput]) >> HRTIM_TIMISR_O1STAT_Pos); } @@ -6274,7 +6284,7 @@ __STATIC_INLINE uint32_t LL_HRTIM_OUT_GetDLYPRTOutStatus(const HRTIM_TypeDef *HR * @arg @ref LL_HRTIM_OUT_LEVEL_ACTIVE * @retval None */ -__STATIC_INLINE void LL_HRTIM_OUT_ForceLevel(HRTIM_TypeDef *HRTIMx, uint32_t Output, uint32_t OutputLevel) +__STATIC_INLINE void LL_HRTIM_OUT_ForceLevel(const HRTIM_TypeDef *HRTIMx, uint32_t Output, uint32_t OutputLevel) { const uint8_t REG_OFFSET_TAB_OUT_LEVEL[] = { @@ -6284,7 +6294,7 @@ __STATIC_INLINE void LL_HRTIM_OUT_ForceLevel(HRTIM_TypeDef *HRTIMx, uint32_t Out uint32_t iOutput = (uint8_t)(POSITION_VAL(Output) - POSITION_VAL(LL_HRTIM_OUTPUT_TA1)); __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].SETx1R) + - REG_OFFSET_TAB_SETxR[iOutput] + REG_OFFSET_TAB_OUT_LEVEL[OutputLevel])); + REG_OFFSET_TAB_SETxR[iOutput] + REG_OFFSET_TAB_OUT_LEVEL[OutputLevel])); SET_BIT(*pReg, HRTIM_SET1R_SST); } @@ -6312,7 +6322,7 @@ __STATIC_INLINE uint32_t LL_HRTIM_OUT_GetLevel(const HRTIM_TypeDef *HRTIMx, uint { uint32_t iOutput = (uint8_t)(POSITION_VAL(Output) - POSITION_VAL(LL_HRTIM_OUTPUT_TA1)); const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].TIMxISR) + - REG_OFFSET_TAB_OUTxR[iOutput])); + REG_OFFSET_TAB_OUTxR[iOutput])); return ((READ_BIT(*pReg, (uint32_t)(HRTIM_TIMISR_O1CPY) << REG_SHIFT_TAB_OxSTAT[iOutput]) >> REG_SHIFT_TAB_OxSTAT[iOutput]) >> HRTIM_TIMISR_O1CPY_Pos); } @@ -6389,11 +6399,11 @@ __STATIC_INLINE uint32_t LL_HRTIM_OUT_GetLevel(const HRTIM_TypeDef *HRTIMx, uint * @arg @ref LL_HRTIM_EE_FASTMODE_DISABLE or @ref LL_HRTIM_EE_FASTMODE_ENABLE * @retval None */ -__STATIC_INLINE void LL_HRTIM_EE_Config(HRTIM_TypeDef *HRTIMx, uint32_t Event, uint32_t Configuration) +__STATIC_INLINE void LL_HRTIM_EE_Config(const HRTIM_TypeDef *HRTIMx, uint32_t Event, uint32_t Configuration) { uint32_t iEvent = (uint8_t)(POSITION_VAL(Event) - POSITION_VAL(LL_HRTIM_EVENT_1)); __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sCommonRegs.EECR1) + - REG_OFFSET_TAB_EECR[iEvent])); + REG_OFFSET_TAB_EECR[iEvent])); MODIFY_REG(*pReg, (HRTIM_EE_CONFIG_MASK << REG_SHIFT_TAB_EExSRC[iEvent]), (Configuration << REG_SHIFT_TAB_EExSRC[iEvent])); } @@ -6429,11 +6439,11 @@ __STATIC_INLINE void LL_HRTIM_EE_Config(HRTIM_TypeDef *HRTIMx, uint32_t Event, u * @arg External event source 4 * @retval None */ -__STATIC_INLINE void LL_HRTIM_EE_SetSrc(HRTIM_TypeDef *HRTIMx, uint32_t Event, uint32_t Src) +__STATIC_INLINE void LL_HRTIM_EE_SetSrc(const HRTIM_TypeDef *HRTIMx, uint32_t Event, uint32_t Src) { uint32_t iEvent = (uint8_t)(POSITION_VAL(Event) - POSITION_VAL(LL_HRTIM_EVENT_1)); __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sCommonRegs.EECR1) + - REG_OFFSET_TAB_EECR[iEvent])); + REG_OFFSET_TAB_EECR[iEvent])); MODIFY_REG(*pReg, (HRTIM_EECR1_EE1SRC << REG_SHIFT_TAB_EExSRC[iEvent]), (Src << REG_SHIFT_TAB_EExSRC[iEvent])); } @@ -6471,7 +6481,7 @@ __STATIC_INLINE uint32_t LL_HRTIM_EE_GetSrc(const HRTIM_TypeDef *HRTIMx, uint32_ { uint32_t iEvent = (uint8_t)(POSITION_VAL(Event) - POSITION_VAL(LL_HRTIM_EVENT_1)); const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sCommonRegs.EECR1) + - REG_OFFSET_TAB_EECR[iEvent])); + REG_OFFSET_TAB_EECR[iEvent])); return (READ_BIT(*pReg, (uint32_t)(HRTIM_EECR1_EE1SRC) << REG_SHIFT_TAB_EExSRC[iEvent]) >> REG_SHIFT_TAB_EExSRC[iEvent]); } @@ -6506,11 +6516,11 @@ __STATIC_INLINE uint32_t LL_HRTIM_EE_GetSrc(const HRTIM_TypeDef *HRTIMx, uint32_ * @arg @ref LL_HRTIM_EE_POLARITY_LOW * @retval None */ -__STATIC_INLINE void LL_HRTIM_EE_SetPolarity(HRTIM_TypeDef *HRTIMx, uint32_t Event, uint32_t Polarity) +__STATIC_INLINE void LL_HRTIM_EE_SetPolarity(const HRTIM_TypeDef *HRTIMx, uint32_t Event, uint32_t Polarity) { uint32_t iEvent = (uint8_t)(POSITION_VAL(Event) - POSITION_VAL(LL_HRTIM_EVENT_1)); __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sCommonRegs.EECR1) + - REG_OFFSET_TAB_EECR[iEvent])); + REG_OFFSET_TAB_EECR[iEvent])); MODIFY_REG(*pReg, (HRTIM_EECR1_EE1POL << REG_SHIFT_TAB_EExSRC[iEvent]), (Polarity << REG_SHIFT_TAB_EExSRC[iEvent])); } @@ -6546,7 +6556,7 @@ __STATIC_INLINE uint32_t LL_HRTIM_EE_GetPolarity(const HRTIM_TypeDef *HRTIMx, ui { uint32_t iEvent = (uint8_t)(POSITION_VAL(Event) - POSITION_VAL(LL_HRTIM_EVENT_1)); const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sCommonRegs.EECR1) + - REG_OFFSET_TAB_EECR[iEvent])); + REG_OFFSET_TAB_EECR[iEvent])); return (READ_BIT(*pReg, (uint32_t)(HRTIM_EECR1_EE1POL) << REG_SHIFT_TAB_EExSRC[iEvent]) >> REG_SHIFT_TAB_EExSRC[iEvent]); } @@ -6582,11 +6592,11 @@ __STATIC_INLINE uint32_t LL_HRTIM_EE_GetPolarity(const HRTIM_TypeDef *HRTIMx, ui * @retval None */ -__STATIC_INLINE void LL_HRTIM_EE_SetSensitivity(HRTIM_TypeDef *HRTIMx, uint32_t Event, uint32_t Sensitivity) +__STATIC_INLINE void LL_HRTIM_EE_SetSensitivity(const HRTIM_TypeDef *HRTIMx, uint32_t Event, uint32_t Sensitivity) { uint32_t iEvent = (uint8_t)(POSITION_VAL(Event) - POSITION_VAL(LL_HRTIM_EVENT_1)); __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sCommonRegs.EECR1) + - REG_OFFSET_TAB_EECR[iEvent])); + REG_OFFSET_TAB_EECR[iEvent])); MODIFY_REG(*pReg, (HRTIM_EECR1_EE1SNS << REG_SHIFT_TAB_EExSRC[iEvent]), (Sensitivity << REG_SHIFT_TAB_EExSRC[iEvent])); } @@ -6624,7 +6634,7 @@ __STATIC_INLINE uint32_t LL_HRTIM_EE_GetSensitivity(const HRTIM_TypeDef *HRTIMx, { uint32_t iEvent = (uint8_t)(POSITION_VAL(Event) - POSITION_VAL(LL_HRTIM_EVENT_1)); const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sCommonRegs.EECR1) + - REG_OFFSET_TAB_EECR[iEvent])); + REG_OFFSET_TAB_EECR[iEvent])); return (READ_BIT(*pReg, (uint32_t)(HRTIM_EECR1_EE1SNS) << REG_SHIFT_TAB_EExSRC[iEvent]) >> REG_SHIFT_TAB_EExSRC[iEvent]); } @@ -6653,11 +6663,11 @@ __STATIC_INLINE uint32_t LL_HRTIM_EE_GetSensitivity(const HRTIM_TypeDef *HRTIMx, * @arg @ref LL_HRTIM_EE_FASTMODE_ENABLE * @retval None */ -__STATIC_INLINE void LL_HRTIM_EE_SetFastMode(HRTIM_TypeDef *HRTIMx, uint32_t Event, uint32_t FastMode) +__STATIC_INLINE void LL_HRTIM_EE_SetFastMode(const HRTIM_TypeDef *HRTIMx, uint32_t Event, uint32_t FastMode) { uint32_t iEvent = (uint8_t)(POSITION_VAL(Event) - POSITION_VAL(LL_HRTIM_EVENT_1)); __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sCommonRegs.EECR1) + - REG_OFFSET_TAB_EECR[iEvent])); + REG_OFFSET_TAB_EECR[iEvent])); MODIFY_REG(*pReg, (HRTIM_EECR1_EE1FAST << REG_SHIFT_TAB_EExSRC[iEvent]), (FastMode << REG_SHIFT_TAB_EExSRC[iEvent])); } @@ -6688,7 +6698,7 @@ __STATIC_INLINE uint32_t LL_HRTIM_EE_GetFastMode(const HRTIM_TypeDef *HRTIMx, ui { uint32_t iEvent = (uint8_t)(POSITION_VAL(Event) - POSITION_VAL(LL_HRTIM_EVENT_1)); const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sCommonRegs.EECR1) + - REG_OFFSET_TAB_EECR[iEvent])); + REG_OFFSET_TAB_EECR[iEvent])); return (READ_BIT(*pReg, (uint32_t)(HRTIM_EECR1_EE1FAST) << REG_SHIFT_TAB_EExSRC[iEvent]) >> REG_SHIFT_TAB_EExSRC[iEvent]); } @@ -6836,11 +6846,11 @@ __STATIC_INLINE uint32_t LL_HRTIM_EE_GetPrescaler(const HRTIM_TypeDef *HRTIMx) * @arg @ref LL_HRTIM_FLT_POLARITY_LOW..LL_HRTIM_FLT_POLARITY_HIGH * @retval None */ -__STATIC_INLINE void LL_HRTIM_FLT_Config(HRTIM_TypeDef *HRTIMx, uint32_t Fault, uint32_t Configuration) +__STATIC_INLINE void LL_HRTIM_FLT_Config(const HRTIM_TypeDef *HRTIMx, uint32_t Fault, uint32_t Configuration) { uint32_t iFault = (uint8_t)POSITION_VAL(Fault); __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sCommonRegs.FLTINR1) + - REG_OFFSET_TAB_FLTINR[iFault])); + REG_OFFSET_TAB_FLTINR[iFault])); MODIFY_REG(*pReg, (HRTIM_FLT_CONFIG_MASK << REG_SHIFT_TAB_FLTxE[iFault]), (Configuration << REG_SHIFT_TAB_FLTxE[iFault])); } @@ -6865,11 +6875,11 @@ __STATIC_INLINE void LL_HRTIM_FLT_Config(HRTIM_TypeDef *HRTIMx, uint32_t Fault, * @arg @ref LL_HRTIM_FLT_SRC_INTERNAL * @retval None */ -__STATIC_INLINE void LL_HRTIM_FLT_SetSrc(HRTIM_TypeDef *HRTIMx, uint32_t Fault, uint32_t Src) +__STATIC_INLINE void LL_HRTIM_FLT_SetSrc(const HRTIM_TypeDef *HRTIMx, uint32_t Fault, uint32_t Src) { uint32_t iFault = (uint8_t)POSITION_VAL(Fault); __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sCommonRegs.FLTINR1) + - REG_OFFSET_TAB_FLTINR[iFault])); + REG_OFFSET_TAB_FLTINR[iFault])); MODIFY_REG(*pReg, (HRTIM_FLTINR1_FLT1SRC << REG_SHIFT_TAB_FLTxE[iFault]), (Src << REG_SHIFT_TAB_FLTxE[iFault])); } @@ -6894,8 +6904,8 @@ __STATIC_INLINE void LL_HRTIM_FLT_SetSrc(HRTIM_TypeDef *HRTIMx, uint32_t Fault, __STATIC_INLINE uint32_t LL_HRTIM_FLT_GetSrc(const HRTIM_TypeDef *HRTIMx, uint32_t Fault) { uint32_t iFault = (uint8_t)POSITION_VAL(Fault); - __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sCommonRegs.FLTINR1) + - REG_OFFSET_TAB_FLTINR[iFault])); + const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sCommonRegs.FLTINR1) + + REG_OFFSET_TAB_FLTINR[iFault])); return (READ_BIT(*pReg, (HRTIM_FLTINR1_FLT1SRC << REG_SHIFT_TAB_FLTxE[iFault])) >> REG_SHIFT_TAB_FLTxE[iFault]); } @@ -6919,11 +6929,11 @@ __STATIC_INLINE uint32_t LL_HRTIM_FLT_GetSrc(const HRTIM_TypeDef *HRTIMx, uint32 * @arg @ref LL_HRTIM_FLT_POLARITY_HIGH * @retval None */ -__STATIC_INLINE void LL_HRTIM_FLT_SetPolarity(HRTIM_TypeDef *HRTIMx, uint32_t Fault, uint32_t Polarity) +__STATIC_INLINE void LL_HRTIM_FLT_SetPolarity(const HRTIM_TypeDef *HRTIMx, uint32_t Fault, uint32_t Polarity) { uint32_t iFault = (uint8_t)POSITION_VAL(Fault); __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sCommonRegs.FLTINR1) + - REG_OFFSET_TAB_FLTINR[iFault])); + REG_OFFSET_TAB_FLTINR[iFault])); MODIFY_REG(*pReg, (HRTIM_FLTINR1_FLT1P << REG_SHIFT_TAB_FLTxE[iFault]), (Polarity << REG_SHIFT_TAB_FLTxE[iFault])); } @@ -6948,8 +6958,8 @@ __STATIC_INLINE void LL_HRTIM_FLT_SetPolarity(HRTIM_TypeDef *HRTIMx, uint32_t Fa __STATIC_INLINE uint32_t LL_HRTIM_FLT_GetPolarity(const HRTIM_TypeDef *HRTIMx, uint32_t Fault) { uint32_t iFault = (uint8_t)POSITION_VAL(Fault); - __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sCommonRegs.FLTINR1) + - REG_OFFSET_TAB_FLTINR[iFault])); + const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sCommonRegs.FLTINR1) + + REG_OFFSET_TAB_FLTINR[iFault])); return (READ_BIT(*pReg, (HRTIM_FLTINR1_FLT1P << REG_SHIFT_TAB_FLTxE[iFault])) >> REG_SHIFT_TAB_FLTxE[iFault]); } @@ -6987,11 +6997,11 @@ __STATIC_INLINE uint32_t LL_HRTIM_FLT_GetPolarity(const HRTIM_TypeDef *HRTIMx, u * @arg @ref LL_HRTIM_FLT_FILTER_15 * @retval None */ -__STATIC_INLINE void LL_HRTIM_FLT_SetFilter(HRTIM_TypeDef *HRTIMx, uint32_t Fault, uint32_t Filter) +__STATIC_INLINE void LL_HRTIM_FLT_SetFilter(const HRTIM_TypeDef *HRTIMx, uint32_t Fault, uint32_t Filter) { uint32_t iFault = (uint8_t)POSITION_VAL(Fault); __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sCommonRegs.FLTINR1) + - REG_OFFSET_TAB_FLTINR[iFault])); + REG_OFFSET_TAB_FLTINR[iFault])); MODIFY_REG(*pReg, (HRTIM_FLTINR1_FLT1F << REG_SHIFT_TAB_FLTxE[iFault]), (Filter << REG_SHIFT_TAB_FLTxE[iFault])); } @@ -7030,8 +7040,8 @@ __STATIC_INLINE void LL_HRTIM_FLT_SetFilter(HRTIM_TypeDef *HRTIMx, uint32_t Faul __STATIC_INLINE uint32_t LL_HRTIM_FLT_GetFilter(const HRTIM_TypeDef *HRTIMx, uint32_t Fault) { uint32_t iFault = (uint8_t)POSITION_VAL(Fault); - __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sCommonRegs.FLTINR1) + - REG_OFFSET_TAB_FLTINR[iFault])); + const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sCommonRegs.FLTINR1) + + REG_OFFSET_TAB_FLTINR[iFault])); return (READ_BIT(*pReg, (HRTIM_FLTINR1_FLT1F << REG_SHIFT_TAB_FLTxE[iFault])) >> REG_SHIFT_TAB_FLTxE[iFault]); } @@ -7083,11 +7093,11 @@ __STATIC_INLINE uint32_t LL_HRTIM_FLT_GetPrescaler(const HRTIM_TypeDef *HRTIMx) * @arg @ref LL_HRTIM_FAULT_5 * @retval None */ -__STATIC_INLINE void LL_HRTIM_FLT_Lock(HRTIM_TypeDef *HRTIMx, uint32_t Fault) +__STATIC_INLINE void LL_HRTIM_FLT_Lock(const HRTIM_TypeDef *HRTIMx, uint32_t Fault) { uint32_t iFault = (uint8_t)POSITION_VAL(Fault); __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sCommonRegs.FLTINR1) + - REG_OFFSET_TAB_FLTINR[iFault])); + REG_OFFSET_TAB_FLTINR[iFault])); SET_BIT(*pReg, (HRTIM_FLTINR1_FLT1LCK << REG_SHIFT_TAB_FLTxE[iFault])); } @@ -7107,11 +7117,11 @@ __STATIC_INLINE void LL_HRTIM_FLT_Lock(HRTIM_TypeDef *HRTIMx, uint32_t Fault) * @arg @ref LL_HRTIM_FAULT_5 * @retval None */ -__STATIC_INLINE void LL_HRTIM_FLT_Enable(HRTIM_TypeDef *HRTIMx, uint32_t Fault) +__STATIC_INLINE void LL_HRTIM_FLT_Enable(const HRTIM_TypeDef *HRTIMx, uint32_t Fault) { uint32_t iFault = (uint8_t)POSITION_VAL(Fault); __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sCommonRegs.FLTINR1) + - REG_OFFSET_TAB_FLTINR[iFault])); + REG_OFFSET_TAB_FLTINR[iFault])); SET_BIT(*pReg, (HRTIM_FLTINR1_FLT1E << REG_SHIFT_TAB_FLTxE[iFault])); } @@ -7131,11 +7141,11 @@ __STATIC_INLINE void LL_HRTIM_FLT_Enable(HRTIM_TypeDef *HRTIMx, uint32_t Fault) * @arg @ref LL_HRTIM_FAULT_5 * @retval None */ -__STATIC_INLINE void LL_HRTIM_FLT_Disable(HRTIM_TypeDef *HRTIMx, uint32_t Fault) +__STATIC_INLINE void LL_HRTIM_FLT_Disable(const HRTIM_TypeDef *HRTIMx, uint32_t Fault) { uint32_t iFault = (uint8_t)POSITION_VAL(Fault); __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sCommonRegs.FLTINR1) + - REG_OFFSET_TAB_FLTINR[iFault])); + REG_OFFSET_TAB_FLTINR[iFault])); CLEAR_BIT(*pReg, (HRTIM_FLTINR1_FLT1E << REG_SHIFT_TAB_FLTxE[iFault])); } @@ -7159,7 +7169,7 @@ __STATIC_INLINE uint32_t LL_HRTIM_FLT_IsEnabled(const HRTIM_TypeDef *HRTIMx, uin { uint32_t iFault = (uint8_t)POSITION_VAL(Fault); const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sCommonRegs.FLTINR1) + - REG_OFFSET_TAB_FLTINR[iFault])); + REG_OFFSET_TAB_FLTINR[iFault])); return (((READ_BIT(*pReg, (HRTIM_FLTINR1_FLT1E << REG_SHIFT_TAB_FLTxE[iFault])) >> REG_SHIFT_TAB_FLTxE[iFault]) == (HRTIM_IER_FLT1)) ? 1UL : 0UL); } @@ -7853,11 +7863,11 @@ __STATIC_INLINE uint32_t LL_HRTIM_IsActiveFlag_SYNC(const HRTIM_TypeDef *HRTIMx) * @arg @ref LL_HRTIM_TIMER_E * @retval None */ -__STATIC_INLINE void LL_HRTIM_ClearFlag_UPDATE(HRTIM_TypeDef *HRTIMx, uint32_t Timer) +__STATIC_INLINE void LL_HRTIM_ClearFlag_UPDATE(const HRTIM_TypeDef *HRTIMx, uint32_t Timer) { uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MICR) + - REG_OFFSET_TAB_TIMER[iTimer])); + REG_OFFSET_TAB_TIMER[iTimer])); SET_BIT(*pReg, HRTIM_MICR_MUPD); } @@ -7879,7 +7889,7 @@ __STATIC_INLINE uint32_t LL_HRTIM_IsActiveFlag_UPDATE(const HRTIM_TypeDef *HRTIM { uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MISR) + - REG_OFFSET_TAB_TIMER[iTimer])); + REG_OFFSET_TAB_TIMER[iTimer])); return ((READ_BIT(*pReg, HRTIM_MISR_MUPD) == (HRTIM_MISR_MUPD)) ? 1UL : 0UL); } @@ -7898,11 +7908,11 @@ __STATIC_INLINE uint32_t LL_HRTIM_IsActiveFlag_UPDATE(const HRTIM_TypeDef *HRTIM * @arg @ref LL_HRTIM_TIMER_E * @retval None */ -__STATIC_INLINE void LL_HRTIM_ClearFlag_REP(HRTIM_TypeDef *HRTIMx, uint32_t Timer) +__STATIC_INLINE void LL_HRTIM_ClearFlag_REP(const HRTIM_TypeDef *HRTIMx, uint32_t Timer) { uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MICR) + - REG_OFFSET_TAB_TIMER[iTimer])); + REG_OFFSET_TAB_TIMER[iTimer])); SET_BIT(*pReg, HRTIM_MICR_MREP); } @@ -7925,7 +7935,7 @@ __STATIC_INLINE uint32_t LL_HRTIM_IsActiveFlag_REP(const HRTIM_TypeDef *HRTIMx, { uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MISR) + - REG_OFFSET_TAB_TIMER[iTimer])); + REG_OFFSET_TAB_TIMER[iTimer])); return ((READ_BIT(*pReg, HRTIM_MISR_MREP) == (HRTIM_MISR_MREP)) ? 1UL : 0UL); } @@ -7944,11 +7954,11 @@ __STATIC_INLINE uint32_t LL_HRTIM_IsActiveFlag_REP(const HRTIM_TypeDef *HRTIMx, * @arg @ref LL_HRTIM_TIMER_E * @retval None */ -__STATIC_INLINE void LL_HRTIM_ClearFlag_CMP1(HRTIM_TypeDef *HRTIMx, uint32_t Timer) +__STATIC_INLINE void LL_HRTIM_ClearFlag_CMP1(const HRTIM_TypeDef *HRTIMx, uint32_t Timer) { uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MICR) + - REG_OFFSET_TAB_TIMER[iTimer])); + REG_OFFSET_TAB_TIMER[iTimer])); SET_BIT(*pReg, HRTIM_MICR_MCMP1); } @@ -7970,7 +7980,7 @@ __STATIC_INLINE uint32_t LL_HRTIM_IsActiveFlag_CMP1(const HRTIM_TypeDef *HRTIMx, { uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MISR) + - REG_OFFSET_TAB_TIMER[iTimer])); + REG_OFFSET_TAB_TIMER[iTimer])); return ((READ_BIT(*pReg, HRTIM_MISR_MCMP1) == (HRTIM_MISR_MCMP1)) ? 1UL : 0UL); } @@ -7989,11 +7999,11 @@ __STATIC_INLINE uint32_t LL_HRTIM_IsActiveFlag_CMP1(const HRTIM_TypeDef *HRTIMx, * @arg @ref LL_HRTIM_TIMER_E * @retval None */ -__STATIC_INLINE void LL_HRTIM_ClearFlag_CMP2(HRTIM_TypeDef *HRTIMx, uint32_t Timer) +__STATIC_INLINE void LL_HRTIM_ClearFlag_CMP2(const HRTIM_TypeDef *HRTIMx, uint32_t Timer) { uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MICR) + - REG_OFFSET_TAB_TIMER[iTimer])); + REG_OFFSET_TAB_TIMER[iTimer])); SET_BIT(*pReg, HRTIM_MICR_MCMP2); } @@ -8015,7 +8025,7 @@ __STATIC_INLINE uint32_t LL_HRTIM_IsActiveFlag_CMP2(const HRTIM_TypeDef *HRTIMx, { uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MISR) + - REG_OFFSET_TAB_TIMER[iTimer])); + REG_OFFSET_TAB_TIMER[iTimer])); return ((READ_BIT(*pReg, HRTIM_MISR_MCMP2) == (HRTIM_MISR_MCMP2)) ? 1UL : 0UL); } @@ -8034,11 +8044,11 @@ __STATIC_INLINE uint32_t LL_HRTIM_IsActiveFlag_CMP2(const HRTIM_TypeDef *HRTIMx, * @arg @ref LL_HRTIM_TIMER_E * @retval None */ -__STATIC_INLINE void LL_HRTIM_ClearFlag_CMP3(HRTIM_TypeDef *HRTIMx, uint32_t Timer) +__STATIC_INLINE void LL_HRTIM_ClearFlag_CMP3(const HRTIM_TypeDef *HRTIMx, uint32_t Timer) { uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MICR) + - REG_OFFSET_TAB_TIMER[iTimer])); + REG_OFFSET_TAB_TIMER[iTimer])); SET_BIT(*pReg, HRTIM_MICR_MCMP3); } @@ -8060,7 +8070,7 @@ __STATIC_INLINE uint32_t LL_HRTIM_IsActiveFlag_CMP3(const HRTIM_TypeDef *HRTIMx, { uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MISR) + - REG_OFFSET_TAB_TIMER[iTimer])); + REG_OFFSET_TAB_TIMER[iTimer])); return ((READ_BIT(*pReg, HRTIM_MISR_MCMP3) == (HRTIM_MISR_MCMP3)) ? 1UL : 0UL); } @@ -8079,11 +8089,11 @@ __STATIC_INLINE uint32_t LL_HRTIM_IsActiveFlag_CMP3(const HRTIM_TypeDef *HRTIMx, * @arg @ref LL_HRTIM_TIMER_E * @retval None */ -__STATIC_INLINE void LL_HRTIM_ClearFlag_CMP4(HRTIM_TypeDef *HRTIMx, uint32_t Timer) +__STATIC_INLINE void LL_HRTIM_ClearFlag_CMP4(const HRTIM_TypeDef *HRTIMx, uint32_t Timer) { uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MICR) + - REG_OFFSET_TAB_TIMER[iTimer])); + REG_OFFSET_TAB_TIMER[iTimer])); SET_BIT(*pReg, HRTIM_MICR_MCMP4); } @@ -8105,7 +8115,7 @@ __STATIC_INLINE uint32_t LL_HRTIM_IsActiveFlag_CMP4(const HRTIM_TypeDef *HRTIMx, { uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MISR) + - REG_OFFSET_TAB_TIMER[iTimer])); + REG_OFFSET_TAB_TIMER[iTimer])); return ((READ_BIT(*pReg, HRTIM_MISR_MCMP4) == (HRTIM_MISR_MCMP4)) ? 1UL : 0UL); } @@ -8122,11 +8132,11 @@ __STATIC_INLINE uint32_t LL_HRTIM_IsActiveFlag_CMP4(const HRTIM_TypeDef *HRTIMx, * @arg @ref LL_HRTIM_TIMER_E * @retval None */ -__STATIC_INLINE void LL_HRTIM_ClearFlag_CPT1(HRTIM_TypeDef *HRTIMx, uint32_t Timer) +__STATIC_INLINE void LL_HRTIM_ClearFlag_CPT1(const HRTIM_TypeDef *HRTIMx, uint32_t Timer) { uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MICR) + - REG_OFFSET_TAB_TIMER[iTimer])); + REG_OFFSET_TAB_TIMER[iTimer])); SET_BIT(*pReg, HRTIM_TIMICR_CPT1C); } @@ -8146,7 +8156,7 @@ __STATIC_INLINE uint32_t LL_HRTIM_IsActiveFlag_CPT1(const HRTIM_TypeDef *HRTIMx, { uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MISR) + - REG_OFFSET_TAB_TIMER[iTimer])); + REG_OFFSET_TAB_TIMER[iTimer])); return ((READ_BIT(*pReg, HRTIM_TIMISR_CPT1) == (HRTIM_TIMISR_CPT1)) ? 1UL : 0UL); } @@ -8163,11 +8173,11 @@ __STATIC_INLINE uint32_t LL_HRTIM_IsActiveFlag_CPT1(const HRTIM_TypeDef *HRTIMx, * @arg @ref LL_HRTIM_TIMER_E * @retval None */ -__STATIC_INLINE void LL_HRTIM_ClearFlag_CPT2(HRTIM_TypeDef *HRTIMx, uint32_t Timer) +__STATIC_INLINE void LL_HRTIM_ClearFlag_CPT2(const HRTIM_TypeDef *HRTIMx, uint32_t Timer) { uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MICR) + - REG_OFFSET_TAB_TIMER[iTimer])); + REG_OFFSET_TAB_TIMER[iTimer])); SET_BIT(*pReg, HRTIM_TIMICR_CPT2C); } @@ -8187,7 +8197,7 @@ __STATIC_INLINE uint32_t LL_HRTIM_IsActiveFlag_CPT2(const HRTIM_TypeDef *HRTIMx, { uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MISR) + - REG_OFFSET_TAB_TIMER[iTimer])); + REG_OFFSET_TAB_TIMER[iTimer])); return ((READ_BIT(*pReg, HRTIM_TIMISR_CPT2) == (HRTIM_TIMISR_CPT2)) ? 1UL : 0UL); } @@ -8204,11 +8214,11 @@ __STATIC_INLINE uint32_t LL_HRTIM_IsActiveFlag_CPT2(const HRTIM_TypeDef *HRTIMx, * @arg @ref LL_HRTIM_TIMER_E * @retval None */ -__STATIC_INLINE void LL_HRTIM_ClearFlag_SET1(HRTIM_TypeDef *HRTIMx, uint32_t Timer) +__STATIC_INLINE void LL_HRTIM_ClearFlag_SET1(const HRTIM_TypeDef *HRTIMx, uint32_t Timer) { uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MICR) + - REG_OFFSET_TAB_TIMER[iTimer])); + REG_OFFSET_TAB_TIMER[iTimer])); SET_BIT(*pReg, HRTIM_TIMICR_SET1C); } @@ -8228,7 +8238,7 @@ __STATIC_INLINE uint32_t LL_HRTIM_IsActiveFlag_SET1(const HRTIM_TypeDef *HRTIMx, { uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MISR) + - REG_OFFSET_TAB_TIMER[iTimer])); + REG_OFFSET_TAB_TIMER[iTimer])); return ((READ_BIT(*pReg, HRTIM_TIMISR_SET1) == (HRTIM_TIMISR_SET1)) ? 1UL : 0UL); } @@ -8245,11 +8255,11 @@ __STATIC_INLINE uint32_t LL_HRTIM_IsActiveFlag_SET1(const HRTIM_TypeDef *HRTIMx, * @arg @ref LL_HRTIM_TIMER_E * @retval None */ -__STATIC_INLINE void LL_HRTIM_ClearFlag_RST1(HRTIM_TypeDef *HRTIMx, uint32_t Timer) +__STATIC_INLINE void LL_HRTIM_ClearFlag_RST1(const HRTIM_TypeDef *HRTIMx, uint32_t Timer) { uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MICR) + - REG_OFFSET_TAB_TIMER[iTimer])); + REG_OFFSET_TAB_TIMER[iTimer])); SET_BIT(*pReg, HRTIM_TIMICR_RST1C); } @@ -8269,7 +8279,7 @@ __STATIC_INLINE uint32_t LL_HRTIM_IsActiveFlag_RST1(const HRTIM_TypeDef *HRTIMx, { uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MISR) + - REG_OFFSET_TAB_TIMER[iTimer])); + REG_OFFSET_TAB_TIMER[iTimer])); return ((READ_BIT(*pReg, HRTIM_TIMISR_RST1) == (HRTIM_TIMISR_RST1)) ? 1UL : 0UL); } @@ -8286,11 +8296,11 @@ __STATIC_INLINE uint32_t LL_HRTIM_IsActiveFlag_RST1(const HRTIM_TypeDef *HRTIMx, * @arg @ref LL_HRTIM_TIMER_E * @retval None */ -__STATIC_INLINE void LL_HRTIM_ClearFlag_SET2(HRTIM_TypeDef *HRTIMx, uint32_t Timer) +__STATIC_INLINE void LL_HRTIM_ClearFlag_SET2(const HRTIM_TypeDef *HRTIMx, uint32_t Timer) { uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MICR) + - REG_OFFSET_TAB_TIMER[iTimer])); + REG_OFFSET_TAB_TIMER[iTimer])); SET_BIT(*pReg, HRTIM_TIMICR_SET2C); } @@ -8310,7 +8320,7 @@ __STATIC_INLINE uint32_t LL_HRTIM_IsActiveFlag_SET2(const HRTIM_TypeDef *HRTIMx, { uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MISR) + - REG_OFFSET_TAB_TIMER[iTimer])); + REG_OFFSET_TAB_TIMER[iTimer])); return ((READ_BIT(*pReg, HRTIM_TIMISR_SET2) == (HRTIM_TIMISR_SET2)) ? 1UL : 0UL); } @@ -8327,11 +8337,11 @@ __STATIC_INLINE uint32_t LL_HRTIM_IsActiveFlag_SET2(const HRTIM_TypeDef *HRTIMx, * @arg @ref LL_HRTIM_TIMER_E * @retval None */ -__STATIC_INLINE void LL_HRTIM_ClearFlag_RST2(HRTIM_TypeDef *HRTIMx, uint32_t Timer) +__STATIC_INLINE void LL_HRTIM_ClearFlag_RST2(const HRTIM_TypeDef *HRTIMx, uint32_t Timer) { uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MICR) + - REG_OFFSET_TAB_TIMER[iTimer])); + REG_OFFSET_TAB_TIMER[iTimer])); SET_BIT(*pReg, HRTIM_TIMICR_RST2C); } @@ -8351,7 +8361,7 @@ __STATIC_INLINE uint32_t LL_HRTIM_IsActiveFlag_RST2(const HRTIM_TypeDef *HRTIMx, { uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MISR) + - REG_OFFSET_TAB_TIMER[iTimer])); + REG_OFFSET_TAB_TIMER[iTimer])); return ((READ_BIT(*pReg, HRTIM_TIMISR_RST2) == (HRTIM_TIMISR_RST2)) ? 1UL : 0UL); } @@ -8368,11 +8378,11 @@ __STATIC_INLINE uint32_t LL_HRTIM_IsActiveFlag_RST2(const HRTIM_TypeDef *HRTIMx, * @arg @ref LL_HRTIM_TIMER_E * @retval None */ -__STATIC_INLINE void LL_HRTIM_ClearFlag_RST(HRTIM_TypeDef *HRTIMx, uint32_t Timer) +__STATIC_INLINE void LL_HRTIM_ClearFlag_RST(const HRTIM_TypeDef *HRTIMx, uint32_t Timer) { uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MICR) + - REG_OFFSET_TAB_TIMER[iTimer])); + REG_OFFSET_TAB_TIMER[iTimer])); SET_BIT(*pReg, HRTIM_TIMICR_RSTC); } @@ -8392,7 +8402,7 @@ __STATIC_INLINE uint32_t LL_HRTIM_IsActiveFlag_RST(const HRTIM_TypeDef *HRTIMx, { uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MISR) + - REG_OFFSET_TAB_TIMER[iTimer])); + REG_OFFSET_TAB_TIMER[iTimer])); return ((READ_BIT(*pReg, HRTIM_TIMISR_RST) == (HRTIM_TIMISR_RST)) ? 1UL : 0UL); } @@ -8409,11 +8419,11 @@ __STATIC_INLINE uint32_t LL_HRTIM_IsActiveFlag_RST(const HRTIM_TypeDef *HRTIMx, * @arg @ref LL_HRTIM_TIMER_E * @retval None */ -__STATIC_INLINE void LL_HRTIM_ClearFlag_DLYPRT(HRTIM_TypeDef *HRTIMx, uint32_t Timer) +__STATIC_INLINE void LL_HRTIM_ClearFlag_DLYPRT(const HRTIM_TypeDef *HRTIMx, uint32_t Timer) { uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MICR) + - REG_OFFSET_TAB_TIMER[iTimer])); + REG_OFFSET_TAB_TIMER[iTimer])); SET_BIT(*pReg, HRTIM_TIMICR_DLYPRTC); } @@ -8433,7 +8443,7 @@ __STATIC_INLINE uint32_t LL_HRTIM_IsActiveFlag_DLYPRT(const HRTIM_TypeDef *HRTIM { uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MISR) + - REG_OFFSET_TAB_TIMER[iTimer])); + REG_OFFSET_TAB_TIMER[iTimer])); return ((READ_BIT(*pReg, HRTIM_TIMISR_DLYPRT) == (HRTIM_TIMISR_DLYPRT)) ? 1UL : 0UL); } @@ -8757,11 +8767,11 @@ __STATIC_INLINE uint32_t LL_HRTIM_IsEnabledIT_SYNC(const HRTIM_TypeDef *HRTIMx) * @arg @ref LL_HRTIM_TIMER_E * @retval None */ -__STATIC_INLINE void LL_HRTIM_EnableIT_UPDATE(HRTIM_TypeDef *HRTIMx, uint32_t Timer) +__STATIC_INLINE void LL_HRTIM_EnableIT_UPDATE(const HRTIM_TypeDef *HRTIMx, uint32_t Timer) { uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) + - REG_OFFSET_TAB_TIMER[iTimer])); + REG_OFFSET_TAB_TIMER[iTimer])); SET_BIT(*pReg, HRTIM_MDIER_MUPDIE); } @@ -8779,11 +8789,11 @@ __STATIC_INLINE void LL_HRTIM_EnableIT_UPDATE(HRTIM_TypeDef *HRTIMx, uint32_t Ti * @arg @ref LL_HRTIM_TIMER_E * @retval None */ -__STATIC_INLINE void LL_HRTIM_DisableIT_UPDATE(HRTIM_TypeDef *HRTIMx, uint32_t Timer) +__STATIC_INLINE void LL_HRTIM_DisableIT_UPDATE(const HRTIM_TypeDef *HRTIMx, uint32_t Timer) { uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) + - REG_OFFSET_TAB_TIMER[iTimer])); + REG_OFFSET_TAB_TIMER[iTimer])); CLEAR_BIT(*pReg, HRTIM_MDIER_MUPDIE); } @@ -8805,7 +8815,7 @@ __STATIC_INLINE uint32_t LL_HRTIM_IsEnabledIT_UPDATE(const HRTIM_TypeDef *HRTIMx { uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) + - REG_OFFSET_TAB_TIMER[iTimer])); + REG_OFFSET_TAB_TIMER[iTimer])); return ((READ_BIT(*pReg, HRTIM_MDIER_MUPDIE) == (HRTIM_MDIER_MUPDIE)) ? 1UL : 0UL); } @@ -8824,11 +8834,11 @@ __STATIC_INLINE uint32_t LL_HRTIM_IsEnabledIT_UPDATE(const HRTIM_TypeDef *HRTIMx * @arg @ref LL_HRTIM_TIMER_E * @retval None */ -__STATIC_INLINE void LL_HRTIM_EnableIT_REP(HRTIM_TypeDef *HRTIMx, uint32_t Timer) +__STATIC_INLINE void LL_HRTIM_EnableIT_REP(const HRTIM_TypeDef *HRTIMx, uint32_t Timer) { uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) + - REG_OFFSET_TAB_TIMER[iTimer])); + REG_OFFSET_TAB_TIMER[iTimer])); SET_BIT(*pReg, HRTIM_MDIER_MREPIE); } @@ -8846,11 +8856,11 @@ __STATIC_INLINE void LL_HRTIM_EnableIT_REP(HRTIM_TypeDef *HRTIMx, uint32_t Timer * @arg @ref LL_HRTIM_TIMER_E * @retval None */ -__STATIC_INLINE void LL_HRTIM_DisableIT_REP(HRTIM_TypeDef *HRTIMx, uint32_t Timer) +__STATIC_INLINE void LL_HRTIM_DisableIT_REP(const HRTIM_TypeDef *HRTIMx, uint32_t Timer) { uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) + - REG_OFFSET_TAB_TIMER[iTimer])); + REG_OFFSET_TAB_TIMER[iTimer])); CLEAR_BIT(*pReg, HRTIM_MDIER_MREPIE); } @@ -8872,7 +8882,7 @@ __STATIC_INLINE uint32_t LL_HRTIM_IsEnabledIT_REP(const HRTIM_TypeDef *HRTIMx, u { uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) + - REG_OFFSET_TAB_TIMER[iTimer])); + REG_OFFSET_TAB_TIMER[iTimer])); return ((READ_BIT(*pReg, HRTIM_MDIER_MREPIE) == (HRTIM_MDIER_MREPIE)) ? 1UL : 0UL); } @@ -8891,11 +8901,11 @@ __STATIC_INLINE uint32_t LL_HRTIM_IsEnabledIT_REP(const HRTIM_TypeDef *HRTIMx, u * @arg @ref LL_HRTIM_TIMER_E * @retval None */ -__STATIC_INLINE void LL_HRTIM_EnableIT_CMP1(HRTIM_TypeDef *HRTIMx, uint32_t Timer) +__STATIC_INLINE void LL_HRTIM_EnableIT_CMP1(const HRTIM_TypeDef *HRTIMx, uint32_t Timer) { uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) + - REG_OFFSET_TAB_TIMER[iTimer])); + REG_OFFSET_TAB_TIMER[iTimer])); SET_BIT(*pReg, HRTIM_MDIER_MCMP1IE); } @@ -8913,11 +8923,11 @@ __STATIC_INLINE void LL_HRTIM_EnableIT_CMP1(HRTIM_TypeDef *HRTIMx, uint32_t Time * @arg @ref LL_HRTIM_TIMER_E * @retval None */ -__STATIC_INLINE void LL_HRTIM_DisableIT_CMP1(HRTIM_TypeDef *HRTIMx, uint32_t Timer) +__STATIC_INLINE void LL_HRTIM_DisableIT_CMP1(const HRTIM_TypeDef *HRTIMx, uint32_t Timer) { uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) + - REG_OFFSET_TAB_TIMER[iTimer])); + REG_OFFSET_TAB_TIMER[iTimer])); CLEAR_BIT(*pReg, HRTIM_MDIER_MCMP1IE); } @@ -8939,7 +8949,7 @@ __STATIC_INLINE uint32_t LL_HRTIM_IsEnabledIT_CMP1(const HRTIM_TypeDef *HRTIMx, { uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) + - REG_OFFSET_TAB_TIMER[iTimer])); + REG_OFFSET_TAB_TIMER[iTimer])); return ((READ_BIT(*pReg, HRTIM_MDIER_MCMP1IE) == (HRTIM_MDIER_MCMP1IE)) ? 1UL : 0UL); } @@ -8958,11 +8968,11 @@ __STATIC_INLINE uint32_t LL_HRTIM_IsEnabledIT_CMP1(const HRTIM_TypeDef *HRTIMx, * @arg @ref LL_HRTIM_TIMER_E * @retval None */ -__STATIC_INLINE void LL_HRTIM_EnableIT_CMP2(HRTIM_TypeDef *HRTIMx, uint32_t Timer) +__STATIC_INLINE void LL_HRTIM_EnableIT_CMP2(const HRTIM_TypeDef *HRTIMx, uint32_t Timer) { uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) + - REG_OFFSET_TAB_TIMER[iTimer])); + REG_OFFSET_TAB_TIMER[iTimer])); SET_BIT(*pReg, HRTIM_MDIER_MCMP2IE); } @@ -8980,11 +8990,11 @@ __STATIC_INLINE void LL_HRTIM_EnableIT_CMP2(HRTIM_TypeDef *HRTIMx, uint32_t Time * @arg @ref LL_HRTIM_TIMER_E * @retval None */ -__STATIC_INLINE void LL_HRTIM_DisableIT_CMP2(HRTIM_TypeDef *HRTIMx, uint32_t Timer) +__STATIC_INLINE void LL_HRTIM_DisableIT_CMP2(const HRTIM_TypeDef *HRTIMx, uint32_t Timer) { uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) + - REG_OFFSET_TAB_TIMER[iTimer])); + REG_OFFSET_TAB_TIMER[iTimer])); CLEAR_BIT(*pReg, HRTIM_MDIER_MCMP2IE); } @@ -9006,7 +9016,7 @@ __STATIC_INLINE uint32_t LL_HRTIM_IsEnabledIT_CMP2(const HRTIM_TypeDef *HRTIMx, { uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) + - REG_OFFSET_TAB_TIMER[iTimer])); + REG_OFFSET_TAB_TIMER[iTimer])); return ((READ_BIT(*pReg, HRTIM_MDIER_MCMP2IE) == (HRTIM_MDIER_MCMP2IE)) ? 1UL : 0UL); } @@ -9025,11 +9035,11 @@ __STATIC_INLINE uint32_t LL_HRTIM_IsEnabledIT_CMP2(const HRTIM_TypeDef *HRTIMx, * @arg @ref LL_HRTIM_TIMER_E * @retval None */ -__STATIC_INLINE void LL_HRTIM_EnableIT_CMP3(HRTIM_TypeDef *HRTIMx, uint32_t Timer) +__STATIC_INLINE void LL_HRTIM_EnableIT_CMP3(const HRTIM_TypeDef *HRTIMx, uint32_t Timer) { uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) + - REG_OFFSET_TAB_TIMER[iTimer])); + REG_OFFSET_TAB_TIMER[iTimer])); SET_BIT(*pReg, HRTIM_MDIER_MCMP3IE); } @@ -9047,11 +9057,11 @@ __STATIC_INLINE void LL_HRTIM_EnableIT_CMP3(HRTIM_TypeDef *HRTIMx, uint32_t Time * @arg @ref LL_HRTIM_TIMER_E * @retval None */ -__STATIC_INLINE void LL_HRTIM_DisableIT_CMP3(HRTIM_TypeDef *HRTIMx, uint32_t Timer) +__STATIC_INLINE void LL_HRTIM_DisableIT_CMP3(const HRTIM_TypeDef *HRTIMx, uint32_t Timer) { uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) + - REG_OFFSET_TAB_TIMER[iTimer])); + REG_OFFSET_TAB_TIMER[iTimer])); CLEAR_BIT(*pReg, HRTIM_MDIER_MCMP3IE); } @@ -9073,7 +9083,7 @@ __STATIC_INLINE uint32_t LL_HRTIM_IsEnabledIT_CMP3(const HRTIM_TypeDef *HRTIMx, { uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) + - REG_OFFSET_TAB_TIMER[iTimer])); + REG_OFFSET_TAB_TIMER[iTimer])); return ((READ_BIT(*pReg, HRTIM_MDIER_MCMP3IE) == (HRTIM_MDIER_MCMP3IE)) ? 1UL : 0UL); } @@ -9092,11 +9102,11 @@ __STATIC_INLINE uint32_t LL_HRTIM_IsEnabledIT_CMP3(const HRTIM_TypeDef *HRTIMx, * @arg @ref LL_HRTIM_TIMER_E * @retval None */ -__STATIC_INLINE void LL_HRTIM_EnableIT_CMP4(HRTIM_TypeDef *HRTIMx, uint32_t Timer) +__STATIC_INLINE void LL_HRTIM_EnableIT_CMP4(const HRTIM_TypeDef *HRTIMx, uint32_t Timer) { uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) + - REG_OFFSET_TAB_TIMER[iTimer])); + REG_OFFSET_TAB_TIMER[iTimer])); SET_BIT(*pReg, HRTIM_MDIER_MCMP4IE); } @@ -9114,11 +9124,11 @@ __STATIC_INLINE void LL_HRTIM_EnableIT_CMP4(HRTIM_TypeDef *HRTIMx, uint32_t Time * @arg @ref LL_HRTIM_TIMER_E * @retval None */ -__STATIC_INLINE void LL_HRTIM_DisableIT_CMP4(HRTIM_TypeDef *HRTIMx, uint32_t Timer) +__STATIC_INLINE void LL_HRTIM_DisableIT_CMP4(const HRTIM_TypeDef *HRTIMx, uint32_t Timer) { uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) + - REG_OFFSET_TAB_TIMER[iTimer])); + REG_OFFSET_TAB_TIMER[iTimer])); CLEAR_BIT(*pReg, HRTIM_MDIER_MCMP4IE); } @@ -9140,7 +9150,7 @@ __STATIC_INLINE uint32_t LL_HRTIM_IsEnabledIT_CMP4(const HRTIM_TypeDef *HRTIMx, { uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) + - REG_OFFSET_TAB_TIMER[iTimer])); + REG_OFFSET_TAB_TIMER[iTimer])); return ((READ_BIT(*pReg, HRTIM_MDIER_MCMP4IE) == (HRTIM_MDIER_MCMP4IE)) ? 1UL : 0UL); } @@ -9157,11 +9167,11 @@ __STATIC_INLINE uint32_t LL_HRTIM_IsEnabledIT_CMP4(const HRTIM_TypeDef *HRTIMx, * @arg @ref LL_HRTIM_TIMER_E * @retval None */ -__STATIC_INLINE void LL_HRTIM_EnableIT_CPT1(HRTIM_TypeDef *HRTIMx, uint32_t Timer) +__STATIC_INLINE void LL_HRTIM_EnableIT_CPT1(const HRTIM_TypeDef *HRTIMx, uint32_t Timer) { uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) + - REG_OFFSET_TAB_TIMER[iTimer])); + REG_OFFSET_TAB_TIMER[iTimer])); SET_BIT(*pReg, HRTIM_TIMDIER_CPT1IE); } @@ -9177,11 +9187,11 @@ __STATIC_INLINE void LL_HRTIM_EnableIT_CPT1(HRTIM_TypeDef *HRTIMx, uint32_t Time * @arg @ref LL_HRTIM_TIMER_E * @retval None */ -__STATIC_INLINE void LL_HRTIM_DisableIT_CPT1(HRTIM_TypeDef *HRTIMx, uint32_t Timer) +__STATIC_INLINE void LL_HRTIM_DisableIT_CPT1(const HRTIM_TypeDef *HRTIMx, uint32_t Timer) { uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) + - REG_OFFSET_TAB_TIMER[iTimer])); + REG_OFFSET_TAB_TIMER[iTimer])); CLEAR_BIT(*pReg, HRTIM_TIMDIER_CPT1IE); } @@ -9201,7 +9211,7 @@ __STATIC_INLINE uint32_t LL_HRTIM_IsEnabledIT_CPT1(const HRTIM_TypeDef *HRTIMx, { uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) + - REG_OFFSET_TAB_TIMER[iTimer])); + REG_OFFSET_TAB_TIMER[iTimer])); return ((READ_BIT(*pReg, HRTIM_TIMDIER_CPT1IE) == (HRTIM_TIMDIER_CPT1IE)) ? 1UL : 0UL); } @@ -9218,11 +9228,11 @@ __STATIC_INLINE uint32_t LL_HRTIM_IsEnabledIT_CPT1(const HRTIM_TypeDef *HRTIMx, * @arg @ref LL_HRTIM_TIMER_E * @retval None */ -__STATIC_INLINE void LL_HRTIM_EnableIT_CPT2(HRTIM_TypeDef *HRTIMx, uint32_t Timer) +__STATIC_INLINE void LL_HRTIM_EnableIT_CPT2(const HRTIM_TypeDef *HRTIMx, uint32_t Timer) { uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) + - REG_OFFSET_TAB_TIMER[iTimer])); + REG_OFFSET_TAB_TIMER[iTimer])); SET_BIT(*pReg, HRTIM_TIMDIER_CPT2IE); } @@ -9238,11 +9248,11 @@ __STATIC_INLINE void LL_HRTIM_EnableIT_CPT2(HRTIM_TypeDef *HRTIMx, uint32_t Time * @arg @ref LL_HRTIM_TIMER_E * @retval None */ -__STATIC_INLINE void LL_HRTIM_DisableIT_CPT2(HRTIM_TypeDef *HRTIMx, uint32_t Timer) +__STATIC_INLINE void LL_HRTIM_DisableIT_CPT2(const HRTIM_TypeDef *HRTIMx, uint32_t Timer) { uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) + - REG_OFFSET_TAB_TIMER[iTimer])); + REG_OFFSET_TAB_TIMER[iTimer])); CLEAR_BIT(*pReg, HRTIM_TIMDIER_CPT2IE); } @@ -9262,7 +9272,7 @@ __STATIC_INLINE uint32_t LL_HRTIM_IsEnabledIT_CPT2(const HRTIM_TypeDef *HRTIMx, { uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) + - REG_OFFSET_TAB_TIMER[iTimer])); + REG_OFFSET_TAB_TIMER[iTimer])); return ((READ_BIT(*pReg, HRTIM_TIMDIER_CPT2IE) == (HRTIM_TIMDIER_CPT2IE)) ? 1UL : 0UL); } @@ -9279,11 +9289,11 @@ __STATIC_INLINE uint32_t LL_HRTIM_IsEnabledIT_CPT2(const HRTIM_TypeDef *HRTIMx, * @arg @ref LL_HRTIM_TIMER_E * @retval None */ -__STATIC_INLINE void LL_HRTIM_EnableIT_SET1(HRTIM_TypeDef *HRTIMx, uint32_t Timer) +__STATIC_INLINE void LL_HRTIM_EnableIT_SET1(const HRTIM_TypeDef *HRTIMx, uint32_t Timer) { uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) + - REG_OFFSET_TAB_TIMER[iTimer])); + REG_OFFSET_TAB_TIMER[iTimer])); SET_BIT(*pReg, HRTIM_TIMDIER_SET1IE); } @@ -9299,11 +9309,11 @@ __STATIC_INLINE void LL_HRTIM_EnableIT_SET1(HRTIM_TypeDef *HRTIMx, uint32_t Time * @arg @ref LL_HRTIM_TIMER_E * @retval None */ -__STATIC_INLINE void LL_HRTIM_DisableIT_SET1(HRTIM_TypeDef *HRTIMx, uint32_t Timer) +__STATIC_INLINE void LL_HRTIM_DisableIT_SET1(const HRTIM_TypeDef *HRTIMx, uint32_t Timer) { uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) + - REG_OFFSET_TAB_TIMER[iTimer])); + REG_OFFSET_TAB_TIMER[iTimer])); CLEAR_BIT(*pReg, HRTIM_TIMDIER_SET1IE); } @@ -9323,7 +9333,7 @@ __STATIC_INLINE uint32_t LL_HRTIM_IsEnabledIT_SET1(const HRTIM_TypeDef *HRTIMx, { uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) + - REG_OFFSET_TAB_TIMER[iTimer])); + REG_OFFSET_TAB_TIMER[iTimer])); return ((READ_BIT(*pReg, HRTIM_TIMDIER_SET1IE) == (HRTIM_TIMDIER_SET1IE)) ? 1UL : 0UL); } @@ -9340,11 +9350,11 @@ __STATIC_INLINE uint32_t LL_HRTIM_IsEnabledIT_SET1(const HRTIM_TypeDef *HRTIMx, * @arg @ref LL_HRTIM_TIMER_E * @retval None */ -__STATIC_INLINE void LL_HRTIM_EnableIT_RST1(HRTIM_TypeDef *HRTIMx, uint32_t Timer) +__STATIC_INLINE void LL_HRTIM_EnableIT_RST1(const HRTIM_TypeDef *HRTIMx, uint32_t Timer) { uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) + - REG_OFFSET_TAB_TIMER[iTimer])); + REG_OFFSET_TAB_TIMER[iTimer])); SET_BIT(*pReg, HRTIM_TIMDIER_RST1IE); } @@ -9360,11 +9370,11 @@ __STATIC_INLINE void LL_HRTIM_EnableIT_RST1(HRTIM_TypeDef *HRTIMx, uint32_t Time * @arg @ref LL_HRTIM_TIMER_E * @retval None */ -__STATIC_INLINE void LL_HRTIM_DisableIT_RST1(HRTIM_TypeDef *HRTIMx, uint32_t Timer) +__STATIC_INLINE void LL_HRTIM_DisableIT_RST1(const HRTIM_TypeDef *HRTIMx, uint32_t Timer) { uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) + - REG_OFFSET_TAB_TIMER[iTimer])); + REG_OFFSET_TAB_TIMER[iTimer])); CLEAR_BIT(*pReg, HRTIM_TIMDIER_RST1IE); } @@ -9384,7 +9394,7 @@ __STATIC_INLINE uint32_t LL_HRTIM_IsEnabledIT_RST1(const HRTIM_TypeDef *HRTIMx, { uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) + - REG_OFFSET_TAB_TIMER[iTimer])); + REG_OFFSET_TAB_TIMER[iTimer])); return ((READ_BIT(*pReg, HRTIM_TIMDIER_RST1IE) == (HRTIM_TIMDIER_RST1IE)) ? 1UL : 0UL); } @@ -9401,11 +9411,11 @@ __STATIC_INLINE uint32_t LL_HRTIM_IsEnabledIT_RST1(const HRTIM_TypeDef *HRTIMx, * @arg @ref LL_HRTIM_TIMER_E * @retval None */ -__STATIC_INLINE void LL_HRTIM_EnableIT_SET2(HRTIM_TypeDef *HRTIMx, uint32_t Timer) +__STATIC_INLINE void LL_HRTIM_EnableIT_SET2(const HRTIM_TypeDef *HRTIMx, uint32_t Timer) { uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) + - REG_OFFSET_TAB_TIMER[iTimer])); + REG_OFFSET_TAB_TIMER[iTimer])); SET_BIT(*pReg, HRTIM_TIMDIER_SET2IE); } @@ -9421,11 +9431,11 @@ __STATIC_INLINE void LL_HRTIM_EnableIT_SET2(HRTIM_TypeDef *HRTIMx, uint32_t Time * @arg @ref LL_HRTIM_TIMER_E * @retval None */ -__STATIC_INLINE void LL_HRTIM_DisableIT_SET2(HRTIM_TypeDef *HRTIMx, uint32_t Timer) +__STATIC_INLINE void LL_HRTIM_DisableIT_SET2(const HRTIM_TypeDef *HRTIMx, uint32_t Timer) { uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) + - REG_OFFSET_TAB_TIMER[iTimer])); + REG_OFFSET_TAB_TIMER[iTimer])); CLEAR_BIT(*pReg, HRTIM_TIMDIER_SET2IE); } @@ -9445,7 +9455,7 @@ __STATIC_INLINE uint32_t LL_HRTIM_IsEnabledIT_SET2(const HRTIM_TypeDef *HRTIMx, { uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) + - REG_OFFSET_TAB_TIMER[iTimer])); + REG_OFFSET_TAB_TIMER[iTimer])); return ((READ_BIT(*pReg, HRTIM_TIMDIER_SET2IE) == (HRTIM_TIMDIER_SET2IE)) ? 1UL : 0UL); } @@ -9462,11 +9472,11 @@ __STATIC_INLINE uint32_t LL_HRTIM_IsEnabledIT_SET2(const HRTIM_TypeDef *HRTIMx, * @arg @ref LL_HRTIM_TIMER_E * @retval None */ -__STATIC_INLINE void LL_HRTIM_EnableIT_RST2(HRTIM_TypeDef *HRTIMx, uint32_t Timer) +__STATIC_INLINE void LL_HRTIM_EnableIT_RST2(const HRTIM_TypeDef *HRTIMx, uint32_t Timer) { uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) + - REG_OFFSET_TAB_TIMER[iTimer])); + REG_OFFSET_TAB_TIMER[iTimer])); SET_BIT(*pReg, HRTIM_TIMDIER_RST2IE); } @@ -9482,11 +9492,11 @@ __STATIC_INLINE void LL_HRTIM_EnableIT_RST2(HRTIM_TypeDef *HRTIMx, uint32_t Time * @arg @ref LL_HRTIM_TIMER_E * @retval None */ -__STATIC_INLINE void LL_HRTIM_DisableIT_RST2(HRTIM_TypeDef *HRTIMx, uint32_t Timer) +__STATIC_INLINE void LL_HRTIM_DisableIT_RST2(const HRTIM_TypeDef *HRTIMx, uint32_t Timer) { uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) + - REG_OFFSET_TAB_TIMER[iTimer])); + REG_OFFSET_TAB_TIMER[iTimer])); CLEAR_BIT(*pReg, HRTIM_TIMDIER_RST2IE); } @@ -9506,7 +9516,7 @@ __STATIC_INLINE uint32_t LL_HRTIM_IsEnabledIT_RST2(const HRTIM_TypeDef *HRTIMx, { uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) + - REG_OFFSET_TAB_TIMER[iTimer])); + REG_OFFSET_TAB_TIMER[iTimer])); return ((READ_BIT(*pReg, HRTIM_TIMDIER_RST2IE) == (HRTIM_TIMDIER_RST2IE)) ? 1UL : 0UL); } @@ -9523,11 +9533,11 @@ __STATIC_INLINE uint32_t LL_HRTIM_IsEnabledIT_RST2(const HRTIM_TypeDef *HRTIMx, * @arg @ref LL_HRTIM_TIMER_E * @retval None */ -__STATIC_INLINE void LL_HRTIM_EnableIT_RST(HRTIM_TypeDef *HRTIMx, uint32_t Timer) +__STATIC_INLINE void LL_HRTIM_EnableIT_RST(const HRTIM_TypeDef *HRTIMx, uint32_t Timer) { uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) + - REG_OFFSET_TAB_TIMER[iTimer])); + REG_OFFSET_TAB_TIMER[iTimer])); SET_BIT(*pReg, HRTIM_TIMDIER_RSTIE); } @@ -9543,11 +9553,11 @@ __STATIC_INLINE void LL_HRTIM_EnableIT_RST(HRTIM_TypeDef *HRTIMx, uint32_t Timer * @arg @ref LL_HRTIM_TIMER_E * @retval None */ -__STATIC_INLINE void LL_HRTIM_DisableIT_RST(HRTIM_TypeDef *HRTIMx, uint32_t Timer) +__STATIC_INLINE void LL_HRTIM_DisableIT_RST(const HRTIM_TypeDef *HRTIMx, uint32_t Timer) { uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) + - REG_OFFSET_TAB_TIMER[iTimer])); + REG_OFFSET_TAB_TIMER[iTimer])); CLEAR_BIT(*pReg, HRTIM_TIMDIER_RSTIE); } @@ -9567,7 +9577,7 @@ __STATIC_INLINE uint32_t LL_HRTIM_IsEnabledIT_RST(const HRTIM_TypeDef *HRTIMx, u { uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) + - REG_OFFSET_TAB_TIMER[iTimer])); + REG_OFFSET_TAB_TIMER[iTimer])); return ((READ_BIT(*pReg, HRTIM_TIMDIER_RSTIE) == (HRTIM_TIMDIER_RSTIE)) ? 1UL : 0UL); } @@ -9584,11 +9594,11 @@ __STATIC_INLINE uint32_t LL_HRTIM_IsEnabledIT_RST(const HRTIM_TypeDef *HRTIMx, u * @arg @ref LL_HRTIM_TIMER_E * @retval None */ -__STATIC_INLINE void LL_HRTIM_EnableIT_DLYPRT(HRTIM_TypeDef *HRTIMx, uint32_t Timer) +__STATIC_INLINE void LL_HRTIM_EnableIT_DLYPRT(const HRTIM_TypeDef *HRTIMx, uint32_t Timer) { uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) + - REG_OFFSET_TAB_TIMER[iTimer])); + REG_OFFSET_TAB_TIMER[iTimer])); SET_BIT(*pReg, HRTIM_TIMDIER_DLYPRTIE); } @@ -9604,11 +9614,11 @@ __STATIC_INLINE void LL_HRTIM_EnableIT_DLYPRT(HRTIM_TypeDef *HRTIMx, uint32_t Ti * @arg @ref LL_HRTIM_TIMER_E * @retval None */ -__STATIC_INLINE void LL_HRTIM_DisableIT_DLYPRT(HRTIM_TypeDef *HRTIMx, uint32_t Timer) +__STATIC_INLINE void LL_HRTIM_DisableIT_DLYPRT(const HRTIM_TypeDef *HRTIMx, uint32_t Timer) { uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) + - REG_OFFSET_TAB_TIMER[iTimer])); + REG_OFFSET_TAB_TIMER[iTimer])); CLEAR_BIT(*pReg, HRTIM_TIMDIER_DLYPRTIE); } @@ -9628,7 +9638,7 @@ __STATIC_INLINE uint32_t LL_HRTIM_IsEnabledIT_DLYPRT(const HRTIM_TypeDef *HRTIMx { uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) + - REG_OFFSET_TAB_TIMER[iTimer])); + REG_OFFSET_TAB_TIMER[iTimer])); return ((READ_BIT(*pReg, HRTIM_TIMDIER_DLYPRTIE) == (HRTIM_TIMDIER_DLYPRTIE)) ? 1UL : 0UL); } @@ -9688,11 +9698,11 @@ __STATIC_INLINE uint32_t LL_HRTIM_IsEnabledDMAReq_SYNC(const HRTIM_TypeDef *HRTI * @arg @ref LL_HRTIM_TIMER_E * @retval None */ -__STATIC_INLINE void LL_HRTIM_EnableDMAReq_UPDATE(HRTIM_TypeDef *HRTIMx, uint32_t Timer) +__STATIC_INLINE void LL_HRTIM_EnableDMAReq_UPDATE(const HRTIM_TypeDef *HRTIMx, uint32_t Timer) { uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) + - REG_OFFSET_TAB_TIMER[iTimer])); + REG_OFFSET_TAB_TIMER[iTimer])); SET_BIT(*pReg, HRTIM_MDIER_MUPDDE); } @@ -9710,11 +9720,11 @@ __STATIC_INLINE void LL_HRTIM_EnableDMAReq_UPDATE(HRTIM_TypeDef *HRTIMx, uint32_ * @arg @ref LL_HRTIM_TIMER_E * @retval None */ -__STATIC_INLINE void LL_HRTIM_DisableDMAReq_UPDATE(HRTIM_TypeDef *HRTIMx, uint32_t Timer) +__STATIC_INLINE void LL_HRTIM_DisableDMAReq_UPDATE(const HRTIM_TypeDef *HRTIMx, uint32_t Timer) { uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) + - REG_OFFSET_TAB_TIMER[iTimer])); + REG_OFFSET_TAB_TIMER[iTimer])); CLEAR_BIT(*pReg, HRTIM_MDIER_MUPDDE); } @@ -9736,7 +9746,7 @@ __STATIC_INLINE uint32_t LL_HRTIM_IsEnabledDMAReq_UPDATE(const HRTIM_TypeDef *HR { uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) + - REG_OFFSET_TAB_TIMER[iTimer])); + REG_OFFSET_TAB_TIMER[iTimer])); return ((READ_BIT(*pReg, HRTIM_MDIER_MUPDDE) == (HRTIM_MDIER_MUPDDE)) ? 1UL : 0UL); } @@ -9755,11 +9765,11 @@ __STATIC_INLINE uint32_t LL_HRTIM_IsEnabledDMAReq_UPDATE(const HRTIM_TypeDef *HR * @arg @ref LL_HRTIM_TIMER_E * @retval None */ -__STATIC_INLINE void LL_HRTIM_EnableDMAReq_REP(HRTIM_TypeDef *HRTIMx, uint32_t Timer) +__STATIC_INLINE void LL_HRTIM_EnableDMAReq_REP(const HRTIM_TypeDef *HRTIMx, uint32_t Timer) { uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) + - REG_OFFSET_TAB_TIMER[iTimer])); + REG_OFFSET_TAB_TIMER[iTimer])); SET_BIT(*pReg, HRTIM_MDIER_MREPDE); } @@ -9777,11 +9787,11 @@ __STATIC_INLINE void LL_HRTIM_EnableDMAReq_REP(HRTIM_TypeDef *HRTIMx, uint32_t T * @arg @ref LL_HRTIM_TIMER_E * @retval None */ -__STATIC_INLINE void LL_HRTIM_DisableDMAReq_REP(HRTIM_TypeDef *HRTIMx, uint32_t Timer) +__STATIC_INLINE void LL_HRTIM_DisableDMAReq_REP(const HRTIM_TypeDef *HRTIMx, uint32_t Timer) { uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) + - REG_OFFSET_TAB_TIMER[iTimer])); + REG_OFFSET_TAB_TIMER[iTimer])); CLEAR_BIT(*pReg, HRTIM_MDIER_MREPDE); } @@ -9803,7 +9813,7 @@ __STATIC_INLINE uint32_t LL_HRTIM_IsEnabledDMAReq_REP(const HRTIM_TypeDef *HRTIM { uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) + - REG_OFFSET_TAB_TIMER[iTimer])); + REG_OFFSET_TAB_TIMER[iTimer])); return ((READ_BIT(*pReg, HRTIM_MDIER_MREPDE) == (HRTIM_MDIER_MREPDE)) ? 1UL : 0UL); } @@ -9822,11 +9832,11 @@ __STATIC_INLINE uint32_t LL_HRTIM_IsEnabledDMAReq_REP(const HRTIM_TypeDef *HRTIM * @arg @ref LL_HRTIM_TIMER_E * @retval None */ -__STATIC_INLINE void LL_HRTIM_EnableDMAReq_CMP1(HRTIM_TypeDef *HRTIMx, uint32_t Timer) +__STATIC_INLINE void LL_HRTIM_EnableDMAReq_CMP1(const HRTIM_TypeDef *HRTIMx, uint32_t Timer) { uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) + - REG_OFFSET_TAB_TIMER[iTimer])); + REG_OFFSET_TAB_TIMER[iTimer])); SET_BIT(*pReg, HRTIM_MDIER_MCMP1DE); } @@ -9844,11 +9854,11 @@ __STATIC_INLINE void LL_HRTIM_EnableDMAReq_CMP1(HRTIM_TypeDef *HRTIMx, uint32_t * @arg @ref LL_HRTIM_TIMER_E * @retval None */ -__STATIC_INLINE void LL_HRTIM_DisableDMAReq_CMP1(HRTIM_TypeDef *HRTIMx, uint32_t Timer) +__STATIC_INLINE void LL_HRTIM_DisableDMAReq_CMP1(const HRTIM_TypeDef *HRTIMx, uint32_t Timer) { uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) + - REG_OFFSET_TAB_TIMER[iTimer])); + REG_OFFSET_TAB_TIMER[iTimer])); CLEAR_BIT(*pReg, HRTIM_MDIER_MCMP1DE); } @@ -9870,7 +9880,7 @@ __STATIC_INLINE uint32_t LL_HRTIM_IsEnabledDMAReq_CMP1(const HRTIM_TypeDef *HRTI { uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) + - REG_OFFSET_TAB_TIMER[iTimer])); + REG_OFFSET_TAB_TIMER[iTimer])); return ((READ_BIT(*pReg, HRTIM_MDIER_MCMP1DE) == (HRTIM_MDIER_MCMP1DE)) ? 1UL : 0UL); } @@ -9889,11 +9899,11 @@ __STATIC_INLINE uint32_t LL_HRTIM_IsEnabledDMAReq_CMP1(const HRTIM_TypeDef *HRTI * @arg @ref LL_HRTIM_TIMER_E * @retval None */ -__STATIC_INLINE void LL_HRTIM_EnableDMAReq_CMP2(HRTIM_TypeDef *HRTIMx, uint32_t Timer) +__STATIC_INLINE void LL_HRTIM_EnableDMAReq_CMP2(const HRTIM_TypeDef *HRTIMx, uint32_t Timer) { uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) + - REG_OFFSET_TAB_TIMER[iTimer])); + REG_OFFSET_TAB_TIMER[iTimer])); SET_BIT(*pReg, HRTIM_MDIER_MCMP2DE); } @@ -9911,11 +9921,11 @@ __STATIC_INLINE void LL_HRTIM_EnableDMAReq_CMP2(HRTIM_TypeDef *HRTIMx, uint32_t * @arg @ref LL_HRTIM_TIMER_E * @retval None */ -__STATIC_INLINE void LL_HRTIM_DisableDMAReq_CMP2(HRTIM_TypeDef *HRTIMx, uint32_t Timer) +__STATIC_INLINE void LL_HRTIM_DisableDMAReq_CMP2(const HRTIM_TypeDef *HRTIMx, uint32_t Timer) { uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) + - REG_OFFSET_TAB_TIMER[iTimer])); + REG_OFFSET_TAB_TIMER[iTimer])); CLEAR_BIT(*pReg, HRTIM_MDIER_MCMP2DE); } @@ -9937,7 +9947,7 @@ __STATIC_INLINE uint32_t LL_HRTIM_IsEnabledDMAReq_CMP2(const HRTIM_TypeDef *HRTI { uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) + - REG_OFFSET_TAB_TIMER[iTimer])); + REG_OFFSET_TAB_TIMER[iTimer])); return ((READ_BIT(*pReg, HRTIM_MDIER_MCMP2DE) == (HRTIM_MDIER_MCMP2DE)) ? 1UL : 0UL); } @@ -9956,11 +9966,11 @@ __STATIC_INLINE uint32_t LL_HRTIM_IsEnabledDMAReq_CMP2(const HRTIM_TypeDef *HRTI * @arg @ref LL_HRTIM_TIMER_E * @retval None */ -__STATIC_INLINE void LL_HRTIM_EnableDMAReq_CMP3(HRTIM_TypeDef *HRTIMx, uint32_t Timer) +__STATIC_INLINE void LL_HRTIM_EnableDMAReq_CMP3(const HRTIM_TypeDef *HRTIMx, uint32_t Timer) { uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) + - REG_OFFSET_TAB_TIMER[iTimer])); + REG_OFFSET_TAB_TIMER[iTimer])); SET_BIT(*pReg, HRTIM_MDIER_MCMP3DE); } @@ -9978,11 +9988,11 @@ __STATIC_INLINE void LL_HRTIM_EnableDMAReq_CMP3(HRTIM_TypeDef *HRTIMx, uint32_t * @arg @ref LL_HRTIM_TIMER_E * @retval None */ -__STATIC_INLINE void LL_HRTIM_DisableDMAReq_CMP3(HRTIM_TypeDef *HRTIMx, uint32_t Timer) +__STATIC_INLINE void LL_HRTIM_DisableDMAReq_CMP3(const HRTIM_TypeDef *HRTIMx, uint32_t Timer) { uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) + - REG_OFFSET_TAB_TIMER[iTimer])); + REG_OFFSET_TAB_TIMER[iTimer])); CLEAR_BIT(*pReg, HRTIM_MDIER_MCMP3DE); } @@ -10004,7 +10014,7 @@ __STATIC_INLINE uint32_t LL_HRTIM_IsEnabledDMAReq_CMP3(const HRTIM_TypeDef *HRTI { uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) + - REG_OFFSET_TAB_TIMER[iTimer])); + REG_OFFSET_TAB_TIMER[iTimer])); return ((READ_BIT(*pReg, HRTIM_MDIER_MCMP3DE) == (HRTIM_MDIER_MCMP3DE)) ? 1UL : 0UL); } @@ -10023,11 +10033,11 @@ __STATIC_INLINE uint32_t LL_HRTIM_IsEnabledDMAReq_CMP3(const HRTIM_TypeDef *HRTI * @arg @ref LL_HRTIM_TIMER_E * @retval None */ -__STATIC_INLINE void LL_HRTIM_EnableDMAReq_CMP4(HRTIM_TypeDef *HRTIMx, uint32_t Timer) +__STATIC_INLINE void LL_HRTIM_EnableDMAReq_CMP4(const HRTIM_TypeDef *HRTIMx, uint32_t Timer) { uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) + - REG_OFFSET_TAB_TIMER[iTimer])); + REG_OFFSET_TAB_TIMER[iTimer])); SET_BIT(*pReg, HRTIM_MDIER_MCMP4DE); } @@ -10045,11 +10055,11 @@ __STATIC_INLINE void LL_HRTIM_EnableDMAReq_CMP4(HRTIM_TypeDef *HRTIMx, uint32_t * @arg @ref LL_HRTIM_TIMER_E * @retval None */ -__STATIC_INLINE void LL_HRTIM_DisableDMAReq_CMP4(HRTIM_TypeDef *HRTIMx, uint32_t Timer) +__STATIC_INLINE void LL_HRTIM_DisableDMAReq_CMP4(const HRTIM_TypeDef *HRTIMx, uint32_t Timer) { uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) + - REG_OFFSET_TAB_TIMER[iTimer])); + REG_OFFSET_TAB_TIMER[iTimer])); CLEAR_BIT(*pReg, HRTIM_MDIER_MCMP4DE); } @@ -10071,7 +10081,7 @@ __STATIC_INLINE uint32_t LL_HRTIM_IsEnabledDMAReq_CMP4(const HRTIM_TypeDef *HRTI { uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) + - REG_OFFSET_TAB_TIMER[iTimer])); + REG_OFFSET_TAB_TIMER[iTimer])); return ((READ_BIT(*pReg, HRTIM_MDIER_MCMP4DE) == (HRTIM_MDIER_MCMP4DE)) ? 1UL : 0UL); } @@ -10088,11 +10098,11 @@ __STATIC_INLINE uint32_t LL_HRTIM_IsEnabledDMAReq_CMP4(const HRTIM_TypeDef *HRTI * @arg @ref LL_HRTIM_TIMER_E * @retval None */ -__STATIC_INLINE void LL_HRTIM_EnableDMAReq_CPT1(HRTIM_TypeDef *HRTIMx, uint32_t Timer) +__STATIC_INLINE void LL_HRTIM_EnableDMAReq_CPT1(const HRTIM_TypeDef *HRTIMx, uint32_t Timer) { uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) + - REG_OFFSET_TAB_TIMER[iTimer])); + REG_OFFSET_TAB_TIMER[iTimer])); SET_BIT(*pReg, HRTIM_TIMDIER_CPT1DE); } @@ -10108,11 +10118,11 @@ __STATIC_INLINE void LL_HRTIM_EnableDMAReq_CPT1(HRTIM_TypeDef *HRTIMx, uint32_t * @arg @ref LL_HRTIM_TIMER_E * @retval None */ -__STATIC_INLINE void LL_HRTIM_DisableDMAReq_CPT1(HRTIM_TypeDef *HRTIMx, uint32_t Timer) +__STATIC_INLINE void LL_HRTIM_DisableDMAReq_CPT1(const HRTIM_TypeDef *HRTIMx, uint32_t Timer) { uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) + - REG_OFFSET_TAB_TIMER[iTimer])); + REG_OFFSET_TAB_TIMER[iTimer])); CLEAR_BIT(*pReg, HRTIM_TIMDIER_CPT1DE); } @@ -10132,7 +10142,7 @@ __STATIC_INLINE uint32_t LL_HRTIM_IsEnabledDMAReq_CPT1(const HRTIM_TypeDef *HRTI { uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) + - REG_OFFSET_TAB_TIMER[iTimer])); + REG_OFFSET_TAB_TIMER[iTimer])); return ((READ_BIT(*pReg, HRTIM_TIMDIER_CPT1DE) == (HRTIM_TIMDIER_CPT1DE)) ? 1UL : 0UL); } @@ -10149,11 +10159,11 @@ __STATIC_INLINE uint32_t LL_HRTIM_IsEnabledDMAReq_CPT1(const HRTIM_TypeDef *HRTI * @arg @ref LL_HRTIM_TIMER_E * @retval None */ -__STATIC_INLINE void LL_HRTIM_EnableDMAReq_CPT2(HRTIM_TypeDef *HRTIMx, uint32_t Timer) +__STATIC_INLINE void LL_HRTIM_EnableDMAReq_CPT2(const HRTIM_TypeDef *HRTIMx, uint32_t Timer) { uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) + - REG_OFFSET_TAB_TIMER[iTimer])); + REG_OFFSET_TAB_TIMER[iTimer])); SET_BIT(*pReg, HRTIM_TIMDIER_CPT2DE); } @@ -10169,11 +10179,11 @@ __STATIC_INLINE void LL_HRTIM_EnableDMAReq_CPT2(HRTIM_TypeDef *HRTIMx, uint32_t * @arg @ref LL_HRTIM_TIMER_E * @retval None */ -__STATIC_INLINE void LL_HRTIM_DisableDMAReq_CPT2(HRTIM_TypeDef *HRTIMx, uint32_t Timer) +__STATIC_INLINE void LL_HRTIM_DisableDMAReq_CPT2(const HRTIM_TypeDef *HRTIMx, uint32_t Timer) { uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) + - REG_OFFSET_TAB_TIMER[iTimer])); + REG_OFFSET_TAB_TIMER[iTimer])); CLEAR_BIT(*pReg, HRTIM_TIMDIER_CPT2DE); } @@ -10193,7 +10203,7 @@ __STATIC_INLINE uint32_t LL_HRTIM_IsEnabledDMAReq_CPT2(const HRTIM_TypeDef *HRTI { uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) + - REG_OFFSET_TAB_TIMER[iTimer])); + REG_OFFSET_TAB_TIMER[iTimer])); return ((READ_BIT(*pReg, HRTIM_TIMDIER_CPT2DE) == (HRTIM_TIMDIER_CPT2DE)) ? 1UL : 0UL); } @@ -10210,11 +10220,11 @@ __STATIC_INLINE uint32_t LL_HRTIM_IsEnabledDMAReq_CPT2(const HRTIM_TypeDef *HRTI * @arg @ref LL_HRTIM_TIMER_E * @retval None */ -__STATIC_INLINE void LL_HRTIM_EnableDMAReq_SET1(HRTIM_TypeDef *HRTIMx, uint32_t Timer) +__STATIC_INLINE void LL_HRTIM_EnableDMAReq_SET1(const HRTIM_TypeDef *HRTIMx, uint32_t Timer) { uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) + - REG_OFFSET_TAB_TIMER[iTimer])); + REG_OFFSET_TAB_TIMER[iTimer])); SET_BIT(*pReg, HRTIM_TIMDIER_SET1DE); } @@ -10230,11 +10240,11 @@ __STATIC_INLINE void LL_HRTIM_EnableDMAReq_SET1(HRTIM_TypeDef *HRTIMx, uint32_t * @arg @ref LL_HRTIM_TIMER_E * @retval None */ -__STATIC_INLINE void LL_HRTIM_DisableDMAReq_SET1(HRTIM_TypeDef *HRTIMx, uint32_t Timer) +__STATIC_INLINE void LL_HRTIM_DisableDMAReq_SET1(const HRTIM_TypeDef *HRTIMx, uint32_t Timer) { uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) + - REG_OFFSET_TAB_TIMER[iTimer])); + REG_OFFSET_TAB_TIMER[iTimer])); CLEAR_BIT(*pReg, HRTIM_TIMDIER_SET1DE); } @@ -10254,7 +10264,7 @@ __STATIC_INLINE uint32_t LL_HRTIM_IsEnabledDMAReq_SET1(const HRTIM_TypeDef *HRTI { uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) + - REG_OFFSET_TAB_TIMER[iTimer])); + REG_OFFSET_TAB_TIMER[iTimer])); return ((READ_BIT(*pReg, HRTIM_TIMDIER_SET1DE) == (HRTIM_TIMDIER_SET1DE)) ? 1UL : 0UL); } @@ -10271,11 +10281,11 @@ __STATIC_INLINE uint32_t LL_HRTIM_IsEnabledDMAReq_SET1(const HRTIM_TypeDef *HRTI * @arg @ref LL_HRTIM_TIMER_E * @retval None */ -__STATIC_INLINE void LL_HRTIM_EnableDMAReq_RST1(HRTIM_TypeDef *HRTIMx, uint32_t Timer) +__STATIC_INLINE void LL_HRTIM_EnableDMAReq_RST1(const HRTIM_TypeDef *HRTIMx, uint32_t Timer) { uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) + - REG_OFFSET_TAB_TIMER[iTimer])); + REG_OFFSET_TAB_TIMER[iTimer])); SET_BIT(*pReg, HRTIM_TIMDIER_RST1DE); } @@ -10291,11 +10301,11 @@ __STATIC_INLINE void LL_HRTIM_EnableDMAReq_RST1(HRTIM_TypeDef *HRTIMx, uint32_t * @arg @ref LL_HRTIM_TIMER_E * @retval None */ -__STATIC_INLINE void LL_HRTIM_DisableDMAReq_RST1(HRTIM_TypeDef *HRTIMx, uint32_t Timer) +__STATIC_INLINE void LL_HRTIM_DisableDMAReq_RST1(const HRTIM_TypeDef *HRTIMx, uint32_t Timer) { uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) + - REG_OFFSET_TAB_TIMER[iTimer])); + REG_OFFSET_TAB_TIMER[iTimer])); CLEAR_BIT(*pReg, HRTIM_TIMDIER_RST1DE); } @@ -10315,7 +10325,7 @@ __STATIC_INLINE uint32_t LL_HRTIM_IsEnabledDMAReq_RST1(const HRTIM_TypeDef *HRTI { uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) + - REG_OFFSET_TAB_TIMER[iTimer])); + REG_OFFSET_TAB_TIMER[iTimer])); return ((READ_BIT(*pReg, HRTIM_TIMDIER_RST1DE) == (HRTIM_TIMDIER_RST1DE)) ? 1UL : 0UL); } @@ -10332,11 +10342,11 @@ __STATIC_INLINE uint32_t LL_HRTIM_IsEnabledDMAReq_RST1(const HRTIM_TypeDef *HRTI * @arg @ref LL_HRTIM_TIMER_E * @retval None */ -__STATIC_INLINE void LL_HRTIM_EnableDMAReq_SET2(HRTIM_TypeDef *HRTIMx, uint32_t Timer) +__STATIC_INLINE void LL_HRTIM_EnableDMAReq_SET2(const HRTIM_TypeDef *HRTIMx, uint32_t Timer) { uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) + - REG_OFFSET_TAB_TIMER[iTimer])); + REG_OFFSET_TAB_TIMER[iTimer])); SET_BIT(*pReg, HRTIM_TIMDIER_SET2DE); } @@ -10352,11 +10362,11 @@ __STATIC_INLINE void LL_HRTIM_EnableDMAReq_SET2(HRTIM_TypeDef *HRTIMx, uint32_t * @arg @ref LL_HRTIM_TIMER_E * @retval None */ -__STATIC_INLINE void LL_HRTIM_DisableDMAReq_SET2(HRTIM_TypeDef *HRTIMx, uint32_t Timer) +__STATIC_INLINE void LL_HRTIM_DisableDMAReq_SET2(const HRTIM_TypeDef *HRTIMx, uint32_t Timer) { uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) + - REG_OFFSET_TAB_TIMER[iTimer])); + REG_OFFSET_TAB_TIMER[iTimer])); CLEAR_BIT(*pReg, HRTIM_TIMDIER_SET2DE); } @@ -10376,7 +10386,7 @@ __STATIC_INLINE uint32_t LL_HRTIM_IsEnabledDMAReq_SET2(const HRTIM_TypeDef *HRTI { uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) + - REG_OFFSET_TAB_TIMER[iTimer])); + REG_OFFSET_TAB_TIMER[iTimer])); return ((READ_BIT(*pReg, HRTIM_TIMDIER_SET2DE) == (HRTIM_TIMDIER_SET2DE)) ? 1UL : 0UL); } @@ -10393,11 +10403,11 @@ __STATIC_INLINE uint32_t LL_HRTIM_IsEnabledDMAReq_SET2(const HRTIM_TypeDef *HRTI * @arg @ref LL_HRTIM_TIMER_E * @retval None */ -__STATIC_INLINE void LL_HRTIM_EnableDMAReq_RST2(HRTIM_TypeDef *HRTIMx, uint32_t Timer) +__STATIC_INLINE void LL_HRTIM_EnableDMAReq_RST2(const HRTIM_TypeDef *HRTIMx, uint32_t Timer) { uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) + - REG_OFFSET_TAB_TIMER[iTimer])); + REG_OFFSET_TAB_TIMER[iTimer])); SET_BIT(*pReg, HRTIM_TIMDIER_RST2DE); } @@ -10413,11 +10423,11 @@ __STATIC_INLINE void LL_HRTIM_EnableDMAReq_RST2(HRTIM_TypeDef *HRTIMx, uint32_t * @arg @ref LL_HRTIM_TIMER_E * @retval None */ -__STATIC_INLINE void LL_HRTIM_DisableDMAReq_RST2(HRTIM_TypeDef *HRTIMx, uint32_t Timer) +__STATIC_INLINE void LL_HRTIM_DisableDMAReq_RST2(const HRTIM_TypeDef *HRTIMx, uint32_t Timer) { uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) + - REG_OFFSET_TAB_TIMER[iTimer])); + REG_OFFSET_TAB_TIMER[iTimer])); CLEAR_BIT(*pReg, HRTIM_TIMDIER_RST2DE); } @@ -10437,7 +10447,7 @@ __STATIC_INLINE uint32_t LL_HRTIM_IsEnabledDMAReq_RST2(const HRTIM_TypeDef *HRTI { uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) + - REG_OFFSET_TAB_TIMER[iTimer])); + REG_OFFSET_TAB_TIMER[iTimer])); return ((READ_BIT(*pReg, HRTIM_TIMDIER_RST2DE) == (HRTIM_TIMDIER_RST2DE)) ? 1UL : 0UL); } @@ -10454,11 +10464,11 @@ __STATIC_INLINE uint32_t LL_HRTIM_IsEnabledDMAReq_RST2(const HRTIM_TypeDef *HRTI * @arg @ref LL_HRTIM_TIMER_E * @retval None */ -__STATIC_INLINE void LL_HRTIM_EnableDMAReq_RST(HRTIM_TypeDef *HRTIMx, uint32_t Timer) +__STATIC_INLINE void LL_HRTIM_EnableDMAReq_RST(const HRTIM_TypeDef *HRTIMx, uint32_t Timer) { uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) + - REG_OFFSET_TAB_TIMER[iTimer])); + REG_OFFSET_TAB_TIMER[iTimer])); SET_BIT(*pReg, HRTIM_TIMDIER_RSTDE); } @@ -10474,11 +10484,11 @@ __STATIC_INLINE void LL_HRTIM_EnableDMAReq_RST(HRTIM_TypeDef *HRTIMx, uint32_t T * @arg @ref LL_HRTIM_TIMER_E * @retval None */ -__STATIC_INLINE void LL_HRTIM_DisableDMAReq_RST(HRTIM_TypeDef *HRTIMx, uint32_t Timer) +__STATIC_INLINE void LL_HRTIM_DisableDMAReq_RST(const HRTIM_TypeDef *HRTIMx, uint32_t Timer) { uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) + - REG_OFFSET_TAB_TIMER[iTimer])); + REG_OFFSET_TAB_TIMER[iTimer])); CLEAR_BIT(*pReg, HRTIM_TIMDIER_RSTDE); } @@ -10498,7 +10508,7 @@ __STATIC_INLINE uint32_t LL_HRTIM_IsEnabledDMAReq_RST(const HRTIM_TypeDef *HRTIM { uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) + - REG_OFFSET_TAB_TIMER[iTimer])); + REG_OFFSET_TAB_TIMER[iTimer])); return ((READ_BIT(*pReg, HRTIM_TIMDIER_RSTDE) == (HRTIM_TIMDIER_RSTDE)) ? 1UL : 0UL); } @@ -10515,11 +10525,11 @@ __STATIC_INLINE uint32_t LL_HRTIM_IsEnabledDMAReq_RST(const HRTIM_TypeDef *HRTIM * @arg @ref LL_HRTIM_TIMER_E * @retval None */ -__STATIC_INLINE void LL_HRTIM_EnableDMAReq_DLYPRT(HRTIM_TypeDef *HRTIMx, uint32_t Timer) +__STATIC_INLINE void LL_HRTIM_EnableDMAReq_DLYPRT(const HRTIM_TypeDef *HRTIMx, uint32_t Timer) { uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) + - REG_OFFSET_TAB_TIMER[iTimer])); + REG_OFFSET_TAB_TIMER[iTimer])); SET_BIT(*pReg, HRTIM_TIMDIER_DLYPRTDE); } @@ -10535,11 +10545,11 @@ __STATIC_INLINE void LL_HRTIM_EnableDMAReq_DLYPRT(HRTIM_TypeDef *HRTIMx, uint32_ * @arg @ref LL_HRTIM_TIMER_E * @retval None */ -__STATIC_INLINE void LL_HRTIM_DisableDMAReq_DLYPRT(HRTIM_TypeDef *HRTIMx, uint32_t Timer) +__STATIC_INLINE void LL_HRTIM_DisableDMAReq_DLYPRT(const HRTIM_TypeDef *HRTIMx, uint32_t Timer) { uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) + - REG_OFFSET_TAB_TIMER[iTimer])); + REG_OFFSET_TAB_TIMER[iTimer])); CLEAR_BIT(*pReg, HRTIM_TIMDIER_DLYPRTDE); } @@ -10559,7 +10569,7 @@ __STATIC_INLINE uint32_t LL_HRTIM_IsEnabledDMAReq_DLYPRT(const HRTIM_TypeDef *HR { uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) + - REG_OFFSET_TAB_TIMER[iTimer])); + REG_OFFSET_TAB_TIMER[iTimer])); return ((READ_BIT(*pReg, HRTIM_TIMDIER_DLYPRTDE) == (HRTIM_TIMDIER_DLYPRTDE)) ? 1UL : 0UL); } @@ -10572,7 +10582,7 @@ __STATIC_INLINE uint32_t LL_HRTIM_IsEnabledDMAReq_DLYPRT(const HRTIM_TypeDef *HR /** @defgroup HRTIM_LL_LL_EF_Init In-initialization and de-initialization functions * @{ */ -ErrorStatus LL_HRTIM_DeInit(HRTIM_TypeDef* HRTIMx); +ErrorStatus LL_HRTIM_DeInit(const HRTIM_TypeDef *HRTIMx); /** * @} */ @@ -10597,5 +10607,3 @@ ErrorStatus LL_HRTIM_DeInit(HRTIM_TypeDef* HRTIMx); #endif #endif /* STM32F3xx_LL_HRTIM_H */ - - diff --git a/system/Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_ll_rtc.h b/system/Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_ll_rtc.h index f39c3920fc..f46368727e 100644 --- a/system/Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_ll_rtc.h +++ b/system/Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_ll_rtc.h @@ -598,7 +598,7 @@ typedef struct * @param __VALUE__ Value to be written in the register * @retval None */ -#define LL_RTC_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__)) +#define LL_RTC_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG((__INSTANCE__)->__REG__, (__VALUE__)) /** * @brief Read a value in RTC register @@ -606,7 +606,7 @@ typedef struct * @param __REG__ Register to be read * @retval Register value */ -#define LL_RTC_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__) +#define LL_RTC_ReadReg(__INSTANCE__, __REG__) READ_REG((__INSTANCE__)->__REG__) /** * @} */ @@ -627,7 +627,7 @@ typedef struct * @param __VALUE__ BCD value to be converted * @retval Converted byte */ -#define __LL_RTC_CONVERT_BCD2BIN(__VALUE__) (uint8_t)(((uint8_t)((__VALUE__) & (uint8_t)0xF0U) >> (uint8_t)0x4U) * 10U + ((__VALUE__) & (uint8_t)0x0FU)) +#define __LL_RTC_CONVERT_BCD2BIN(__VALUE__) (uint8_t)((((uint8_t)((__VALUE__) & (uint8_t)0xF0U) >> (uint8_t)0x4U) * 10U) + ((__VALUE__) & (uint8_t)0x0FU)) /** * @} diff --git a/system/Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_ll_spi.h b/system/Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_ll_spi.h index f35fb1db1e..fb2679dd7c 100644 --- a/system/Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_ll_spi.h +++ b/system/Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_ll_spi.h @@ -55,53 +55,66 @@ typedef struct uint32_t TransferDirection; /*!< Specifies the SPI unidirectional or bidirectional data mode. This parameter can be a value of @ref SPI_LL_EC_TRANSFER_MODE. - This feature can be modified afterwards using unitary function @ref LL_SPI_SetTransferDirection().*/ + This feature can be modified afterwards using unitary + function @ref LL_SPI_SetTransferDirection().*/ uint32_t Mode; /*!< Specifies the SPI mode (Master/Slave). This parameter can be a value of @ref SPI_LL_EC_MODE. - This feature can be modified afterwards using unitary function @ref LL_SPI_SetMode().*/ + This feature can be modified afterwards using unitary + function @ref LL_SPI_SetMode().*/ uint32_t DataWidth; /*!< Specifies the SPI data width. This parameter can be a value of @ref SPI_LL_EC_DATAWIDTH. - This feature can be modified afterwards using unitary function @ref LL_SPI_SetDataWidth().*/ + This feature can be modified afterwards using unitary + function @ref LL_SPI_SetDataWidth().*/ uint32_t ClockPolarity; /*!< Specifies the serial clock steady state. This parameter can be a value of @ref SPI_LL_EC_POLARITY. - This feature can be modified afterwards using unitary function @ref LL_SPI_SetClockPolarity().*/ + This feature can be modified afterwards using unitary + function @ref LL_SPI_SetClockPolarity().*/ uint32_t ClockPhase; /*!< Specifies the clock active edge for the bit capture. This parameter can be a value of @ref SPI_LL_EC_PHASE. - This feature can be modified afterwards using unitary function @ref LL_SPI_SetClockPhase().*/ + This feature can be modified afterwards using unitary + function @ref LL_SPI_SetClockPhase().*/ - uint32_t NSS; /*!< Specifies whether the NSS signal is managed by hardware (NSS pin) or by software using the SSI bit. + uint32_t NSS; /*!< Specifies whether the NSS signal is managed by hardware (NSS pin) + or by software using the SSI bit. This parameter can be a value of @ref SPI_LL_EC_NSS_MODE. - This feature can be modified afterwards using unitary function @ref LL_SPI_SetNSSMode().*/ + This feature can be modified afterwards using unitary + function @ref LL_SPI_SetNSSMode().*/ - uint32_t BaudRate; /*!< Specifies the BaudRate prescaler value which will be used to configure the transmit and receive SCK clock. + uint32_t BaudRate; /*!< Specifies the BaudRate prescaler value which will be used + to configure the transmit and receive SCK clock. This parameter can be a value of @ref SPI_LL_EC_BAUDRATEPRESCALER. - @note The communication clock is derived from the master clock. The slave clock does not need to be set. + @note The communication clock is derived from the master clock. + The slave clock does not need to be set. - This feature can be modified afterwards using unitary function @ref LL_SPI_SetBaudRatePrescaler().*/ + This feature can be modified afterwards using unitary + function @ref LL_SPI_SetBaudRatePrescaler().*/ uint32_t BitOrder; /*!< Specifies whether data transfers start from MSB or LSB bit. This parameter can be a value of @ref SPI_LL_EC_BIT_ORDER. - This feature can be modified afterwards using unitary function @ref LL_SPI_SetTransferBitOrder().*/ + This feature can be modified afterwards using unitary + function @ref LL_SPI_SetTransferBitOrder().*/ uint32_t CRCCalculation; /*!< Specifies if the CRC calculation is enabled or not. This parameter can be a value of @ref SPI_LL_EC_CRC_CALCULATION. - This feature can be modified afterwards using unitary functions @ref LL_SPI_EnableCRC() and @ref LL_SPI_DisableCRC().*/ + This feature can be modified afterwards using unitary + functions @ref LL_SPI_EnableCRC() and @ref LL_SPI_DisableCRC().*/ uint32_t CRCPoly; /*!< Specifies the polynomial used for the CRC calculation. This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFFFF. - This feature can be modified afterwards using unitary function @ref LL_SPI_SetCRCPolynomial().*/ + This feature can be modified afterwards using unitary + function @ref LL_SPI_SetCRCPolynomial().*/ } LL_SPI_InitTypeDef; @@ -378,7 +391,7 @@ __STATIC_INLINE void LL_SPI_Disable(SPI_TypeDef *SPIx) * @param SPIx SPI Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_SPI_IsEnabled(SPI_TypeDef *SPIx) +__STATIC_INLINE uint32_t LL_SPI_IsEnabled(const SPI_TypeDef *SPIx) { return ((READ_BIT(SPIx->CR1, SPI_CR1_SPE) == (SPI_CR1_SPE)) ? 1UL : 0UL); } @@ -408,7 +421,7 @@ __STATIC_INLINE void LL_SPI_SetMode(SPI_TypeDef *SPIx, uint32_t Mode) * @arg @ref LL_SPI_MODE_MASTER * @arg @ref LL_SPI_MODE_SLAVE */ -__STATIC_INLINE uint32_t LL_SPI_GetMode(SPI_TypeDef *SPIx) +__STATIC_INLINE uint32_t LL_SPI_GetMode(const SPI_TypeDef *SPIx) { return (uint32_t)(READ_BIT(SPIx->CR1, SPI_CR1_MSTR | SPI_CR1_SSI)); } @@ -436,7 +449,7 @@ __STATIC_INLINE void LL_SPI_SetStandard(SPI_TypeDef *SPIx, uint32_t Standard) * @arg @ref LL_SPI_PROTOCOL_MOTOROLA * @arg @ref LL_SPI_PROTOCOL_TI */ -__STATIC_INLINE uint32_t LL_SPI_GetStandard(SPI_TypeDef *SPIx) +__STATIC_INLINE uint32_t LL_SPI_GetStandard(const SPI_TypeDef *SPIx) { return (uint32_t)(READ_BIT(SPIx->CR2, SPI_CR2_FRF)); } @@ -465,7 +478,7 @@ __STATIC_INLINE void LL_SPI_SetClockPhase(SPI_TypeDef *SPIx, uint32_t ClockPhase * @arg @ref LL_SPI_PHASE_1EDGE * @arg @ref LL_SPI_PHASE_2EDGE */ -__STATIC_INLINE uint32_t LL_SPI_GetClockPhase(SPI_TypeDef *SPIx) +__STATIC_INLINE uint32_t LL_SPI_GetClockPhase(const SPI_TypeDef *SPIx) { return (uint32_t)(READ_BIT(SPIx->CR1, SPI_CR1_CPHA)); } @@ -494,7 +507,7 @@ __STATIC_INLINE void LL_SPI_SetClockPolarity(SPI_TypeDef *SPIx, uint32_t ClockPo * @arg @ref LL_SPI_POLARITY_LOW * @arg @ref LL_SPI_POLARITY_HIGH */ -__STATIC_INLINE uint32_t LL_SPI_GetClockPolarity(SPI_TypeDef *SPIx) +__STATIC_INLINE uint32_t LL_SPI_GetClockPolarity(const SPI_TypeDef *SPIx) { return (uint32_t)(READ_BIT(SPIx->CR1, SPI_CR1_CPOL)); } @@ -534,7 +547,7 @@ __STATIC_INLINE void LL_SPI_SetBaudRatePrescaler(SPI_TypeDef *SPIx, uint32_t Bau * @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV128 * @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV256 */ -__STATIC_INLINE uint32_t LL_SPI_GetBaudRatePrescaler(SPI_TypeDef *SPIx) +__STATIC_INLINE uint32_t LL_SPI_GetBaudRatePrescaler(const SPI_TypeDef *SPIx) { return (uint32_t)(READ_BIT(SPIx->CR1, SPI_CR1_BR)); } @@ -562,7 +575,7 @@ __STATIC_INLINE void LL_SPI_SetTransferBitOrder(SPI_TypeDef *SPIx, uint32_t BitO * @arg @ref LL_SPI_LSB_FIRST * @arg @ref LL_SPI_MSB_FIRST */ -__STATIC_INLINE uint32_t LL_SPI_GetTransferBitOrder(SPI_TypeDef *SPIx) +__STATIC_INLINE uint32_t LL_SPI_GetTransferBitOrder(const SPI_TypeDef *SPIx) { return (uint32_t)(READ_BIT(SPIx->CR1, SPI_CR1_LSBFIRST)); } @@ -599,7 +612,7 @@ __STATIC_INLINE void LL_SPI_SetTransferDirection(SPI_TypeDef *SPIx, uint32_t Tra * @arg @ref LL_SPI_HALF_DUPLEX_RX * @arg @ref LL_SPI_HALF_DUPLEX_TX */ -__STATIC_INLINE uint32_t LL_SPI_GetTransferDirection(SPI_TypeDef *SPIx) +__STATIC_INLINE uint32_t LL_SPI_GetTransferDirection(const SPI_TypeDef *SPIx) { return (uint32_t)(READ_BIT(SPIx->CR1, SPI_CR1_RXONLY | SPI_CR1_BIDIMODE | SPI_CR1_BIDIOE)); } @@ -648,7 +661,7 @@ __STATIC_INLINE void LL_SPI_SetDataWidth(SPI_TypeDef *SPIx, uint32_t DataWidth) * @arg @ref LL_SPI_DATAWIDTH_15BIT * @arg @ref LL_SPI_DATAWIDTH_16BIT */ -__STATIC_INLINE uint32_t LL_SPI_GetDataWidth(SPI_TypeDef *SPIx) +__STATIC_INLINE uint32_t LL_SPI_GetDataWidth(const SPI_TypeDef *SPIx) { return (uint32_t)(READ_BIT(SPIx->CR2, SPI_CR2_DS)); } @@ -675,7 +688,7 @@ __STATIC_INLINE void LL_SPI_SetRxFIFOThreshold(SPI_TypeDef *SPIx, uint32_t Thres * @arg @ref LL_SPI_RX_FIFO_TH_HALF * @arg @ref LL_SPI_RX_FIFO_TH_QUARTER */ -__STATIC_INLINE uint32_t LL_SPI_GetRxFIFOThreshold(SPI_TypeDef *SPIx) +__STATIC_INLINE uint32_t LL_SPI_GetRxFIFOThreshold(const SPI_TypeDef *SPIx) { return (uint32_t)(READ_BIT(SPIx->CR2, SPI_CR2_FRXTH)); } @@ -719,7 +732,7 @@ __STATIC_INLINE void LL_SPI_DisableCRC(SPI_TypeDef *SPIx) * @param SPIx SPI Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_SPI_IsEnabledCRC(SPI_TypeDef *SPIx) +__STATIC_INLINE uint32_t LL_SPI_IsEnabledCRC(const SPI_TypeDef *SPIx) { return ((READ_BIT(SPIx->CR1, SPI_CR1_CRCEN) == (SPI_CR1_CRCEN)) ? 1UL : 0UL); } @@ -747,7 +760,7 @@ __STATIC_INLINE void LL_SPI_SetCRCWidth(SPI_TypeDef *SPIx, uint32_t CRCLength) * @arg @ref LL_SPI_CRC_8BIT * @arg @ref LL_SPI_CRC_16BIT */ -__STATIC_INLINE uint32_t LL_SPI_GetCRCWidth(SPI_TypeDef *SPIx) +__STATIC_INLINE uint32_t LL_SPI_GetCRCWidth(const SPI_TypeDef *SPIx) { return (uint32_t)(READ_BIT(SPIx->CR1, SPI_CR1_CRCL)); } @@ -782,7 +795,7 @@ __STATIC_INLINE void LL_SPI_SetCRCPolynomial(SPI_TypeDef *SPIx, uint32_t CRCPoly * @param SPIx SPI Instance * @retval Returned value is a number between Min_Data = 0x00 and Max_Data = 0xFFFF */ -__STATIC_INLINE uint32_t LL_SPI_GetCRCPolynomial(SPI_TypeDef *SPIx) +__STATIC_INLINE uint32_t LL_SPI_GetCRCPolynomial(const SPI_TypeDef *SPIx) { return (uint32_t)(READ_REG(SPIx->CRCPR)); } @@ -793,7 +806,7 @@ __STATIC_INLINE uint32_t LL_SPI_GetCRCPolynomial(SPI_TypeDef *SPIx) * @param SPIx SPI Instance * @retval Returned value is a number between Min_Data = 0x00 and Max_Data = 0xFFFF */ -__STATIC_INLINE uint32_t LL_SPI_GetRxCRC(SPI_TypeDef *SPIx) +__STATIC_INLINE uint32_t LL_SPI_GetRxCRC(const SPI_TypeDef *SPIx) { return (uint32_t)(READ_REG(SPIx->RXCRCR)); } @@ -804,7 +817,7 @@ __STATIC_INLINE uint32_t LL_SPI_GetRxCRC(SPI_TypeDef *SPIx) * @param SPIx SPI Instance * @retval Returned value is a number between Min_Data = 0x00 and Max_Data = 0xFFFF */ -__STATIC_INLINE uint32_t LL_SPI_GetTxCRC(SPI_TypeDef *SPIx) +__STATIC_INLINE uint32_t LL_SPI_GetTxCRC(const SPI_TypeDef *SPIx) { return (uint32_t)(READ_REG(SPIx->TXCRCR)); } @@ -845,7 +858,7 @@ __STATIC_INLINE void LL_SPI_SetNSSMode(SPI_TypeDef *SPIx, uint32_t NSS) * @arg @ref LL_SPI_NSS_HARD_INPUT * @arg @ref LL_SPI_NSS_HARD_OUTPUT */ -__STATIC_INLINE uint32_t LL_SPI_GetNSSMode(SPI_TypeDef *SPIx) +__STATIC_INLINE uint32_t LL_SPI_GetNSSMode(const SPI_TypeDef *SPIx) { uint32_t Ssm = (READ_BIT(SPIx->CR1, SPI_CR1_SSM)); uint32_t Ssoe = (READ_BIT(SPIx->CR2, SPI_CR2_SSOE) << 16U); @@ -883,7 +896,7 @@ __STATIC_INLINE void LL_SPI_DisableNSSPulseMgt(SPI_TypeDef *SPIx) * @param SPIx SPI Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_SPI_IsEnabledNSSPulse(SPI_TypeDef *SPIx) +__STATIC_INLINE uint32_t LL_SPI_IsEnabledNSSPulse(const SPI_TypeDef *SPIx) { return ((READ_BIT(SPIx->CR2, SPI_CR2_NSSP) == (SPI_CR2_NSSP)) ? 1UL : 0UL); } @@ -902,7 +915,7 @@ __STATIC_INLINE uint32_t LL_SPI_IsEnabledNSSPulse(SPI_TypeDef *SPIx) * @param SPIx SPI Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_RXNE(SPI_TypeDef *SPIx) +__STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_RXNE(const SPI_TypeDef *SPIx) { return ((READ_BIT(SPIx->SR, SPI_SR_RXNE) == (SPI_SR_RXNE)) ? 1UL : 0UL); } @@ -913,7 +926,7 @@ __STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_RXNE(SPI_TypeDef *SPIx) * @param SPIx SPI Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_TXE(SPI_TypeDef *SPIx) +__STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_TXE(const SPI_TypeDef *SPIx) { return ((READ_BIT(SPIx->SR, SPI_SR_TXE) == (SPI_SR_TXE)) ? 1UL : 0UL); } @@ -924,7 +937,7 @@ __STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_TXE(SPI_TypeDef *SPIx) * @param SPIx SPI Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_CRCERR(SPI_TypeDef *SPIx) +__STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_CRCERR(const SPI_TypeDef *SPIx) { return ((READ_BIT(SPIx->SR, SPI_SR_CRCERR) == (SPI_SR_CRCERR)) ? 1UL : 0UL); } @@ -935,7 +948,7 @@ __STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_CRCERR(SPI_TypeDef *SPIx) * @param SPIx SPI Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_MODF(SPI_TypeDef *SPIx) +__STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_MODF(const SPI_TypeDef *SPIx) { return ((READ_BIT(SPIx->SR, SPI_SR_MODF) == (SPI_SR_MODF)) ? 1UL : 0UL); } @@ -946,7 +959,7 @@ __STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_MODF(SPI_TypeDef *SPIx) * @param SPIx SPI Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_OVR(SPI_TypeDef *SPIx) +__STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_OVR(const SPI_TypeDef *SPIx) { return ((READ_BIT(SPIx->SR, SPI_SR_OVR) == (SPI_SR_OVR)) ? 1UL : 0UL); } @@ -964,7 +977,7 @@ __STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_OVR(SPI_TypeDef *SPIx) * @param SPIx SPI Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_BSY(SPI_TypeDef *SPIx) +__STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_BSY(const SPI_TypeDef *SPIx) { return ((READ_BIT(SPIx->SR, SPI_SR_BSY) == (SPI_SR_BSY)) ? 1UL : 0UL); } @@ -975,7 +988,7 @@ __STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_BSY(SPI_TypeDef *SPIx) * @param SPIx SPI Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_FRE(SPI_TypeDef *SPIx) +__STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_FRE(const SPI_TypeDef *SPIx) { return ((READ_BIT(SPIx->SR, SPI_SR_FRE) == (SPI_SR_FRE)) ? 1UL : 0UL); } @@ -990,7 +1003,7 @@ __STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_FRE(SPI_TypeDef *SPIx) * @arg @ref LL_SPI_RX_FIFO_HALF_FULL * @arg @ref LL_SPI_RX_FIFO_FULL */ -__STATIC_INLINE uint32_t LL_SPI_GetRxFIFOLevel(SPI_TypeDef *SPIx) +__STATIC_INLINE uint32_t LL_SPI_GetRxFIFOLevel(const SPI_TypeDef *SPIx) { return (uint32_t)(READ_BIT(SPIx->SR, SPI_SR_FRLVL)); } @@ -1005,7 +1018,7 @@ __STATIC_INLINE uint32_t LL_SPI_GetRxFIFOLevel(SPI_TypeDef *SPIx) * @arg @ref LL_SPI_TX_FIFO_HALF_FULL * @arg @ref LL_SPI_TX_FIFO_FULL */ -__STATIC_INLINE uint32_t LL_SPI_GetTxFIFOLevel(SPI_TypeDef *SPIx) +__STATIC_INLINE uint32_t LL_SPI_GetTxFIFOLevel(const SPI_TypeDef *SPIx) { return (uint32_t)(READ_BIT(SPIx->SR, SPI_SR_FTLVL)); } @@ -1045,7 +1058,7 @@ __STATIC_INLINE void LL_SPI_ClearFlag_MODF(SPI_TypeDef *SPIx) * @param SPIx SPI Instance * @retval None */ -__STATIC_INLINE void LL_SPI_ClearFlag_OVR(SPI_TypeDef *SPIx) +__STATIC_INLINE void LL_SPI_ClearFlag_OVR(const SPI_TypeDef *SPIx) { __IO uint32_t tmpreg; tmpreg = SPIx->DR; @@ -1061,7 +1074,7 @@ __STATIC_INLINE void LL_SPI_ClearFlag_OVR(SPI_TypeDef *SPIx) * @param SPIx SPI Instance * @retval None */ -__STATIC_INLINE void LL_SPI_ClearFlag_FRE(SPI_TypeDef *SPIx) +__STATIC_INLINE void LL_SPI_ClearFlag_FRE(const SPI_TypeDef *SPIx) { __IO uint32_t tmpreg; tmpreg = SPIx->SR; @@ -1078,7 +1091,8 @@ __STATIC_INLINE void LL_SPI_ClearFlag_FRE(SPI_TypeDef *SPIx) /** * @brief Enable error interrupt - * @note This bit controls the generation of an interrupt when an error condition occurs (CRCERR, OVR, MODF in SPI mode, FRE at TI mode). + * @note This bit controls the generation of an interrupt when an error condition + * occurs (CRCERR, OVR, MODF in SPI mode, FRE at TI mode). * @rmtoll CR2 ERRIE LL_SPI_EnableIT_ERR * @param SPIx SPI Instance * @retval None @@ -1112,7 +1126,8 @@ __STATIC_INLINE void LL_SPI_EnableIT_TXE(SPI_TypeDef *SPIx) /** * @brief Disable error interrupt - * @note This bit controls the generation of an interrupt when an error condition occurs (CRCERR, OVR, MODF in SPI mode, FRE at TI mode). + * @note This bit controls the generation of an interrupt when an error condition + * occurs (CRCERR, OVR, MODF in SPI mode, FRE at TI mode). * @rmtoll CR2 ERRIE LL_SPI_DisableIT_ERR * @param SPIx SPI Instance * @retval None @@ -1150,7 +1165,7 @@ __STATIC_INLINE void LL_SPI_DisableIT_TXE(SPI_TypeDef *SPIx) * @param SPIx SPI Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_SPI_IsEnabledIT_ERR(SPI_TypeDef *SPIx) +__STATIC_INLINE uint32_t LL_SPI_IsEnabledIT_ERR(const SPI_TypeDef *SPIx) { return ((READ_BIT(SPIx->CR2, SPI_CR2_ERRIE) == (SPI_CR2_ERRIE)) ? 1UL : 0UL); } @@ -1161,7 +1176,7 @@ __STATIC_INLINE uint32_t LL_SPI_IsEnabledIT_ERR(SPI_TypeDef *SPIx) * @param SPIx SPI Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_SPI_IsEnabledIT_RXNE(SPI_TypeDef *SPIx) +__STATIC_INLINE uint32_t LL_SPI_IsEnabledIT_RXNE(const SPI_TypeDef *SPIx) { return ((READ_BIT(SPIx->CR2, SPI_CR2_RXNEIE) == (SPI_CR2_RXNEIE)) ? 1UL : 0UL); } @@ -1172,7 +1187,7 @@ __STATIC_INLINE uint32_t LL_SPI_IsEnabledIT_RXNE(SPI_TypeDef *SPIx) * @param SPIx SPI Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_SPI_IsEnabledIT_TXE(SPI_TypeDef *SPIx) +__STATIC_INLINE uint32_t LL_SPI_IsEnabledIT_TXE(const SPI_TypeDef *SPIx) { return ((READ_BIT(SPIx->CR2, SPI_CR2_TXEIE) == (SPI_CR2_TXEIE)) ? 1UL : 0UL); } @@ -1213,7 +1228,7 @@ __STATIC_INLINE void LL_SPI_DisableDMAReq_RX(SPI_TypeDef *SPIx) * @param SPIx SPI Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_SPI_IsEnabledDMAReq_RX(SPI_TypeDef *SPIx) +__STATIC_INLINE uint32_t LL_SPI_IsEnabledDMAReq_RX(const SPI_TypeDef *SPIx) { return ((READ_BIT(SPIx->CR2, SPI_CR2_RXDMAEN) == (SPI_CR2_RXDMAEN)) ? 1UL : 0UL); } @@ -1246,7 +1261,7 @@ __STATIC_INLINE void LL_SPI_DisableDMAReq_TX(SPI_TypeDef *SPIx) * @param SPIx SPI Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_SPI_IsEnabledDMAReq_TX(SPI_TypeDef *SPIx) +__STATIC_INLINE uint32_t LL_SPI_IsEnabledDMAReq_TX(const SPI_TypeDef *SPIx) { return ((READ_BIT(SPIx->CR2, SPI_CR2_TXDMAEN) == (SPI_CR2_TXDMAEN)) ? 1UL : 0UL); } @@ -1273,7 +1288,7 @@ __STATIC_INLINE void LL_SPI_SetDMAParity_RX(SPI_TypeDef *SPIx, uint32_t Parity) * @arg @ref LL_SPI_DMA_PARITY_ODD * @arg @ref LL_SPI_DMA_PARITY_EVEN */ -__STATIC_INLINE uint32_t LL_SPI_GetDMAParity_RX(SPI_TypeDef *SPIx) +__STATIC_INLINE uint32_t LL_SPI_GetDMAParity_RX(const SPI_TypeDef *SPIx) { return (uint32_t)(READ_BIT(SPIx->CR2, SPI_CR2_LDMARX) >> SPI_CR2_LDMARX_Pos); } @@ -1300,7 +1315,7 @@ __STATIC_INLINE void LL_SPI_SetDMAParity_TX(SPI_TypeDef *SPIx, uint32_t Parity) * @arg @ref LL_SPI_DMA_PARITY_ODD * @arg @ref LL_SPI_DMA_PARITY_EVEN */ -__STATIC_INLINE uint32_t LL_SPI_GetDMAParity_TX(SPI_TypeDef *SPIx) +__STATIC_INLINE uint32_t LL_SPI_GetDMAParity_TX(const SPI_TypeDef *SPIx) { return (uint32_t)(READ_BIT(SPIx->CR2, SPI_CR2_LDMATX) >> SPI_CR2_LDMATX_Pos); } @@ -1311,7 +1326,7 @@ __STATIC_INLINE uint32_t LL_SPI_GetDMAParity_TX(SPI_TypeDef *SPIx) * @param SPIx SPI Instance * @retval Address of data register */ -__STATIC_INLINE uint32_t LL_SPI_DMA_GetRegAddr(SPI_TypeDef *SPIx) +__STATIC_INLINE uint32_t LL_SPI_DMA_GetRegAddr(const SPI_TypeDef *SPIx) { return (uint32_t) &(SPIx->DR); } @@ -1388,7 +1403,7 @@ __STATIC_INLINE void LL_SPI_TransmitData16(SPI_TypeDef *SPIx, uint16_t TxData) * @{ */ -ErrorStatus LL_SPI_DeInit(SPI_TypeDef *SPIx); +ErrorStatus LL_SPI_DeInit(const SPI_TypeDef *SPIx); ErrorStatus LL_SPI_Init(SPI_TypeDef *SPIx, LL_SPI_InitTypeDef *SPI_InitStruct); void LL_SPI_StructInit(LL_SPI_InitTypeDef *SPI_InitStruct); @@ -1656,7 +1671,7 @@ __STATIC_INLINE void LL_I2S_Disable(SPI_TypeDef *SPIx) * @param SPIx SPI Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_I2S_IsEnabled(SPI_TypeDef *SPIx) +__STATIC_INLINE uint32_t LL_I2S_IsEnabled(const SPI_TypeDef *SPIx) { return ((READ_BIT(SPIx->I2SCFGR, SPI_I2SCFGR_I2SE) == (SPI_I2SCFGR_I2SE)) ? 1UL : 0UL); } @@ -1689,7 +1704,7 @@ __STATIC_INLINE void LL_I2S_SetDataFormat(SPI_TypeDef *SPIx, uint32_t DataFormat * @arg @ref LL_I2S_DATAFORMAT_24B * @arg @ref LL_I2S_DATAFORMAT_32B */ -__STATIC_INLINE uint32_t LL_I2S_GetDataFormat(SPI_TypeDef *SPIx) +__STATIC_INLINE uint32_t LL_I2S_GetDataFormat(const SPI_TypeDef *SPIx) { return (uint32_t)(READ_BIT(SPIx->I2SCFGR, SPI_I2SCFGR_DATLEN | SPI_I2SCFGR_CHLEN)); } @@ -1716,7 +1731,7 @@ __STATIC_INLINE void LL_I2S_SetClockPolarity(SPI_TypeDef *SPIx, uint32_t ClockPo * @arg @ref LL_I2S_POLARITY_LOW * @arg @ref LL_I2S_POLARITY_HIGH */ -__STATIC_INLINE uint32_t LL_I2S_GetClockPolarity(SPI_TypeDef *SPIx) +__STATIC_INLINE uint32_t LL_I2S_GetClockPolarity(const SPI_TypeDef *SPIx) { return (uint32_t)(READ_BIT(SPIx->I2SCFGR, SPI_I2SCFGR_CKPOL)); } @@ -1751,7 +1766,7 @@ __STATIC_INLINE void LL_I2S_SetStandard(SPI_TypeDef *SPIx, uint32_t Standard) * @arg @ref LL_I2S_STANDARD_PCM_SHORT * @arg @ref LL_I2S_STANDARD_PCM_LONG */ -__STATIC_INLINE uint32_t LL_I2S_GetStandard(SPI_TypeDef *SPIx) +__STATIC_INLINE uint32_t LL_I2S_GetStandard(const SPI_TypeDef *SPIx) { return (uint32_t)(READ_BIT(SPIx->I2SCFGR, SPI_I2SCFGR_I2SSTD | SPI_I2SCFGR_PCMSYNC)); } @@ -1782,7 +1797,7 @@ __STATIC_INLINE void LL_I2S_SetTransferMode(SPI_TypeDef *SPIx, uint32_t Mode) * @arg @ref LL_I2S_MODE_MASTER_TX * @arg @ref LL_I2S_MODE_MASTER_RX */ -__STATIC_INLINE uint32_t LL_I2S_GetTransferMode(SPI_TypeDef *SPIx) +__STATIC_INLINE uint32_t LL_I2S_GetTransferMode(const SPI_TypeDef *SPIx) { return (uint32_t)(READ_BIT(SPIx->I2SCFGR, SPI_I2SCFGR_I2SCFG)); } @@ -1805,7 +1820,7 @@ __STATIC_INLINE void LL_I2S_SetPrescalerLinear(SPI_TypeDef *SPIx, uint8_t Presca * @param SPIx SPI Instance * @retval PrescalerLinear Value between Min_Data=0x02 and Max_Data=0xFF */ -__STATIC_INLINE uint32_t LL_I2S_GetPrescalerLinear(SPI_TypeDef *SPIx) +__STATIC_INLINE uint32_t LL_I2S_GetPrescalerLinear(const SPI_TypeDef *SPIx) { return (uint32_t)(READ_BIT(SPIx->I2SPR, SPI_I2SPR_I2SDIV)); } @@ -1832,7 +1847,7 @@ __STATIC_INLINE void LL_I2S_SetPrescalerParity(SPI_TypeDef *SPIx, uint32_t Presc * @arg @ref LL_I2S_PRESCALER_PARITY_EVEN * @arg @ref LL_I2S_PRESCALER_PARITY_ODD */ -__STATIC_INLINE uint32_t LL_I2S_GetPrescalerParity(SPI_TypeDef *SPIx) +__STATIC_INLINE uint32_t LL_I2S_GetPrescalerParity(const SPI_TypeDef *SPIx) { return (uint32_t)(READ_BIT(SPIx->I2SPR, SPI_I2SPR_ODD) >> 8U); } @@ -1865,7 +1880,7 @@ __STATIC_INLINE void LL_I2S_DisableMasterClock(SPI_TypeDef *SPIx) * @param SPIx SPI Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_I2S_IsEnabledMasterClock(SPI_TypeDef *SPIx) +__STATIC_INLINE uint32_t LL_I2S_IsEnabledMasterClock(const SPI_TypeDef *SPIx) { return ((READ_BIT(SPIx->I2SPR, SPI_I2SPR_MCKOE) == (SPI_I2SPR_MCKOE)) ? 1UL : 0UL); } @@ -1884,7 +1899,7 @@ __STATIC_INLINE uint32_t LL_I2S_IsEnabledMasterClock(SPI_TypeDef *SPIx) * @param SPIx SPI Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_I2S_IsActiveFlag_RXNE(SPI_TypeDef *SPIx) +__STATIC_INLINE uint32_t LL_I2S_IsActiveFlag_RXNE(const SPI_TypeDef *SPIx) { return LL_SPI_IsActiveFlag_RXNE(SPIx); } @@ -1895,7 +1910,7 @@ __STATIC_INLINE uint32_t LL_I2S_IsActiveFlag_RXNE(SPI_TypeDef *SPIx) * @param SPIx SPI Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_I2S_IsActiveFlag_TXE(SPI_TypeDef *SPIx) +__STATIC_INLINE uint32_t LL_I2S_IsActiveFlag_TXE(const SPI_TypeDef *SPIx) { return LL_SPI_IsActiveFlag_TXE(SPIx); } @@ -1906,7 +1921,7 @@ __STATIC_INLINE uint32_t LL_I2S_IsActiveFlag_TXE(SPI_TypeDef *SPIx) * @param SPIx SPI Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_I2S_IsActiveFlag_BSY(SPI_TypeDef *SPIx) +__STATIC_INLINE uint32_t LL_I2S_IsActiveFlag_BSY(const SPI_TypeDef *SPIx) { return LL_SPI_IsActiveFlag_BSY(SPIx); } @@ -1917,7 +1932,7 @@ __STATIC_INLINE uint32_t LL_I2S_IsActiveFlag_BSY(SPI_TypeDef *SPIx) * @param SPIx SPI Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_I2S_IsActiveFlag_OVR(SPI_TypeDef *SPIx) +__STATIC_INLINE uint32_t LL_I2S_IsActiveFlag_OVR(const SPI_TypeDef *SPIx) { return LL_SPI_IsActiveFlag_OVR(SPIx); } @@ -1928,7 +1943,7 @@ __STATIC_INLINE uint32_t LL_I2S_IsActiveFlag_OVR(SPI_TypeDef *SPIx) * @param SPIx SPI Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_I2S_IsActiveFlag_UDR(SPI_TypeDef *SPIx) +__STATIC_INLINE uint32_t LL_I2S_IsActiveFlag_UDR(const SPI_TypeDef *SPIx) { return ((READ_BIT(SPIx->SR, SPI_SR_UDR) == (SPI_SR_UDR)) ? 1UL : 0UL); } @@ -1939,7 +1954,7 @@ __STATIC_INLINE uint32_t LL_I2S_IsActiveFlag_UDR(SPI_TypeDef *SPIx) * @param SPIx SPI Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_I2S_IsActiveFlag_FRE(SPI_TypeDef *SPIx) +__STATIC_INLINE uint32_t LL_I2S_IsActiveFlag_FRE(const SPI_TypeDef *SPIx) { return LL_SPI_IsActiveFlag_FRE(SPIx); } @@ -1953,7 +1968,7 @@ __STATIC_INLINE uint32_t LL_I2S_IsActiveFlag_FRE(SPI_TypeDef *SPIx) * @param SPIx SPI Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_I2S_IsActiveFlag_CHSIDE(SPI_TypeDef *SPIx) +__STATIC_INLINE uint32_t LL_I2S_IsActiveFlag_CHSIDE(const SPI_TypeDef *SPIx) { return ((READ_BIT(SPIx->SR, SPI_SR_CHSIDE) == (SPI_SR_CHSIDE)) ? 1UL : 0UL); } @@ -1975,7 +1990,7 @@ __STATIC_INLINE void LL_I2S_ClearFlag_OVR(SPI_TypeDef *SPIx) * @param SPIx SPI Instance * @retval None */ -__STATIC_INLINE void LL_I2S_ClearFlag_UDR(SPI_TypeDef *SPIx) +__STATIC_INLINE void LL_I2S_ClearFlag_UDR(const SPI_TypeDef *SPIx) { __IO uint32_t tmpreg; tmpreg = SPIx->SR; @@ -1988,7 +2003,7 @@ __STATIC_INLINE void LL_I2S_ClearFlag_UDR(SPI_TypeDef *SPIx) * @param SPIx SPI Instance * @retval None */ -__STATIC_INLINE void LL_I2S_ClearFlag_FRE(SPI_TypeDef *SPIx) +__STATIC_INLINE void LL_I2S_ClearFlag_FRE(const SPI_TypeDef *SPIx) { LL_SPI_ClearFlag_FRE(SPIx); } @@ -2075,7 +2090,7 @@ __STATIC_INLINE void LL_I2S_DisableIT_TXE(SPI_TypeDef *SPIx) * @param SPIx SPI Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_I2S_IsEnabledIT_ERR(SPI_TypeDef *SPIx) +__STATIC_INLINE uint32_t LL_I2S_IsEnabledIT_ERR(const SPI_TypeDef *SPIx) { return LL_SPI_IsEnabledIT_ERR(SPIx); } @@ -2086,7 +2101,7 @@ __STATIC_INLINE uint32_t LL_I2S_IsEnabledIT_ERR(SPI_TypeDef *SPIx) * @param SPIx SPI Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_I2S_IsEnabledIT_RXNE(SPI_TypeDef *SPIx) +__STATIC_INLINE uint32_t LL_I2S_IsEnabledIT_RXNE(const SPI_TypeDef *SPIx) { return LL_SPI_IsEnabledIT_RXNE(SPIx); } @@ -2097,7 +2112,7 @@ __STATIC_INLINE uint32_t LL_I2S_IsEnabledIT_RXNE(SPI_TypeDef *SPIx) * @param SPIx SPI Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_I2S_IsEnabledIT_TXE(SPI_TypeDef *SPIx) +__STATIC_INLINE uint32_t LL_I2S_IsEnabledIT_TXE(const SPI_TypeDef *SPIx) { return LL_SPI_IsEnabledIT_TXE(SPIx); } @@ -2138,7 +2153,7 @@ __STATIC_INLINE void LL_I2S_DisableDMAReq_RX(SPI_TypeDef *SPIx) * @param SPIx SPI Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_I2S_IsEnabledDMAReq_RX(SPI_TypeDef *SPIx) +__STATIC_INLINE uint32_t LL_I2S_IsEnabledDMAReq_RX(const SPI_TypeDef *SPIx) { return LL_SPI_IsEnabledDMAReq_RX(SPIx); } @@ -2171,7 +2186,7 @@ __STATIC_INLINE void LL_I2S_DisableDMAReq_TX(SPI_TypeDef *SPIx) * @param SPIx SPI Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_I2S_IsEnabledDMAReq_TX(SPI_TypeDef *SPIx) +__STATIC_INLINE uint32_t LL_I2S_IsEnabledDMAReq_TX(const SPI_TypeDef *SPIx) { return LL_SPI_IsEnabledDMAReq_TX(SPIx); } @@ -2216,8 +2231,8 @@ __STATIC_INLINE void LL_I2S_TransmitData16(SPI_TypeDef *SPIx, uint16_t TxData) * @{ */ -ErrorStatus LL_I2S_DeInit(SPI_TypeDef *SPIx); -ErrorStatus LL_I2S_Init(SPI_TypeDef *SPIx, LL_I2S_InitTypeDef *I2S_InitStruct); +ErrorStatus LL_I2S_DeInit(const SPI_TypeDef *SPIx); +ErrorStatus LL_I2S_Init(SPI_TypeDef *SPIx,const LL_I2S_InitTypeDef *I2S_InitStruct); void LL_I2S_StructInit(LL_I2S_InitTypeDef *I2S_InitStruct); void LL_I2S_ConfigPrescaler(SPI_TypeDef *SPIx, uint32_t PrescalerLinear, uint32_t PrescalerParity); #if defined (SPI_I2S_FULLDUPLEX_SUPPORT) diff --git a/system/Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_ll_tim.h b/system/Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_ll_tim.h index e799626c2b..6709bf267f 100644 --- a/system/Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_ll_tim.h +++ b/system/Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_ll_tim.h @@ -539,8 +539,8 @@ typedef struct @note This bit-field can not be modified as long as LOCK level 1 has been programmed. */ - #endif /* TIM_BDTR_BK2E */ + uint32_t AutomaticOutput; /*!< Specifies whether the TIM Automatic Output feature is enabled or not. This parameter can be a value of @ref TIM_LL_EC_AUTOMATICOUTPUT_ENABLE @@ -757,8 +757,10 @@ typedef struct /** Legacy definitions for compatibility purpose @cond 0 */ +#if defined(TIM_CCMR1_OC1M_3) #define LL_TIM_OCMODE_ASSYMETRIC_PWM1 LL_TIM_OCMODE_ASYMMETRIC_PWM1 #define LL_TIM_OCMODE_ASSYMETRIC_PWM2 LL_TIM_OCMODE_ASYMMETRIC_PWM2 +#endif /* TIM_CCMR1_OC1M_3 */ /** @endcond */ @@ -910,7 +912,7 @@ typedef struct * @} */ -#if defined(TIM_CR2_MMS2) +#if defined(TIM_CR2_MMS2) /** @defgroup TIM_LL_EC_TRGO2 Trigger Output 2 * @{ */ @@ -3438,7 +3440,7 @@ __STATIC_INLINE void LL_TIM_SetTriggerOutput(TIM_TypeDef *TIMx, uint32_t TimerSy MODIFY_REG(TIMx->CR2, TIM_CR2_MMS, TimerSynchronization); } -#if defined(TIM_CR2_MMS2) +#if defined(TIM_CR2_MMS2) /** * @brief Set the trigger output 2 (TRGO2) used for ADC synchronization . * @note Macro IS_TIM_TRGO2_INSTANCE(TIMx) can be used to check @@ -4192,7 +4194,7 @@ __STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC4(const TIM_TypeDef *TIMx) return ((READ_BIT(TIMx->SR, TIM_SR_CC4IF) == (TIM_SR_CC4IF)) ? 1UL : 0UL); } -#if defined (TIM_SR_CC5IF) +#if defined (TIM_SR_CC5IF) /** * @brief Clear the Capture/Compare 5 interrupt flag (CC5F). * @rmtoll SR CC5IF LL_TIM_ClearFlag_CC5 @@ -4216,7 +4218,7 @@ __STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC5(const TIM_TypeDef *TIMx) } #endif /* TIM_SR_CC5IF */ -#if defined (TIM_SR_CC6IF) +#if defined (TIM_SR_CC6IF) /** * @brief Clear the Capture/Compare 6 interrupt flag (CC6F). * @rmtoll SR CC6IF LL_TIM_ClearFlag_CC6 diff --git a/system/Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_ll_usb.h b/system/Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_ll_usb.h index 7bfaeb3aea..b12fecc0ae 100644 --- a/system/Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_ll_usb.h +++ b/system/Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_ll_usb.h @@ -75,6 +75,7 @@ typedef struct uint8_t battery_charging_enable; /*!< Enable or disable Battery charging. */ } USB_CfgTypeDef; +#if defined (HAL_PCD_MODULE_ENABLED) typedef struct { uint8_t num; /*!< Endpoint number @@ -119,6 +120,7 @@ typedef struct uint8_t xfer_fill_db; /*!< double buffer Need to Fill new buffer used with bulk_in */ } USB_EPTypeDef; +#endif /* defined (HAL_PCD_MODULE_ENABLED) */ /* Exported constants --------------------------------------------------------*/ @@ -172,7 +174,7 @@ typedef struct /* STM32F302x8 */ #ifndef USB_EP_RX_STRX -#define USB_EP_RX_STRX (0x3U << 12) +#define USB_EP_RX_STRX (0x3UL << 12) #endif /* USB_EP_RX_STRX */ #define EP_ADDR_MSK 0x7U @@ -197,11 +199,11 @@ typedef struct */ -HAL_StatusTypeDef USB_CoreInit(USB_TypeDef *USBx, USB_CfgTypeDef cfg); +HAL_StatusTypeDef USB_CoreInit(USB_TypeDef const *USBx, USB_CfgTypeDef cfg); HAL_StatusTypeDef USB_DevInit(USB_TypeDef *USBx, USB_CfgTypeDef cfg); HAL_StatusTypeDef USB_EnableGlobalInt(USB_TypeDef *USBx); HAL_StatusTypeDef USB_DisableGlobalInt(USB_TypeDef *USBx); -HAL_StatusTypeDef USB_SetCurrentMode(USB_TypeDef *USBx, USB_ModeTypeDef mode); +HAL_StatusTypeDef USB_SetCurrentMode(USB_TypeDef const *USBx, USB_ModeTypeDef mode); HAL_StatusTypeDef USB_FlushRxFifo(USB_TypeDef const *USBx); HAL_StatusTypeDef USB_FlushTxFifo(USB_TypeDef const *USBx, uint32_t num); @@ -220,6 +222,8 @@ HAL_StatusTypeDef USB_DevConnect(USB_TypeDef *USBx); HAL_StatusTypeDef USB_DevDisconnect(USB_TypeDef *USBx); HAL_StatusTypeDef USB_StopDevice(USB_TypeDef *USBx); uint32_t USB_ReadInterrupts(USB_TypeDef const *USBx); +uint32_t USB_GetCurrentFrame(USB_TypeDef const *USBx); + HAL_StatusTypeDef USB_ActivateRemoteWakeup(USB_TypeDef *USBx); HAL_StatusTypeDef USB_DeActivateRemoteWakeup(USB_TypeDef *USBx); @@ -250,5 +254,4 @@ void USB_ReadPMA(USB_TypeDef const *USBx, uint8_t *pbUsrBuf, } #endif /* __cplusplus */ - #endif /* STM32F3xx_LL_USB_H */ diff --git a/system/Drivers/STM32F3xx_HAL_Driver/LICENSE.md b/system/Drivers/STM32F3xx_HAL_Driver/LICENSE.md index fa1b6f25ef..c681658bea 100644 --- a/system/Drivers/STM32F3xx_HAL_Driver/LICENSE.md +++ b/system/Drivers/STM32F3xx_HAL_Driver/LICENSE.md @@ -24,4 +24,4 @@ ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. \ No newline at end of file diff --git a/system/Drivers/STM32F3xx_HAL_Driver/README.md b/system/Drivers/STM32F3xx_HAL_Driver/README.md index 88907352ce..60f1085854 100644 --- a/system/Drivers/STM32F3xx_HAL_Driver/README.md +++ b/system/Drivers/STM32F3xx_HAL_Driver/README.md @@ -1,6 +1,6 @@ # STM32CubeF3 HAL Driver MCU Component -![latest tag](https://img.shields.io/github/v/tag/STMicroelectronics/stm32f3xx_hal_driver.svg?color=brightgreen) +![tag](https://img.shields.io/badge/tag-v1.5.9-brightgreen.svg) ## Overview @@ -35,4 +35,4 @@ The full **STM32CubeF3** MCU package is available [here](https://github.com/STMi If you have any issue with the **software content** of this repository, you can file an issue [here](https://github.com/STMicroelectronics/stm32f3xx_hal_driver/issues/new/choose). -For any other question related to the product, the tools, the environment, you can submit a topic on the [ST Community/STM32 MCUs forum](https://community.st.com/s/group/0F90X000000AXsASAW/stm32-mcus). +For any other question related to the product, the tools, the environment, you can submit a topic on the [ST Community/STM32 MCUs forum](https://community.st.com/s/group/0F90X000000AXsASAW/stm32-mcus). \ No newline at end of file diff --git a/system/Drivers/STM32F3xx_HAL_Driver/Release_Notes.html b/system/Drivers/STM32F3xx_HAL_Driver/Release_Notes.html index cc683a73aa..9b30290ae3 100644 --- a/system/Drivers/STM32F3xx_HAL_Driver/Release_Notes.html +++ b/system/Drivers/STM32F3xx_HAL_Driver/Release_Notes.html @@ -39,14 +39,92 @@

Purpose

Update History

- +

Main Changes

    -
  • General updates to fix known defects and implementation enhancements.
    • +
  • General updates to fix known defects and enhancements implementation.
    • +
  • HAL code quality enhancement for MISRA-C.

Contents

    +
  • HAL Generic +
      +
    • Fixed the TIM1 timebase initialization sequence by registering the callback before starting the timer.
      • +
    • +
  • HAL ADC +
      +
    • Fix __LL_ADC_DECIMAL_NB_TO_CHANNEL() to return values consistent with LL_ADC_CHANNEL_x macros.
      • +
    • Fix ADC overrun interrupt handling behavior.
      • +
    • +
  • HAL CAN +
      +
    • Avoid losing the FOVR0 or FULL0 status by using a direct assignment.
      • +
    • +
  • HAL I2C +
      +
    • Update function HAL_I2C_IsDeviceReady() to take into account the number of trials.
      • +
    • +
  • HAL I2S +
      +
    • Fix the HAL_I2SEx_TransmitReceive(), HAL_I2SEx_TransmitReceive_DMA() and HAL_I2SEx_TransmitReceive_IT() documentation to correctly state that the Size parameter represents the number of data frames.
      • +
    • +
  • HAL/LL HRTIM +
      +
    • Align the HRTIM_Deadtime_Prescaler_Ratio macro comments with the reference manual.
      • +
    • Fix the HRTIM_Deadtime_Prescaler_Ratio defines.
      • +
    • +
  • HAL/LL RTC +
      +
    • Add an explicit cast in RTC_ByteToBcd2() to avoid an implicit narrowing conversion warning.
      • +
    • +
  • HAL/LL SPI +
      +
    • Add a note to clarify the behavior of HAL_SPI_Receive() in master mode.
      • +
    • Avoid a buffer overflow in SPI_WaitFifoStateUntilTimeout().
      • +
    • Add units to physical measurements in the driver documentation.
      • +
    • Check the data size before changing the state in the reception API.
      • +
    • Update function HAL_I2C_IsDeviceReady() to take into account the number of trials.
      • +
    • +
  • HAL/LL TIM +
      +
    • Fix the build error when TIM18 and TIM19 are enabled for STM32F373xx and STM32F30x devices.
      • +
    • Fix the update flag (UIF) clearing in TIM_Base_SetConfig().
      • +
    • Update TIM_CCER_CCxE_MASK to support the internal TIM Channel5 and Channel6.
      • +
    • Fix the complementary channel being systematically disabled by TIM_OCx_SetConfig().
      • +
    • Add a condition to define the legacy macros LL_TIM_OCMODE_ASSYMMETRIC_PWM1 and LL_TIM_OCMODE_ASSYMMETRIC_PWM2 only if the TIM_CCMR1_OC1M_3 bit register is present.
      • +
    • +
  • HAL/LL USB +
      +
    • Fix the SA0035 USB driver buffer overflow issue.
      • +
    • +
  • HAL UART +
      +
    • Provide the accurate position in RxEventCallback when Reception-to-Idle mode is used with DMA and the interrupt processing is delayed.
      • +
    • Fix the transfer count in the DMA linked list.
      • +
    • Remove the __HAL_UART_DISABLE() call from the HAL_UART_DeInit() API.
      • +
    • Correct references to HAL_UARTEx_WakeupCallback and the HAL_UART_WAKEUP_CB_ID define according to series capabilities.
      • +
    • Fix the transfer count underflow when using polling mode.
      • +
    • Add the HAL_UART_RXEVENT_IDLE event notification when using HAL_UARTEx_ReceiveToIdle_DMA() with circular DMA, even when it occurs just after the transfer complete event.
      • +
    • Correct the DMA Rx abort procedure impact on an ongoing Tx transfer in polling mode.
      • +
    • Align the UART baud rate macro definitions between LL and HAL.
      • +
    • +
  • HAL SMARTCARD +
      +
    • Update the configuration sequence to better fit SMARTCARD specifications.
      • +
    • +
+
+
+
+ +
+

Main Changes

+
    +
  • General updates to fix known defects and implementation enhancements.
    • +
+

Contents

+
  • HAL Generic update
    • Add missing call to UNUSED() macro to avoid compilation warnings related to the unused arguments for the following HAL drivers: ADC, PWR, RCC
      • @@ -152,12 +230,12 @@

      Contents

      -

      Main Changes

      +

      Main Changes

      • General updates to fix known defects and implementation enhancements.
      • HAL code quality enhancement for MISRA-C Rule-8.13 by adding const qualifiers
      -

      Contents

      +

      Contents

      • HAL Generic update
          @@ -289,11 +367,11 @@

          Contents

          -

          Main Changes

          +

          Main Changes

          • General updates to fix known defects and enhancements implementation.
          -

          Contents

          +

          Contents

          • HAL GPIO driver
              @@ -386,11 +464,11 @@

              Contents

              -

              Main Changes

              +

              Main Changes

              • General updates to fix known defects and enhancements implementation.
              -

              Contents

              +

              Contents

              • HAL driver update
                  @@ -614,11 +692,11 @@

                  Contents

                  -

                  Main Changes

                  +

                  Main Changes

                  • General updates to fix known defects and enhancements implementation
                  -

                  Contents

                  +

                  Contents

                  • HAL/LL GPIO update
                      @@ -656,7 +734,7 @@

                      Contents

                      -

                      Main Changes

                      +

                      Main Changes

                      • General updates to fix known defects and enhancements implementation
                      • Add support of HAL callback registration feature
                        • @@ -922,7 +1000,7 @@

                        Main Changes

                        -

                        Main Changes

                        +

                        Main Changes

                        • Maintenance release to fix known defects and enhancements implementation
                        • Generic drivers changes
                          • @@ -1018,7 +1096,7 @@

                          Main Changes

                          -

                          Main Changes

                          +

                          Main Changes

                          • General updates to fix known defects and enhancements implementation
                          • HAL Drivers changes
                            • @@ -1119,7 +1197,7 @@

                            Main Changes

                            -

                            Main Changes

                            +

                            Main Changes

                            • Maintenance release to fix known defects and enhancements implementation
                            • Generic drivers changes
                              • @@ -1258,7 +1336,7 @@

                              Main Changes

                              -

                              Main Changes

                              +

                              Main Changes

                              • Maintenance release to fix known defects and enhancements implementation
                              • HAL Drivers changes
                                • @@ -1470,7 +1548,7 @@

                                Main Changes

                                -

                                Main Changes

                                +

                                Main Changes

                                • First official release supporting the Low Level drivers for the STM32F3xx series:
                                    @@ -1556,7 +1634,7 @@

                                    Main Changes

                                    -

                                    Main Changes

                                    +

                                    Main Changes

                                    • Maintenance release to fix known defects and enhancements implementation.
                                    • HAL generic @@ -1703,7 +1781,7 @@

                                      Main Changes

                                      -

                                      Main Changes

                                      +

                                      Main Changes

                                      • Performed HAL API alignment (macros/functions/constants renaming).
                                      • HAL generic @@ -1966,7 +2044,7 @@

                                        Main Changes

                                        -

                                        Main Changes

                                        +

                                        Main Changes

                                        • Fixed compilation warnings reported by TrueSTUDIO and SW4STM32 toolchains.
                                        @@ -1975,7 +2053,7 @@

                                        Main Changes

                                        -

                                        Main Changes

                                        +

                                        Main Changes

                                        • First official release of STM32F3xx HAL drivers for STM32F303xE, STM32F302xE and STM32F398xx devices.
                                        • HAL generic update @@ -2028,7 +2106,7 @@

                                          Main Changes

                                          -

                                          Main Changes

                                          +

                                          Main Changes

                                          • HAL generic update
                                              @@ -2167,7 +2245,7 @@

                                              Main Changes

                                              -

                                              Main Changes

                                              +

                                              Main Changes

                                              • HAL generic update
                                                  @@ -2281,7 +2359,7 @@

                                                  Main Changes

                                                  -

                                                  Main Changes

                                                  +

                                                  Main Changes

                                                  • First official release of STM32F3xx HAL drivers for STM32F301x6/x8, STM32F302x6/x8, STM32F302xB/xC, STM32F303x6/x8, STM32F373xB/xC, STM32F334x4/x6/x8, STM32F318xx, STM32F328xx, STM32F358xx and STM32F378xx devices.
                                                  diff --git a/system/Drivers/STM32F3xx_HAL_Driver/SW_Security_Level.md b/system/Drivers/STM32F3xx_HAL_Driver/SW_Security_Level.md new file mode 100644 index 0000000000..cc426970fe --- /dev/null +++ b/system/Drivers/STM32F3xx_HAL_Driver/SW_Security_Level.md @@ -0,0 +1,47 @@ + + +## Copyright (c) 2026 STMicroelectronics. +## All rights reserved +
                                                  +
                                                  + +## SW Security Classification + +[STM32Trust software security policies](https://wiki.st.com/stm32mcu/wiki/Security:STM32Trust_software_security_policies) define four levels of SW Security classification, each level defines a set of security policies for the applicable SW. + +| SW | SW Security Level +|:--------- |:-------| +| **STM32F3xx HAL Driver** | Medium| + + +
                                                  + +## IMPORTANT SECURITY NOTICE + +The STMicroelectronics group of companies (ST) places a high value on product security, which is why the ST product(s) identified in this documentation may be certified by various security certification bodies and/or may implement our own security measures as set forth herein. However, no level of security certification and/or built-in security measures can guarantee that ST products are resistant to all forms of attacks. As such, it is the responsibility of each of ST's customers to determine if the level of security provided in an ST product meets the customer needs both in relation to the ST product alone, as well as when combined with other components and/or software for the customer end product or application. In particular, take note that: + +- ST products may have been certified by one or more security certification bodies, such as Platform Security Architecture (www.psacertified.org) and/or Security Evaluation standard for IoT Platforms (www.trustcb.com). For details concerning whether the ST product(s) referenced herein have received security certification along with the level and current status of such certification, either visit the relevant certification standards website or go to the relevant product page on www.st.com for the most up to date information. As the status and/or level of security certification for an ST product can change from time to time, customers should re-check security certification status/level as needed. If an ST product is not shown to be certified under a particular security standard, customers should not assume it is certified. + +- Certification bodies have the right to evaluate, grant and revoke security certification in relation to ST products. These certification bodies are therefore independently responsible for granting or revoking security certification for an ST product, and ST does not take any responsibility for mistakes, evaluations, assessments, testing, or other activity carried out by the certification body with respect to any ST product. + +- Industry-based cryptographic algorithms (such as AES, DES, or MD5) and other open standard technologies which may be used in conjunction with an ST product are based on standards which were not developed by ST. ST does not take responsibility for any flaws in such cryptographic algorithms or open technologies or for any methods which have been or may be developed to bypass, decrypt or crack such algorithms or technologies. + +- While robust security testing may be done, no level of certification can absolutely guarantee protections against all attacks, including, for example, against advanced attacks which have not been tested for, against new or unidentified forms of attack, or against any form of attack when using an ST product outside of its specification or intended use, or in conjunction with other components or software which are used by customer to create their end product or application. ST is not responsible for resistance against such attacks. As such, regardless of the incorporated security features and/or any information or support that may be provided by ST, each customer is solely responsible for determining if the level of attacks tested for meets their needs, both in relation to the ST product alone and when incorporated into a customer end product or application. + +- All security features of ST products (inclusive of any hardware, software, documentation, and the like), including but not limited to any enhanced security features added by ST, are provided on an "AS IS" BASIS. + +AS SUCH, TO THE EXTENT PERMITTED BY APPLICABLE LAW, ST DISCLAIMS ALL WARRANTIES, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, unless the applicable written and signed contract terms specifically provide otherwise. + +
                                                  + +## IMPORTANT NOTICE - READ CAREFULLY + +STMicroelectronics NV and its subsidiaries ("ST") reserve the right to make changes, corrections, enhancements, modifications, and improvements to ST products and/or to this document at any time without notice. Purchasers should obtain the latest relevant information on ST products before placing orders. ST products are sold pursuant to ST's terms and conditions of sale in place at the time of order acknowledgment. + +Purchasers are solely responsible for the choice, selection, and use of ST products and ST assumes no liability for application assistance or the design of purchasers' products. +No license, express or implied, to any intellectual property right is granted by ST herein. +Resale of ST products with provisions different from the information set forth herein shall void any warranty granted by ST for such product. +ST and the ST logo are trademarks of ST. For additional information about ST trademarks, refer to www.st.com/trademarks. All other product or service names are the property of their respective owners. +Information in this document supersedes and replaces information previously supplied in any prior versions of this document. + +Copyright (c) 2026 STMicroelectronics - All rights reserved \ No newline at end of file diff --git a/system/Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal.c b/system/Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal.c index ca88b33d29..9848aad52c 100644 --- a/system/Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal.c +++ b/system/Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal.c @@ -52,11 +52,11 @@ * @{ */ /** - * @brief STM32F3xx HAL Driver version number V1.5.7 + * @brief STM32F3xx HAL Driver version number V1.5.9 */ #define __STM32F3xx_HAL_VERSION_MAIN (0x01U) /*!< [31:24] main version */ #define __STM32F3xx_HAL_VERSION_SUB1 (0x05U) /*!< [23:16] sub1 version */ -#define __STM32F3xx_HAL_VERSION_SUB2 (0x08U) /*!< [15:8] sub2 version */ +#define __STM32F3xx_HAL_VERSION_SUB2 (0x09U) /*!< [15:8] sub2 version */ #define __STM32F3xx_HAL_VERSION_RC (0x00U) /*!< [7:0] release candidate */ #define __STM32F3xx_HAL_VERSION ((__STM32F3xx_HAL_VERSION_MAIN << 24U)\ |(__STM32F3xx_HAL_VERSION_SUB1 << 16U)\ diff --git a/system/Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_adc_ex.c b/system/Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_adc_ex.c index a75c7350fb..b82bfb00f4 100644 --- a/system/Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_adc_ex.c +++ b/system/Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_adc_ex.c @@ -2134,14 +2134,13 @@ HAL_StatusTypeDef HAL_ADC_Start_IT(ADC_HandleTypeDef* hadc) break; } - /* If overrun is set to overwrite previous data (default setting), */ - /* overrun interrupt is not activated (overrun event is not considered */ - /* as an error). */ - /* (cf ref manual "Managing conversions without using the DMA and */ - /* without overrun ") */ + /* Enable ADC overrun interrupt */ + /* If hadc->Init.Overrun is set to ADC_OVR_DATA_PRESERVED, only then is + ADC_IT_OVR enabled; otherwise data overwrite is considered as normal + behavior and no CPU time is lost for a non-processed interruption */ if (hadc->Init.Overrun == ADC_OVR_DATA_PRESERVED) { - __HAL_ADC_DISABLE_IT(hadc, ADC_IT_OVR); + __HAL_ADC_ENABLE_IT(hadc, ADC_IT_OVR); } /* Enable conversion of regular group. */ @@ -2489,8 +2488,8 @@ HAL_StatusTypeDef HAL_ADC_Start_DMA(ADC_HandleTypeDef* hadc, uint32_t* pData, ui SET_BIT(hadc->Instance->CFGR, ADC_CFGR_DMAEN); /* Start the DMA channel */ - HAL_DMA_Start_IT(hadc->DMA_Handle, (uint32_t)&hadc->Instance->DR, (uint32_t)pData, Length); - + tmp_hal_status = HAL_DMA_Start_IT(hadc->DMA_Handle, (uint32_t)&hadc->Instance->DR, (uint32_t)pData, Length); + /* Enable conversion of regular group. */ /* If software start has been selected, conversion starts immediately.*/ /* If external trigger has been selected, conversion will start at */ @@ -2609,7 +2608,7 @@ HAL_StatusTypeDef HAL_ADC_Start_DMA(ADC_HandleTypeDef* hadc, uint32_t* pData, ui hadc->Instance->CR2 |= ADC_CR2_DMA; /* Start the DMA channel */ - HAL_DMA_Start_IT(hadc->DMA_Handle, (uint32_t)&hadc->Instance->DR, (uint32_t)pData, Length); + tmp_hal_status = HAL_DMA_Start_IT(hadc->DMA_Handle, (uint32_t)&hadc->Instance->DR, (uint32_t)pData, Length); /* Enable conversion of regular group. */ /* If software start has been selected, conversion starts immediately. */ @@ -4677,7 +4676,7 @@ HAL_StatusTypeDef HAL_ADCEx_MultiModeStart_DMA(ADC_HandleTypeDef* hadc, uint32_t __HAL_ADC_ENABLE_IT(hadc, ADC_IT_OVR); /* Start the DMA channel */ - HAL_DMA_Start_IT(hadc->DMA_Handle, (uint32_t)&tmpADC_Common->CDR, (uint32_t)pData, Length); + tmp_hal_status = HAL_DMA_Start_IT(hadc->DMA_Handle, (uint32_t)&tmpADC_Common->CDR, (uint32_t)pData, Length); /* Enable conversion of regular group. */ /* If software start has been selected, conversion starts immediately. */ @@ -4822,8 +4821,8 @@ HAL_StatusTypeDef HAL_ADCEx_MultiModeStop_DMA(ADC_HandleTypeDef* hadc) else { /* In case of error, attempt to disable ADC instances anyway */ - ADC_Disable(hadc); - ADC_Disable(&tmphadcSlave); + (void)ADC_Disable(hadc); + (void)ADC_Disable(&tmphadcSlave); /* Update ADC state machine (ADC master) to error */ SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL); @@ -5225,7 +5224,7 @@ HAL_StatusTypeDef HAL_ADCEx_RegularStop_DMA(ADC_HandleTypeDef* hadc) } else { - ADC_Disable(hadc); + (void)ADC_Disable(hadc); } /* Check if ADC is effectively disabled */ @@ -5394,8 +5393,8 @@ HAL_StatusTypeDef HAL_ADCEx_RegularMultiModeStop_DMA(ADC_HandleTypeDef* hadc) else { /* In case of error, attempt to disable ADC instances anyway */ - ADC_Disable(hadc); - ADC_Disable(&tmphadcSlave); + (void)ADC_Disable(hadc); + (void)ADC_Disable(&tmphadcSlave); /* Update ADC state machine (ADC master) to error */ SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL); @@ -6182,8 +6181,10 @@ HAL_StatusTypeDef HAL_ADCEx_InjectedConfigChannel(ADC_HandleTypeDef* hadc, ADC_I ADC_JSQR_RK(sConfigInjected->InjectedChannel, sConfigInjected->InjectedRank) ); /* Decrease channel count after setting into temporary JSQR variable */ - hadc->InjectionConfig.ChannelCount --; - + if (hadc->InjectionConfig.ChannelCount > 0U) + { + hadc->InjectionConfig.ChannelCount --; + } /* 3. End of context setting: If last channel set, then write context */ /* into register JSQR and make it enter into queue */ if (hadc->InjectionConfig.ChannelCount == 0U) diff --git a/system/Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c b/system/Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c index f6eda902d7..2f68c98451 100644 --- a/system/Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c +++ b/system/Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c @@ -840,7 +840,7 @@ HAL_StatusTypeDef HAL_CAN_UnRegisterCallback(CAN_HandleTypeDef *hcan, HAL_CAN_Ca HAL_StatusTypeDef HAL_CAN_ConfigFilter(CAN_HandleTypeDef *hcan, const CAN_FilterTypeDef *sFilterConfig) { uint32_t filternbrbitpos; - CAN_TypeDef *can_ip = hcan->Instance; + CAN_TypeDef *can_ip; HAL_CAN_StateTypeDef state = hcan->State; if ((state == HAL_CAN_STATE_READY) || @@ -857,6 +857,7 @@ HAL_StatusTypeDef HAL_CAN_ConfigFilter(CAN_HandleTypeDef *hcan, const CAN_Filter assert_param(IS_CAN_FILTER_ACTIVATION(sFilterConfig->FilterActivation)); /* CAN is single instance with 14 dedicated filters banks */ + can_ip = hcan->Instance; /* Check the parameters */ assert_param(IS_CAN_FILTER_BANK_SINGLE(sFilterConfig->FilterBank)); @@ -1199,8 +1200,8 @@ uint32_t HAL_CAN_IsSleepActive(const CAN_HandleTypeDef *hcan) * @param pHeader pointer to a CAN_TxHeaderTypeDef structure. * @param aData array containing the payload of the Tx frame. * @param pTxMailbox pointer to a variable where the function will return - * the TxMailbox used to store the Tx message. - * This parameter can be a value of @arg CAN_Tx_Mailboxes. + * the TxMailbox used to store the Tx message, + * with a value of @arg CAN_Tx_Mailboxes. * @retval HAL status */ HAL_StatusTypeDef HAL_CAN_AddTxMessage(CAN_HandleTypeDef *hcan, const CAN_TxHeaderTypeDef *pHeader, @@ -1533,12 +1534,12 @@ HAL_StatusTypeDef HAL_CAN_GetRxMessage(CAN_HandleTypeDef *hcan, uint32_t RxFifo, if (RxFifo == CAN_RX_FIFO0) /* Rx element is assigned to Rx FIFO 0 */ { /* Release RX FIFO 0 */ - SET_BIT(hcan->Instance->RF0R, CAN_RF0R_RFOM0); + hcan->Instance->RF0R = CAN_RF0R_RFOM0; } else /* Rx element is assigned to Rx FIFO 1 */ { /* Release RX FIFO 1 */ - SET_BIT(hcan->Instance->RF1R, CAN_RF1R_RFOM1); + hcan->Instance->RF1R = CAN_RF1R_RFOM1; } /* Return function status */ diff --git a/system/Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_crc.c b/system/Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_crc.c index 8701b61dd7..dedeb71735 100644 --- a/system/Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_crc.c +++ b/system/Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_crc.c @@ -64,8 +64,8 @@ /** @defgroup CRC_Private_Functions CRC Private Functions * @{ */ -static uint32_t CRC_Handle_8(CRC_HandleTypeDef *hcrc, uint8_t pBuffer[], uint32_t BufferLength); -static uint32_t CRC_Handle_16(CRC_HandleTypeDef *hcrc, uint16_t pBuffer[], uint32_t BufferLength); +static uint32_t CRC_Handle_8(CRC_HandleTypeDef *hcrc, uint8_t const pBuffer[], uint32_t BufferLength); +static uint32_t CRC_Handle_16(CRC_HandleTypeDef *hcrc, uint16_t const pBuffer[], uint32_t BufferLength); /** * @} */ @@ -284,7 +284,7 @@ __weak void HAL_CRC_MspDeInit(CRC_HandleTypeDef *hcrc) * handle field hcrc->InputDataFormat. * @retval uint32_t CRC (returned value LSBs for CRC shorter than 32 bits) */ -uint32_t HAL_CRC_Accumulate(CRC_HandleTypeDef *hcrc, uint32_t pBuffer[], uint32_t BufferLength) +uint32_t HAL_CRC_Accumulate(CRC_HandleTypeDef *hcrc, const uint32_t pBuffer[], uint32_t BufferLength) { uint32_t index; /* CRC input data buffer index */ uint32_t temp = 0U; /* CRC output (read from hcrc->Instance->DR register) */ @@ -304,11 +304,12 @@ uint32_t HAL_CRC_Accumulate(CRC_HandleTypeDef *hcrc, uint32_t pBuffer[], uint32_ break; case CRC_INPUTDATA_FORMAT_BYTES: - temp = CRC_Handle_8(hcrc, (uint8_t *)pBuffer, BufferLength); + temp = CRC_Handle_8(hcrc, (uint8_t const *)pBuffer, BufferLength); break; case CRC_INPUTDATA_FORMAT_HALFWORDS: - temp = CRC_Handle_16(hcrc, (uint16_t *)(void *)pBuffer, BufferLength); /* Derogation MisraC2012 R.11.5 */ + temp = + CRC_Handle_16(hcrc, (uint16_t const *)(void const *)pBuffer, BufferLength); /* Derogation MisraC2012 R.11.5 */ break; default: break; @@ -336,7 +337,7 @@ uint32_t HAL_CRC_Accumulate(CRC_HandleTypeDef *hcrc, uint32_t pBuffer[], uint32_ * handle field hcrc->InputDataFormat. * @retval uint32_t CRC (returned value LSBs for CRC shorter than 32 bits) */ -uint32_t HAL_CRC_Calculate(CRC_HandleTypeDef *hcrc, uint32_t pBuffer[], uint32_t BufferLength) +uint32_t HAL_CRC_Calculate(CRC_HandleTypeDef *hcrc, const uint32_t pBuffer[], uint32_t BufferLength) { uint32_t index; /* CRC input data buffer index */ uint32_t temp = 0U; /* CRC output (read from hcrc->Instance->DR register) */ @@ -361,12 +362,13 @@ uint32_t HAL_CRC_Calculate(CRC_HandleTypeDef *hcrc, uint32_t pBuffer[], uint32_t case CRC_INPUTDATA_FORMAT_BYTES: /* Specific 8-bit input data handling */ - temp = CRC_Handle_8(hcrc, (uint8_t *)pBuffer, BufferLength); + temp = CRC_Handle_8(hcrc, (uint8_t const *)pBuffer, BufferLength); break; case CRC_INPUTDATA_FORMAT_HALFWORDS: /* Specific 16-bit input data handling */ - temp = CRC_Handle_16(hcrc, (uint16_t *)(void *)pBuffer, BufferLength); /* Derogation MisraC2012 R.11.5 */ + temp = + CRC_Handle_16(hcrc, (uint16_t const *)(void const *)pBuffer, BufferLength); /* Derogation MisraC2012 R.11.5 */ break; default: @@ -429,7 +431,7 @@ HAL_CRC_StateTypeDef HAL_CRC_GetState(const CRC_HandleTypeDef *hcrc) * @param BufferLength input data buffer length * @retval uint32_t CRC (returned value LSBs for CRC shorter than 32 bits) */ -static uint32_t CRC_Handle_8(CRC_HandleTypeDef *hcrc, uint8_t pBuffer[], uint32_t BufferLength) +static uint32_t CRC_Handle_8(CRC_HandleTypeDef *hcrc, uint8_t const pBuffer[], uint32_t BufferLength) { uint32_t i; /* input data buffer index */ uint16_t data; @@ -452,13 +454,13 @@ static uint32_t CRC_Handle_8(CRC_HandleTypeDef *hcrc, uint8_t pBuffer[], uint32_ { *(__IO uint8_t *)(__IO void *)(&hcrc->Instance->DR) = pBuffer[4U * i]; /* Derogation MisraC2012 R.11.5 */ } - if ((BufferLength % 4U) == 2U) + else if ((BufferLength % 4U) == 2U) { data = ((uint16_t)(pBuffer[4U * i]) << 8U) | (uint16_t)pBuffer[(4U * i) + 1U]; pReg = (__IO uint16_t *)(__IO void *)(&hcrc->Instance->DR); /* Derogation MisraC2012 R.11.5 */ *pReg = data; } - if ((BufferLength % 4U) == 3U) + else if ((BufferLength % 4U) == 3U) { data = ((uint16_t)(pBuffer[4U * i]) << 8U) | (uint16_t)pBuffer[(4U * i) + 1U]; pReg = (__IO uint16_t *)(__IO void *)(&hcrc->Instance->DR); /* Derogation MisraC2012 R.11.5 */ @@ -466,6 +468,10 @@ static uint32_t CRC_Handle_8(CRC_HandleTypeDef *hcrc, uint8_t pBuffer[], uint32_ *(__IO uint8_t *)(__IO void *)(&hcrc->Instance->DR) = pBuffer[(4U * i) + 2U]; /* Derogation MisraC2012 R.11.5 */ } + else + { + /* Nothing to do */ + } } /* Return the CRC computed value */ @@ -480,7 +486,7 @@ static uint32_t CRC_Handle_8(CRC_HandleTypeDef *hcrc, uint8_t pBuffer[], uint32_ * @param BufferLength input data buffer length * @retval uint32_t CRC (returned value LSBs for CRC shorter than 32 bits) */ -static uint32_t CRC_Handle_16(CRC_HandleTypeDef *hcrc, uint16_t pBuffer[], uint32_t BufferLength) +static uint32_t CRC_Handle_16(CRC_HandleTypeDef *hcrc, uint16_t const pBuffer[], uint32_t BufferLength) { uint32_t i; /* input data buffer index */ __IO uint16_t *pReg; diff --git a/system/Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dac_ex.c b/system/Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dac_ex.c index 11b100e5cb..4fae2f3e81 100644 --- a/system/Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dac_ex.c +++ b/system/Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dac_ex.c @@ -445,7 +445,7 @@ HAL_StatusTypeDef HAL_DAC_Start_DMA(DAC_HandleTypeDef* hdac, uint32_t Channel, u __HAL_DAC_ENABLE_IT(hdac, DAC_IT_DMAUDR1); /* Enable the DMA Channel */ - HAL_DMA_Start_IT(hdac->DMA_Handle1, (uint32_t)pData, tmpreg, Length); + (void)HAL_DMA_Start_IT(hdac->DMA_Handle1, (uint32_t)pData, tmpreg, Length); } else { @@ -453,7 +453,7 @@ HAL_StatusTypeDef HAL_DAC_Start_DMA(DAC_HandleTypeDef* hdac, uint32_t Channel, u __HAL_DAC_ENABLE_IT(hdac, DAC_IT_DMAUDR2); /* Enable the DMA Channel */ - HAL_DMA_Start_IT(hdac->DMA_Handle2, (uint32_t)pData, tmpreg, Length); + (void)HAL_DMA_Start_IT(hdac->DMA_Handle2, (uint32_t)pData, tmpreg, Length); } /* Process Unlocked */ @@ -540,7 +540,7 @@ HAL_StatusTypeDef HAL_DAC_Start_DMA(DAC_HandleTypeDef* hdac, uint32_t Channel, u __HAL_DAC_ENABLE_IT(hdac, DAC_IT_DMAUDR1); /* Enable the DMA Channel */ - HAL_DMA_Start_IT(hdac->DMA_Handle1, (uint32_t)pData, tmpreg, Length); + (void)HAL_DMA_Start_IT(hdac->DMA_Handle1, (uint32_t)pData, tmpreg, Length); /* Process Unlocked */ __HAL_UNLOCK(hdac); diff --git a/system/Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c b/system/Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c index 9fc21ee134..b93b14d1da 100644 --- a/system/Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c +++ b/system/Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c @@ -165,7 +165,7 @@ extern void FLASH_PageErase(uint32_t PageAddress); */ HAL_StatusTypeDef HAL_FLASH_Program(uint32_t TypeProgram, uint32_t Address, uint64_t Data) { - HAL_StatusTypeDef status = HAL_ERROR; + HAL_StatusTypeDef status; uint8_t index = 0U; uint8_t nbiterations = 0U; diff --git a/system/Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c b/system/Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c index 6abd00d42b..46e903e622 100644 --- a/system/Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c +++ b/system/Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c @@ -310,8 +310,8 @@ HAL_StatusTypeDef HAL_FLASHEx_Erase_IT(FLASH_EraseInitTypeDef *pEraseInit) HAL_StatusTypeDef HAL_FLASHEx_OBErase(void) { - uint8_t rdptmp = OB_RDP_LEVEL_0; - HAL_StatusTypeDef status = HAL_ERROR; + uint8_t rdptmp; + HAL_StatusTypeDef status; /* Get the actual read protection Option Byte value */ rdptmp = FLASH_OB_GetRDP(); @@ -519,15 +519,15 @@ static void FLASH_MassErase(void) static HAL_StatusTypeDef FLASH_OB_EnableWRP(uint32_t WriteProtectPage) { HAL_StatusTypeDef status = HAL_OK; - uint16_t WRP0_Data = 0xFFFFU; + uint16_t WRP0_Data; #if defined(OB_WRP1_WRP1) - uint16_t WRP1_Data = 0xFFFFU; + uint16_t WRP1_Data; #endif /* OB_WRP1_WRP1 */ #if defined(OB_WRP2_WRP2) - uint16_t WRP2_Data = 0xFFFFU; + uint16_t WRP2_Data; #endif /* OB_WRP2_WRP2 */ #if defined(OB_WRP3_WRP3) - uint16_t WRP3_Data = 0xFFFFU; + uint16_t WRP3_Data; #endif /* OB_WRP3_WRP3 */ /* Check the parameters */ @@ -631,15 +631,15 @@ static HAL_StatusTypeDef FLASH_OB_EnableWRP(uint32_t WriteProtectPage) static HAL_StatusTypeDef FLASH_OB_DisableWRP(uint32_t WriteProtectPage) { HAL_StatusTypeDef status = HAL_OK; - uint16_t WRP0_Data = 0xFFFFU; + uint16_t WRP0_Data; #if defined(OB_WRP1_WRP1) - uint16_t WRP1_Data = 0xFFFFU; + uint16_t WRP1_Data; #endif /* OB_WRP1_WRP1 */ #if defined(OB_WRP2_WRP2) - uint16_t WRP2_Data = 0xFFFFU; + uint16_t WRP2_Data; #endif /* OB_WRP2_WRP2 */ #if defined(OB_WRP3_WRP3) - uint16_t WRP3_Data = 0xFFFFU; + uint16_t WRP3_Data; #endif /* OB_WRP3_WRP3 */ /* Check the parameters */ @@ -845,7 +845,7 @@ static HAL_StatusTypeDef FLASH_OB_UserConfig(uint8_t UserConfig) */ static HAL_StatusTypeDef FLASH_OB_ProgramData(uint32_t Address, uint8_t Data) { - HAL_StatusTypeDef status = HAL_ERROR; + HAL_StatusTypeDef status; /* Check the parameters */ assert_param(IS_OB_DATA_ADDRESS(Address)); diff --git a/system/Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_gpio.c b/system/Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_gpio.c index 8b95993c42..3e0e29f95b 100644 --- a/system/Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_gpio.c +++ b/system/Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_gpio.c @@ -170,7 +170,7 @@ */ void HAL_GPIO_Init(GPIO_TypeDef *GPIOx, GPIO_InitTypeDef *GPIO_Init) { - uint32_t position = 0x00u; + uint32_t position = 0x00U; uint32_t iocurrent; uint32_t temp; @@ -180,12 +180,12 @@ void HAL_GPIO_Init(GPIO_TypeDef *GPIOx, GPIO_InitTypeDef *GPIO_Init) assert_param(IS_GPIO_MODE(GPIO_Init->Mode)); /* Configure the port pins */ - while (((GPIO_Init->Pin) >> position) != 0x00u) + while (((GPIO_Init->Pin) >> position) != 0x00U) { /* Get current io position */ - iocurrent = (GPIO_Init->Pin) & (1uL << position); + iocurrent = (GPIO_Init->Pin) & (1UL << position); - if (iocurrent != 0x00u) + if (iocurrent != 0x00U) { /*--------------------- GPIO Mode Configuration ------------------------*/ /* In case of Output or Alternate function mode selection */ @@ -195,8 +195,8 @@ void HAL_GPIO_Init(GPIO_TypeDef *GPIOx, GPIO_InitTypeDef *GPIO_Init) assert_param(IS_GPIO_SPEED(GPIO_Init->Speed)); /* Configure the IO Speed */ temp = GPIOx->OSPEEDR; - temp &= ~(GPIO_OSPEEDER_OSPEEDR0 << (position * 2u)); - temp |= (GPIO_Init->Speed << (position * 2u)); + temp &= ~(GPIO_OSPEEDER_OSPEEDR0 << (position * 2U)); + temp |= (GPIO_Init->Speed << (position * 2U)); GPIOx->OSPEEDR = temp; /* Configure the IO Output Type */ @@ -213,8 +213,8 @@ void HAL_GPIO_Init(GPIO_TypeDef *GPIOx, GPIO_InitTypeDef *GPIO_Init) /* Activate the Pull-up or Pull down resistor for the current IO */ temp = GPIOx->PUPDR; - temp &= ~(GPIO_PUPDR_PUPDR0 << (position * 2u)); - temp |= ((GPIO_Init->Pull) << (position * 2u)); + temp &= ~(GPIO_PUPDR_PUPDR0 << (position * 2U)); + temp |= ((GPIO_Init->Pull) << (position * 2U)); GPIOx->PUPDR = temp; } @@ -227,34 +227,34 @@ void HAL_GPIO_Init(GPIO_TypeDef *GPIOx, GPIO_InitTypeDef *GPIO_Init) assert_param(IS_GPIO_AF(GPIO_Init->Alternate)); /* Configure Alternate function mapped with the current IO */ - temp = GPIOx->AFR[position >> 3u]; - temp &= ~(0xFu << ((position & 0x07u) * 4u)); - temp |= ((GPIO_Init->Alternate) << ((position & 0x07u) * 4u)); - GPIOx->AFR[position >> 3u] = temp; + temp = GPIOx->AFR[position >> 3U]; + temp &= ~(0xFUL << ((position & 0x07U) * 4U)); + temp |= ((GPIO_Init->Alternate) << ((position & 0x07U) * 4U)); + GPIOx->AFR[position >> 3U] = temp; } /* Configure IO Direction mode (Input, Output, Alternate or Analog) */ temp = GPIOx->MODER; - temp &= ~(GPIO_MODER_MODER0 << (position * 2u)); - temp |= ((GPIO_Init->Mode & GPIO_MODE) << (position * 2u)); + temp &= ~(GPIO_MODER_MODER0 << (position * 2U)); + temp |= ((GPIO_Init->Mode & GPIO_MODE) << (position * 2U)); GPIOx->MODER = temp; /*--------------------- EXTI Mode Configuration ------------------------*/ /* Configure the External Interrupt or event for the current IO */ - if((GPIO_Init->Mode & EXTI_MODE) != 0x00u) + if((GPIO_Init->Mode & EXTI_MODE) != 0x00U) { /* Enable SYSCFG Clock */ __HAL_RCC_SYSCFG_CLK_ENABLE(); - temp = SYSCFG->EXTICR[position >> 2u]; - temp &= ~(0x0FuL << (4u * (position & 0x03u))); - temp |= (GPIO_GET_INDEX(GPIOx) << (4u * (position & 0x03u))); - SYSCFG->EXTICR[position >> 2u] = temp; + temp = SYSCFG->EXTICR[position >> 2U]; + temp &= ~(0x0FUL << (4U * (position & 0x03U))); + temp |= (GPIO_GET_INDEX(GPIOx) << (4U * (position & 0x03U))); + SYSCFG->EXTICR[position >> 2U] = temp; /* Clear Rising Falling edge configuration */ temp = EXTI->RTSR; temp &= ~(iocurrent); - if((GPIO_Init->Mode & TRIGGER_RISING) != 0x00u) + if((GPIO_Init->Mode & TRIGGER_RISING) != 0x00U) { temp |= iocurrent; } @@ -262,7 +262,7 @@ void HAL_GPIO_Init(GPIO_TypeDef *GPIOx, GPIO_InitTypeDef *GPIO_Init) temp = EXTI->FTSR; temp &= ~(iocurrent); - if((GPIO_Init->Mode & TRIGGER_FALLING) != 0x00u) + if((GPIO_Init->Mode & TRIGGER_FALLING) != 0x00U) { temp |= iocurrent; } @@ -270,7 +270,7 @@ void HAL_GPIO_Init(GPIO_TypeDef *GPIOx, GPIO_InitTypeDef *GPIO_Init) temp = EXTI->EMR; temp &= ~(iocurrent); - if((GPIO_Init->Mode & EXTI_EVT) != 0x00u) + if((GPIO_Init->Mode & EXTI_EVT) != 0x00U) { temp |= iocurrent; } @@ -279,7 +279,7 @@ void HAL_GPIO_Init(GPIO_TypeDef *GPIOx, GPIO_InitTypeDef *GPIO_Init) /* Clear EXTI line configuration */ temp = EXTI->IMR; temp &= ~(iocurrent); - if((GPIO_Init->Mode & EXTI_IT) != 0x00u) + if((GPIO_Init->Mode & EXTI_IT) != 0x00U) { temp |= iocurrent; } @@ -300,7 +300,7 @@ void HAL_GPIO_Init(GPIO_TypeDef *GPIOx, GPIO_InitTypeDef *GPIO_Init) */ void HAL_GPIO_DeInit(GPIO_TypeDef *GPIOx, uint32_t GPIO_Pin) { - uint32_t position = 0x00u; + uint32_t position = 0x00U; uint32_t iocurrent; uint32_t tmp; @@ -309,19 +309,19 @@ void HAL_GPIO_DeInit(GPIO_TypeDef *GPIOx, uint32_t GPIO_Pin) assert_param(IS_GPIO_PIN(GPIO_Pin)); /* Configure the port pins */ - while ((GPIO_Pin >> position) != 0x00u) + while ((GPIO_Pin >> position) != 0x00U) { /* Get current io position */ - iocurrent = (GPIO_Pin) & (1uL << position); + iocurrent = (GPIO_Pin) & (1UL << position); - if (iocurrent != 0x00u) + if (iocurrent != 0x00U) { /*------------------------- EXTI Mode Configuration --------------------*/ /* Clear the External Interrupt or Event for the current IO */ - tmp = SYSCFG->EXTICR[position >> 2u]; - tmp &= (0x0FuL << (4u * (position & 0x03u))); - if (tmp == (GPIO_GET_INDEX(GPIOx) << (4u * (position & 0x03u)))) + tmp = SYSCFG->EXTICR[position >> 2U]; + tmp &= (0x0FUL << (4U * (position & 0x03U))); + if (tmp == (GPIO_GET_INDEX(GPIOx) << (4U * (position & 0x03U)))) { /* Clear EXTI line configuration */ EXTI->IMR &= ~((uint32_t)iocurrent); @@ -332,25 +332,25 @@ void HAL_GPIO_DeInit(GPIO_TypeDef *GPIOx, uint32_t GPIO_Pin) EXTI->RTSR &= ~((uint32_t)iocurrent); /* Configure the External Interrupt or event for the current IO */ - tmp = 0x0FuL << (4u * (position & 0x03u)); - SYSCFG->EXTICR[position >> 2u] &= ~tmp; + tmp = 0x0FUL << (4U * (position & 0x03U)); + SYSCFG->EXTICR[position >> 2U] &= ~tmp; } /*------------------------- GPIO Mode Configuration --------------------*/ /* Configure IO Direction in Input Floating Mode */ - GPIOx->MODER &= ~(GPIO_MODER_MODER0 << (position * 2u)); + GPIOx->MODER &= ~(GPIO_MODER_MODER0 << (position * 2U)); /* Configure the default Alternate Function in current IO */ - GPIOx->AFR[position >> 3u] &= ~(0xFu << ((uint32_t)(position & 0x07u) * 4u)) ; + GPIOx->AFR[position >> 3U] &= ~(0xFUL << ((uint32_t)(position & 0x07U) * 4U)) ; /* Deactivate the Pull-up and Pull-down resistor for the current IO */ - GPIOx->PUPDR &= ~(GPIO_PUPDR_PUPDR0 << (position * 2u)); + GPIOx->PUPDR &= ~(GPIO_PUPDR_PUPDR0 << (position * 2U)); /* Configure the default value IO Output Type */ GPIOx->OTYPER &= ~(GPIO_OTYPER_OT_0 << position) ; /* Configure the default value for IO Speed */ - GPIOx->OSPEEDR &= ~(GPIO_OSPEEDER_OSPEEDR0 << (position * 2u)); + GPIOx->OSPEEDR &= ~(GPIO_OSPEEDER_OSPEEDR0 << (position * 2U)); } position++; @@ -481,7 +481,7 @@ HAL_StatusTypeDef HAL_GPIO_LockPin(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin) tmp = GPIOx->LCKR; /* read again in order to confirm lock is active */ - if((GPIOx->LCKR & GPIO_LCKR_LCKK) != 0x00u) + if((GPIOx->LCKR & GPIO_LCKR_LCKK) != 0x00U) { return HAL_OK; } @@ -499,7 +499,7 @@ HAL_StatusTypeDef HAL_GPIO_LockPin(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin) void HAL_GPIO_EXTI_IRQHandler(uint16_t GPIO_Pin) { /* EXTI line interrupt detected */ - if(__HAL_GPIO_EXTI_GET_IT(GPIO_Pin) != 0x00u) + if(__HAL_GPIO_EXTI_GET_IT(GPIO_Pin) != 0x00U) { __HAL_GPIO_EXTI_CLEAR_IT(GPIO_Pin); HAL_GPIO_EXTI_Callback(GPIO_Pin); diff --git a/system/Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_hrtim.c b/system/Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_hrtim.c index f11baa923d..3843c9fb40 100644 --- a/system/Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_hrtim.c +++ b/system/Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_hrtim.c @@ -439,62 +439,62 @@ static uint32_t TimerIdxToTimerId[] = /** @defgroup HRTIM_Private_Functions HRTIM Private Functions * @{ */ -static void HRTIM_MasterBase_Config(HRTIM_HandleTypeDef * hhrtim, - const HRTIM_TimeBaseCfgTypeDef * pTimeBaseCfg); +static void HRTIM_MasterBase_Config(HRTIM_HandleTypeDef *hhrtim, + const HRTIM_TimeBaseCfgTypeDef *pTimeBaseCfg); -static void HRTIM_TimingUnitBase_Config(HRTIM_HandleTypeDef * hhrtim, +static void HRTIM_TimingUnitBase_Config(HRTIM_HandleTypeDef *hhrtim, uint32_t TimerIdx, - const HRTIM_TimeBaseCfgTypeDef * pTimeBaseCfg); + const HRTIM_TimeBaseCfgTypeDef *pTimeBaseCfg); -static void HRTIM_MasterWaveform_Config(HRTIM_HandleTypeDef * hhrtim, - const HRTIM_TimerCfgTypeDef * pTimerCfg); +static void HRTIM_MasterWaveform_Config(HRTIM_HandleTypeDef *hhrtim, + const HRTIM_TimerCfgTypeDef *pTimerCfg); -static void HRTIM_TimingUnitWaveform_Config(HRTIM_HandleTypeDef * hhrtim, +static void HRTIM_TimingUnitWaveform_Config(HRTIM_HandleTypeDef *hhrtim, uint32_t TimerIdx, - const HRTIM_TimerCfgTypeDef * pTimerCfg); + const HRTIM_TimerCfgTypeDef *pTimerCfg); -static void HRTIM_CaptureUnitConfig(HRTIM_HandleTypeDef * hhrtim, +static void HRTIM_CaptureUnitConfig(HRTIM_HandleTypeDef *hhrtim, uint32_t TimerIdx, uint32_t CaptureUnit, uint32_t Event); -static void HRTIM_OutputConfig(HRTIM_HandleTypeDef * hhrtim, - uint32_t TimerIdx, - uint32_t Output, - const HRTIM_OutputCfgTypeDef * pOutputCfg); +static void HRTIM_OutputConfig(HRTIM_HandleTypeDef *hhrtim, + uint32_t TimerIdx, + uint32_t Output, + const HRTIM_OutputCfgTypeDef *pOutputCfg); -static void HRTIM_EventConfig(HRTIM_HandleTypeDef * hhrtim, +static void HRTIM_EventConfig(HRTIM_HandleTypeDef *hhrtim, uint32_t Event, - const HRTIM_EventCfgTypeDef * pEventCfg); + const HRTIM_EventCfgTypeDef *pEventCfg); -static void HRTIM_TIM_ResetConfig(HRTIM_HandleTypeDef * hhrtim, +static void HRTIM_TIM_ResetConfig(HRTIM_HandleTypeDef *hhrtim, uint32_t TimerIdx, uint32_t Event); -static uint32_t HRTIM_GetITFromOCMode(const HRTIM_HandleTypeDef * hhrtim, +static uint32_t HRTIM_GetITFromOCMode(const HRTIM_HandleTypeDef *hhrtim, uint32_t TimerIdx, uint32_t OCChannel); -static uint32_t HRTIM_GetDMAFromOCMode(const HRTIM_HandleTypeDef * hhrtim, +static uint32_t HRTIM_GetDMAFromOCMode(const HRTIM_HandleTypeDef *hhrtim, uint32_t TimerIdx, uint32_t OCChannel); -static DMA_HandleTypeDef * HRTIM_GetDMAHandleFromTimerIdx(const HRTIM_HandleTypeDef * hhrtim, - uint32_t TimerIdx); +static DMA_HandleTypeDef *HRTIM_GetDMAHandleFromTimerIdx(const HRTIM_HandleTypeDef *hhrtim, + uint32_t TimerIdx); -static uint32_t GetTimerIdxFromDMAHandle(const HRTIM_HandleTypeDef * hhrtim, - const DMA_HandleTypeDef * hdma); +static uint32_t GetTimerIdxFromDMAHandle(const HRTIM_HandleTypeDef *hhrtim, + const DMA_HandleTypeDef *hdma); -static void HRTIM_ForceRegistersUpdate(HRTIM_HandleTypeDef * hhrtim, - uint32_t TimerIdx); +static void HRTIM_ForceRegistersUpdate(HRTIM_HandleTypeDef *hhrtim, + uint32_t TimerIdx); -static void HRTIM_HRTIM_ISR(HRTIM_HandleTypeDef * hhrtim); +static void HRTIM_HRTIM_ISR(HRTIM_HandleTypeDef *hhrtim); -static void HRTIM_Master_ISR(HRTIM_HandleTypeDef * hhrtim); +static void HRTIM_Master_ISR(HRTIM_HandleTypeDef *hhrtim); -static void HRTIM_Timer_ISR(HRTIM_HandleTypeDef * hhrtim, - uint32_t TimerIdx); +static void HRTIM_Timer_ISR(HRTIM_HandleTypeDef *hhrtim, + uint32_t TimerIdx); static void HRTIM_DMAMasterCplt(DMA_HandleTypeDef *hdma); @@ -513,7 +513,7 @@ static void HRTIM_BurstDMACplt(DMA_HandleTypeDef *hdma); */ /** @defgroup HRTIM_Exported_Functions_Group1 Initialization and de-initialization functions - * @brief Initialization and Configuration functions + * @brief Initialization and Configuration functions @verbatim =============================================================================== ##### Initialization and Time Base Configuration functions ##### @@ -536,20 +536,20 @@ static void HRTIM_BurstDMACplt(DMA_HandleTypeDef *hdma); * @param hhrtim pointer to HAL HRTIM handle * @retval HAL status */ -HAL_StatusTypeDef HAL_HRTIM_Init(HRTIM_HandleTypeDef * hhrtim) +HAL_StatusTypeDef HAL_HRTIM_Init(HRTIM_HandleTypeDef *hhrtim) { uint8_t timer_idx; uint32_t hrtim_mcr; /* Check the HRTIM handle allocation */ - if(hhrtim == NULL) + if (hhrtim == NULL) { return HAL_ERROR; } /* Check the parameters */ assert_param(IS_HRTIM_ALL_INSTANCE(hhrtim->Instance)); - assert_param(IS_HRTIM_IT(hhrtim->Init.HRTIMInterruptResquests)); + assert_param(IS_HRTIM_IT(hhrtim->Init.HRTIMInterruptRequests)); #if (USE_HAL_HRTIM_REGISTER_CALLBACKS == 1) if (hhrtim->State == HAL_HRTIM_STATE_RESET) @@ -679,10 +679,10 @@ HAL_StatusTypeDef HAL_HRTIM_Init(HRTIM_HandleTypeDef * hhrtim) * @param hhrtim pointer to HAL HRTIM handle * @retval HAL status */ -HAL_StatusTypeDef HAL_HRTIM_DeInit (HRTIM_HandleTypeDef * hhrtim) +HAL_StatusTypeDef HAL_HRTIM_DeInit(HRTIM_HandleTypeDef *hhrtim) { /* Check the HRTIM handle allocation */ - if(hhrtim == NULL) + if (hhrtim == NULL) { return HAL_ERROR; } @@ -715,7 +715,7 @@ HAL_StatusTypeDef HAL_HRTIM_DeInit (HRTIM_HandleTypeDef * hhrtim) * @param hhrtim pointer to HAL HRTIM handle * @retval None */ -__weak void HAL_HRTIM_MspInit(HRTIM_HandleTypeDef * hhrtim) +__weak void HAL_HRTIM_MspInit(HRTIM_HandleTypeDef *hhrtim) { /* Prevent unused argument(s) compilation warning */ UNUSED(hhrtim); @@ -730,7 +730,7 @@ __weak void HAL_HRTIM_MspInit(HRTIM_HandleTypeDef * hhrtim) * @param hhrtim pointer to HAL HRTIM handle * @retval None */ -__weak void HAL_HRTIM_MspDeInit(HRTIM_HandleTypeDef * hhrtim) +__weak void HAL_HRTIM_MspDeInit(HRTIM_HandleTypeDef *hhrtim) { /* Prevent unused argument(s) compilation warning */ UNUSED(hhrtim); @@ -755,7 +755,7 @@ __weak void HAL_HRTIM_MspDeInit(HRTIM_HandleTypeDef * hhrtim) * within the HAL_HRTIM_PollForDLLCalibration function, just before * exiting the function. */ -HAL_StatusTypeDef HAL_HRTIM_DLLCalibrationStart(HRTIM_HandleTypeDef * hhrtim, +HAL_StatusTypeDef HAL_HRTIM_DLLCalibrationStart(HRTIM_HandleTypeDef *hhrtim, uint32_t CalibrationRate) { /* Check the parameters */ @@ -805,7 +805,7 @@ HAL_StatusTypeDef HAL_HRTIM_DLLCalibrationStart(HRTIM_HandleTypeDef * hhrtim, * interrupt is generated every time the calibration completes which * will significantly increases the overall interrupt rate. */ -HAL_StatusTypeDef HAL_HRTIM_DLLCalibrationStart_IT(HRTIM_HandleTypeDef * hhrtim, +HAL_StatusTypeDef HAL_HRTIM_DLLCalibrationStart_IT(HRTIM_HandleTypeDef *hhrtim, uint32_t CalibrationRate) { /* Check the parameters */ @@ -846,7 +846,7 @@ HAL_StatusTypeDef HAL_HRTIM_DLLCalibrationStart_IT(HRTIM_HandleTypeDef * hhrtim, * @param Timeout Timeout duration in millisecond * @retval HAL status */ -HAL_StatusTypeDef HAL_HRTIM_PollForDLLCalibration(HRTIM_HandleTypeDef * hhrtim, +HAL_StatusTypeDef HAL_HRTIM_PollForDLLCalibration(HRTIM_HandleTypeDef *hhrtim, uint32_t Timeout) { uint32_t tickstart; @@ -854,11 +854,11 @@ HAL_StatusTypeDef HAL_HRTIM_PollForDLLCalibration(HRTIM_HandleTypeDef * hhrtim, tickstart = HAL_GetTick(); /* Check End of conversion flag */ - while(__HAL_HRTIM_GET_FLAG(hhrtim, HRTIM_IT_DLLRDY) == (uint32_t)RESET) + while (__HAL_HRTIM_GET_FLAG(hhrtim, HRTIM_IT_DLLRDY) == (uint32_t)RESET) { if (Timeout != HAL_MAX_DELAY) { - if(((HAL_GetTick()-tickstart) > Timeout) || (Timeout == 0U)) + if (((HAL_GetTick() - tickstart) > Timeout) || (Timeout == 0U)) { hhrtim->State = HAL_HRTIM_STATE_ERROR; return HAL_TIMEOUT; @@ -897,16 +897,16 @@ HAL_StatusTypeDef HAL_HRTIM_PollForDLLCalibration(HRTIM_HandleTypeDef * hhrtim, */ HAL_StatusTypeDef HAL_HRTIM_TimeBaseConfig(HRTIM_HandleTypeDef *hhrtim, uint32_t TimerIdx, - const HRTIM_TimeBaseCfgTypeDef * pTimeBaseCfg) + const HRTIM_TimeBaseCfgTypeDef *pTimeBaseCfg) { /* Check the parameters */ assert_param(IS_HRTIM_TIMERINDEX(TimerIdx)); assert_param(IS_HRTIM_PRESCALERRATIO(pTimeBaseCfg->PrescalerRatio)); assert_param(IS_HRTIM_MODE(pTimeBaseCfg->Mode)); - if(hhrtim->State == HAL_HRTIM_STATE_BUSY) + if (hhrtim->State == HAL_HRTIM_STATE_BUSY) { - return HAL_BUSY; + return HAL_BUSY; } /* Set the HRTIM state */ @@ -934,7 +934,7 @@ HAL_StatusTypeDef HAL_HRTIM_TimeBaseConfig(HRTIM_HandleTypeDef *hhrtim, */ /** @defgroup HRTIM_Exported_Functions_Group2 Simple time base mode functions - * @brief Simple time base mode functions. + * @brief Simple time base mode functions. @verbatim =============================================================================== ##### Simple time base mode functions ##### @@ -966,10 +966,10 @@ HAL_StatusTypeDef HAL_HRTIM_TimeBaseConfig(HRTIM_HandleTypeDef *hhrtim, * @arg HRTIM_TIMERINDEX_TIMER_E for timer E * @retval HAL status */ -HAL_StatusTypeDef HAL_HRTIM_SimpleBaseStart(HRTIM_HandleTypeDef * hhrtim, - uint32_t TimerIdx) +HAL_StatusTypeDef HAL_HRTIM_SimpleBaseStart(HRTIM_HandleTypeDef *hhrtim, + uint32_t TimerIdx) { - /* Check the parameters */ + /* Check the parameters */ assert_param(IS_HRTIM_TIMERINDEX(TimerIdx)); /* Process Locked */ @@ -1001,10 +1001,10 @@ HAL_StatusTypeDef HAL_HRTIM_SimpleBaseStart(HRTIM_HandleTypeDef * hhrtim, * @arg HRTIM_TIMERINDEX_TIMER_E for timer E * @retval HAL status */ -HAL_StatusTypeDef HAL_HRTIM_SimpleBaseStop(HRTIM_HandleTypeDef * hhrtim, - uint32_t TimerIdx) +HAL_StatusTypeDef HAL_HRTIM_SimpleBaseStop(HRTIM_HandleTypeDef *hhrtim, + uint32_t TimerIdx) { - /* Check the parameters */ + /* Check the parameters */ assert_param(IS_HRTIM_TIMERINDEX(TimerIdx)); /* Process Locked */ @@ -1037,10 +1037,10 @@ HAL_StatusTypeDef HAL_HRTIM_SimpleBaseStop(HRTIM_HandleTypeDef * hhrtim, * @arg HRTIM_TIMERINDEX_TIMER_E for timer E * @retval HAL status */ -HAL_StatusTypeDef HAL_HRTIM_SimpleBaseStart_IT(HRTIM_HandleTypeDef * hhrtim, - uint32_t TimerIdx) +HAL_StatusTypeDef HAL_HRTIM_SimpleBaseStart_IT(HRTIM_HandleTypeDef *hhrtim, + uint32_t TimerIdx) { - /* Check the parameters */ + /* Check the parameters */ assert_param(IS_HRTIM_TIMERINDEX(TimerIdx)); /* Process Locked */ @@ -1083,10 +1083,10 @@ HAL_StatusTypeDef HAL_HRTIM_SimpleBaseStart_IT(HRTIM_HandleTypeDef * hhrtim, * @arg HRTIM_TIMERINDEX_TIMER_E for timer E * @retval HAL status */ -HAL_StatusTypeDef HAL_HRTIM_SimpleBaseStop_IT(HRTIM_HandleTypeDef * hhrtim, - uint32_t TimerIdx) +HAL_StatusTypeDef HAL_HRTIM_SimpleBaseStop_IT(HRTIM_HandleTypeDef *hhrtim, + uint32_t TimerIdx) { - /* Check the parameters */ + /* Check the parameters */ assert_param(IS_HRTIM_TIMERINDEX(TimerIdx)); /* Process Locked */ @@ -1132,24 +1132,24 @@ HAL_StatusTypeDef HAL_HRTIM_SimpleBaseStop_IT(HRTIM_HandleTypeDef * hhrtim, * @param Length The length of data items (data size) to be transferred * from source to destination */ -HAL_StatusTypeDef HAL_HRTIM_SimpleBaseStart_DMA(HRTIM_HandleTypeDef * hhrtim, - uint32_t TimerIdx, - uint32_t SrcAddr, - uint32_t DestAddr, - uint32_t Length) +HAL_StatusTypeDef HAL_HRTIM_SimpleBaseStart_DMA(HRTIM_HandleTypeDef *hhrtim, + uint32_t TimerIdx, + uint32_t SrcAddr, + uint32_t DestAddr, + uint32_t Length) { - DMA_HandleTypeDef * hdma; + DMA_HandleTypeDef *hdma; /* Check the parameters */ assert_param(IS_HRTIM_TIMERINDEX(TimerIdx)); - if(hhrtim->State == HAL_HRTIM_STATE_BUSY) + if (hhrtim->State == HAL_HRTIM_STATE_BUSY) { - return HAL_BUSY; + return HAL_BUSY; } - if(hhrtim->State == HAL_HRTIM_STATE_READY) + if (hhrtim->State == HAL_HRTIM_STATE_READY) { - if((SrcAddr == 0U ) || (DestAddr == 0U ) || (Length == 0U)) + if ((SrcAddr == 0U) || (DestAddr == 0U) || (Length == 0U)) { return HAL_ERROR; } @@ -1167,12 +1167,12 @@ HAL_StatusTypeDef HAL_HRTIM_SimpleBaseStart_DMA(HRTIM_HandleTypeDef * hhrtim, if (hdma == NULL) { - hhrtim->State = HAL_HRTIM_STATE_ERROR; + hhrtim->State = HAL_HRTIM_STATE_ERROR; - /* Process Unlocked */ - __HAL_UNLOCK(hhrtim); + /* Process Unlocked */ + __HAL_UNLOCK(hhrtim); - return HAL_ERROR; + return HAL_ERROR; } /* Set the DMA transfer completed callback */ @@ -1190,14 +1190,14 @@ HAL_StatusTypeDef HAL_HRTIM_SimpleBaseStart_DMA(HRTIM_HandleTypeDef * hhrtim, /* Enable the DMA channel */ if (HAL_DMA_Start_IT(hdma, SrcAddr, DestAddr, Length) != HAL_OK) - { - hhrtim->State = HAL_HRTIM_STATE_ERROR; + { + hhrtim->State = HAL_HRTIM_STATE_ERROR; - /* Process Unlocked */ - __HAL_UNLOCK(hhrtim); + /* Process Unlocked */ + __HAL_UNLOCK(hhrtim); - return HAL_ERROR; - } + return HAL_ERROR; + } /* Enable the timer repetition DMA request */ if (TimerIdx == HRTIM_TIMERINDEX_MASTER) @@ -1234,10 +1234,10 @@ HAL_StatusTypeDef HAL_HRTIM_SimpleBaseStart_DMA(HRTIM_HandleTypeDef * hhrtim, * @arg HRTIM_TIMERINDEX_TIMER_E for timer E * @retval HAL status */ -HAL_StatusTypeDef HAL_HRTIM_SimpleBaseStop_DMA(HRTIM_HandleTypeDef * hhrtim, - uint32_t TimerIdx) +HAL_StatusTypeDef HAL_HRTIM_SimpleBaseStop_DMA(HRTIM_HandleTypeDef *hhrtim, + uint32_t TimerIdx) { - DMA_HandleTypeDef * hdma; + DMA_HandleTypeDef *hdma; /* Check the parameters */ assert_param(IS_HRTIM_TIMERINDEX(TimerIdx)); @@ -1252,7 +1252,7 @@ HAL_StatusTypeDef HAL_HRTIM_SimpleBaseStop_DMA(HRTIM_HandleTypeDef * hhrtim, /* Disable the DMA */ if (HAL_DMA_Abort(hhrtim->hdmaMaster) != HAL_OK) { - hhrtim->State = HAL_HRTIM_STATE_ERROR; + hhrtim->State = HAL_HRTIM_STATE_ERROR; } /* Disable the timer repetition DMA request */ __HAL_HRTIM_MASTER_DISABLE_DMA(hhrtim, HRTIM_MASTER_DMA_MREP); @@ -1273,12 +1273,12 @@ HAL_StatusTypeDef HAL_HRTIM_SimpleBaseStop_DMA(HRTIM_HandleTypeDef * hhrtim, /* Disable the DMA */ if (HAL_DMA_Abort(hdma) != HAL_OK) { - hhrtim->State = HAL_HRTIM_STATE_ERROR; + hhrtim->State = HAL_HRTIM_STATE_ERROR; } /* Disable the timer repetition DMA request */ __HAL_HRTIM_TIMER_DISABLE_DMA(hhrtim, TimerIdx, HRTIM_TIM_DMA_REP); - } + } } /* Disable the timer counter */ @@ -1289,11 +1289,11 @@ HAL_StatusTypeDef HAL_HRTIM_SimpleBaseStop_DMA(HRTIM_HandleTypeDef * hhrtim, if (hhrtim->State == HAL_HRTIM_STATE_ERROR) { - return HAL_ERROR; + return HAL_ERROR; } else { - return HAL_OK; + return HAL_OK; } } @@ -1302,7 +1302,7 @@ HAL_StatusTypeDef HAL_HRTIM_SimpleBaseStop_DMA(HRTIM_HandleTypeDef * hhrtim, */ /** @defgroup HRTIM_Exported_Functions_Group3 Simple output compare mode functions - * @brief Simple output compare functions + * @brief Simple output compare functions @verbatim =============================================================================== ##### Simple output compare functions ##### @@ -1356,10 +1356,10 @@ HAL_StatusTypeDef HAL_HRTIM_SimpleBaseStop_DMA(HRTIM_HandleTypeDef * hhrtim, * Inactive: SETxy =0, RSTxy = CMPy * @retval HAL status */ -HAL_StatusTypeDef HAL_HRTIM_SimpleOCChannelConfig(HRTIM_HandleTypeDef * hhrtim, - uint32_t TimerIdx, - uint32_t OCChannel, - const HRTIM_SimpleOCChannelCfgTypeDef* pSimpleOCChannelCfg) +HAL_StatusTypeDef HAL_HRTIM_SimpleOCChannelConfig(HRTIM_HandleTypeDef *hhrtim, + uint32_t TimerIdx, + uint32_t OCChannel, + const HRTIM_SimpleOCChannelCfgTypeDef *pSimpleOCChannelCfg) { uint32_t CompareUnit = (uint32_t)RESET; HRTIM_OutputCfgTypeDef OutputCfg; @@ -1371,9 +1371,9 @@ HAL_StatusTypeDef HAL_HRTIM_SimpleOCChannelConfig(HRTIM_HandleTypeDef * hhrtim, assert_param(IS_HRTIM_OUTPUTPOLARITY(pSimpleOCChannelCfg->Polarity)); assert_param(IS_HRTIM_OUTPUTIDLELEVEL(pSimpleOCChannelCfg->IdleLevel)); - if(hhrtim->State == HAL_HRTIM_STATE_BUSY) + if (hhrtim->State == HAL_HRTIM_STATE_BUSY) { - return HAL_BUSY; + return HAL_BUSY; } /* Process Locked */ @@ -1385,27 +1385,27 @@ HAL_StatusTypeDef HAL_HRTIM_SimpleOCChannelConfig(HRTIM_HandleTypeDef * hhrtim, /* Configure timer compare unit */ switch (OCChannel) { - case HRTIM_OUTPUT_TA1: - case HRTIM_OUTPUT_TB1: - case HRTIM_OUTPUT_TC1: - case HRTIM_OUTPUT_TD1: - case HRTIM_OUTPUT_TE1: + case HRTIM_OUTPUT_TA1: + case HRTIM_OUTPUT_TB1: + case HRTIM_OUTPUT_TC1: + case HRTIM_OUTPUT_TD1: + case HRTIM_OUTPUT_TE1: { CompareUnit = HRTIM_COMPAREUNIT_1; hhrtim->Instance->sTimerxRegs[TimerIdx].CMP1xR = pSimpleOCChannelCfg->Pulse; break; } - case HRTIM_OUTPUT_TA2: - case HRTIM_OUTPUT_TB2: - case HRTIM_OUTPUT_TC2: - case HRTIM_OUTPUT_TD2: - case HRTIM_OUTPUT_TE2: + case HRTIM_OUTPUT_TA2: + case HRTIM_OUTPUT_TB2: + case HRTIM_OUTPUT_TC2: + case HRTIM_OUTPUT_TD2: + case HRTIM_OUTPUT_TE2: { CompareUnit = HRTIM_COMPAREUNIT_2; hhrtim->Instance->sTimerxRegs[TimerIdx].CMP2xR = pSimpleOCChannelCfg->Pulse; break; } - default: + default: { hhrtim->State = HAL_HRTIM_STATE_ERROR; @@ -1416,9 +1416,9 @@ HAL_StatusTypeDef HAL_HRTIM_SimpleOCChannelConfig(HRTIM_HandleTypeDef * hhrtim, } } - if(hhrtim->State == HAL_HRTIM_STATE_ERROR) + if (hhrtim->State == HAL_HRTIM_STATE_ERROR) { - return HAL_ERROR; + return HAL_ERROR; } /* Configure timer output */ @@ -1431,7 +1431,7 @@ HAL_StatusTypeDef HAL_HRTIM_SimpleOCChannelConfig(HRTIM_HandleTypeDef * hhrtim, switch (pSimpleOCChannelCfg->Mode) { - case HRTIM_BASICOCMODE_TOGGLE: + case HRTIM_BASICOCMODE_TOGGLE: { if (CompareUnit == HRTIM_COMPAREUNIT_1) { @@ -1445,7 +1445,7 @@ HAL_StatusTypeDef HAL_HRTIM_SimpleOCChannelConfig(HRTIM_HandleTypeDef * hhrtim, break; } - case HRTIM_BASICOCMODE_ACTIVE: + case HRTIM_BASICOCMODE_ACTIVE: { if (CompareUnit == HRTIM_COMPAREUNIT_1) { @@ -1459,7 +1459,7 @@ HAL_StatusTypeDef HAL_HRTIM_SimpleOCChannelConfig(HRTIM_HandleTypeDef * hhrtim, break; } - case HRTIM_BASICOCMODE_INACTIVE: + case HRTIM_BASICOCMODE_INACTIVE: { if (CompareUnit == HRTIM_COMPAREUNIT_1) { @@ -1473,7 +1473,7 @@ HAL_StatusTypeDef HAL_HRTIM_SimpleOCChannelConfig(HRTIM_HandleTypeDef * hhrtim, break; } - default: + default: { OutputCfg.SetSource = HRTIM_OUTPUTSET_NONE; OutputCfg.ResetSource = HRTIM_OUTPUTRESET_NONE; @@ -1487,9 +1487,9 @@ HAL_StatusTypeDef HAL_HRTIM_SimpleOCChannelConfig(HRTIM_HandleTypeDef * hhrtim, } } - if(hhrtim->State == HAL_HRTIM_STATE_ERROR) + if (hhrtim->State == HAL_HRTIM_STATE_ERROR) { - return HAL_ERROR; + return HAL_ERROR; } HRTIM_OutputConfig(hhrtim, @@ -1530,11 +1530,11 @@ HAL_StatusTypeDef HAL_HRTIM_SimpleOCChannelConfig(HRTIM_HandleTypeDef * hhrtim, * @arg HRTIM_OUTPUT_TE2: Timer E - Output 2 * @retval HAL status */ -HAL_StatusTypeDef HAL_HRTIM_SimpleOCStart(HRTIM_HandleTypeDef * hhrtim, - uint32_t TimerIdx, - uint32_t OCChannel) +HAL_StatusTypeDef HAL_HRTIM_SimpleOCStart(HRTIM_HandleTypeDef *hhrtim, + uint32_t TimerIdx, + uint32_t OCChannel) { - /* Check the parameters */ + /* Check the parameters */ assert_param(IS_HRTIM_TIMER_OUTPUT(TimerIdx, OCChannel)); /* Process Locked */ @@ -1580,11 +1580,11 @@ HAL_StatusTypeDef HAL_HRTIM_SimpleOCStart(HRTIM_HandleTypeDef * hhrtim, * @arg HRTIM_OUTPUT_TE2: Timer E - Output 2 * @retval HAL status */ -HAL_StatusTypeDef HAL_HRTIM_SimpleOCStop(HRTIM_HandleTypeDef * hhrtim, - uint32_t TimerIdx, - uint32_t OCChannel) +HAL_StatusTypeDef HAL_HRTIM_SimpleOCStop(HRTIM_HandleTypeDef *hhrtim, + uint32_t TimerIdx, + uint32_t OCChannel) { - /* Check the parameters */ + /* Check the parameters */ assert_param(IS_HRTIM_TIMER_OUTPUT(TimerIdx, OCChannel)); /* Process Locked */ @@ -1635,13 +1635,13 @@ HAL_StatusTypeDef HAL_HRTIM_SimpleOCStop(HRTIM_HandleTypeDef * hhrtim, * Output set inactive: output reset interrupt is enabled * @retval HAL status */ -HAL_StatusTypeDef HAL_HRTIM_SimpleOCStart_IT(HRTIM_HandleTypeDef * hhrtim, - uint32_t TimerIdx, - uint32_t OCChannel) +HAL_StatusTypeDef HAL_HRTIM_SimpleOCStart_IT(HRTIM_HandleTypeDef *hhrtim, + uint32_t TimerIdx, + uint32_t OCChannel) { uint32_t interrupt; - /* Check the parameters */ + /* Check the parameters */ assert_param(IS_HRTIM_TIMER_OUTPUT(TimerIdx, OCChannel)); /* Process Locked */ @@ -1694,13 +1694,13 @@ HAL_StatusTypeDef HAL_HRTIM_SimpleOCStart_IT(HRTIM_HandleTypeDef * hhrtim, * @arg HRTIM_OUTPUT_TE2: Timer E - Output 2 * @retval HAL status */ -HAL_StatusTypeDef HAL_HRTIM_SimpleOCStop_IT(HRTIM_HandleTypeDef * hhrtim, - uint32_t TimerIdx, - uint32_t OCChannel) +HAL_StatusTypeDef HAL_HRTIM_SimpleOCStop_IT(HRTIM_HandleTypeDef *hhrtim, + uint32_t TimerIdx, + uint32_t OCChannel) { uint32_t interrupt; - /* Check the parameters */ + /* Check the parameters */ assert_param(IS_HRTIM_TIMER_OUTPUT(TimerIdx, OCChannel)); /* Process Locked */ @@ -1761,26 +1761,26 @@ HAL_StatusTypeDef HAL_HRTIM_SimpleOCStop_IT(HRTIM_HandleTypeDef * hhrtim, * Output set inactive: output reset DMA request is enabled * @retval HAL status */ -HAL_StatusTypeDef HAL_HRTIM_SimpleOCStart_DMA(HRTIM_HandleTypeDef * hhrtim, - uint32_t TimerIdx, - uint32_t OCChannel, - uint32_t SrcAddr, - uint32_t DestAddr, - uint32_t Length) +HAL_StatusTypeDef HAL_HRTIM_SimpleOCStart_DMA(HRTIM_HandleTypeDef *hhrtim, + uint32_t TimerIdx, + uint32_t OCChannel, + uint32_t SrcAddr, + uint32_t DestAddr, + uint32_t Length) { - DMA_HandleTypeDef * hdma; + DMA_HandleTypeDef *hdma; uint32_t dma_request; /* Check the parameters */ assert_param(IS_HRTIM_TIMER_OUTPUT(TimerIdx, OCChannel)); - if(hhrtim->State == HAL_HRTIM_STATE_BUSY) + if (hhrtim->State == HAL_HRTIM_STATE_BUSY) { - return HAL_BUSY; + return HAL_BUSY; } - if(hhrtim->State == HAL_HRTIM_STATE_READY) + if (hhrtim->State == HAL_HRTIM_STATE_READY) { - if((SrcAddr == 0U ) || (DestAddr == 0U ) || (Length == 0U)) + if ((SrcAddr == 0U) || (DestAddr == 0U) || (Length == 0U)) { return HAL_ERROR; } @@ -1793,7 +1793,7 @@ HAL_StatusTypeDef HAL_HRTIM_SimpleOCStart_DMA(HRTIM_HandleTypeDef * hhrtim, /* Process Locked */ __HAL_LOCK(hhrtim); - /* Enable the timer output */ + /* Enable the timer output */ hhrtim->Instance->sCommonRegs.OENR |= OCChannel; /* Get the DMA request to enable */ @@ -1804,12 +1804,12 @@ HAL_StatusTypeDef HAL_HRTIM_SimpleOCStart_DMA(HRTIM_HandleTypeDef * hhrtim, if (hdma == NULL) { - hhrtim->State = HAL_HRTIM_STATE_ERROR; + hhrtim->State = HAL_HRTIM_STATE_ERROR; - /* Process Unlocked */ - __HAL_UNLOCK(hhrtim); + /* Process Unlocked */ + __HAL_UNLOCK(hhrtim); - return HAL_ERROR; + return HAL_ERROR; } /* Set the DMA error callback */ @@ -1820,14 +1820,14 @@ HAL_StatusTypeDef HAL_HRTIM_SimpleOCStart_DMA(HRTIM_HandleTypeDef * hhrtim, /* Enable the DMA channel */ if (HAL_DMA_Start_IT(hdma, SrcAddr, DestAddr, Length) != HAL_OK) - { - hhrtim->State = HAL_HRTIM_STATE_ERROR; + { + hhrtim->State = HAL_HRTIM_STATE_ERROR; - /* Process Unlocked */ - __HAL_UNLOCK(hhrtim); + /* Process Unlocked */ + __HAL_UNLOCK(hhrtim); - return HAL_ERROR; - } + return HAL_ERROR; + } /* Enable the timer DMA request */ __HAL_HRTIM_TIMER_ENABLE_DMA(hhrtim, TimerIdx, dma_request); @@ -1868,9 +1868,9 @@ HAL_StatusTypeDef HAL_HRTIM_SimpleOCStart_DMA(HRTIM_HandleTypeDef * hhrtim, * @arg HRTIM_OUTPUT_TE2: Timer E - Output 2 * @retval HAL status */ -HAL_StatusTypeDef HAL_HRTIM_SimpleOCStop_DMA(HRTIM_HandleTypeDef * hhrtim, - uint32_t TimerIdx, - uint32_t OCChannel) +HAL_StatusTypeDef HAL_HRTIM_SimpleOCStop_DMA(HRTIM_HandleTypeDef *hhrtim, + uint32_t TimerIdx, + uint32_t OCChannel) { uint32_t dma_request; @@ -1919,7 +1919,7 @@ HAL_StatusTypeDef HAL_HRTIM_SimpleOCStop_DMA(HRTIM_HandleTypeDef * hhrtim, */ /** @defgroup HRTIM_Exported_Functions_Group4 Simple PWM output mode functions - * @brief Simple PWM output functions + * @brief Simple PWM output functions @verbatim =============================================================================== ##### Simple PWM output functions ##### @@ -1976,10 +1976,10 @@ HAL_StatusTypeDef HAL_HRTIM_SimpleOCStop_DMA(HRTIM_HandleTypeDef * hhrtim, * enabled (otherwise the behavior is not guaranteed). * @retval HAL status */ -HAL_StatusTypeDef HAL_HRTIM_SimplePWMChannelConfig(HRTIM_HandleTypeDef * hhrtim, - uint32_t TimerIdx, - uint32_t PWMChannel, - const HRTIM_SimplePWMChannelCfgTypeDef* pSimplePWMChannelCfg) +HAL_StatusTypeDef HAL_HRTIM_SimplePWMChannelConfig(HRTIM_HandleTypeDef *hhrtim, + uint32_t TimerIdx, + uint32_t PWMChannel, + const HRTIM_SimplePWMChannelCfgTypeDef *pSimplePWMChannelCfg) { HRTIM_OutputCfgTypeDef OutputCfg; uint32_t hrtim_timcr; @@ -1990,9 +1990,9 @@ HAL_StatusTypeDef HAL_HRTIM_SimplePWMChannelConfig(HRTIM_HandleTypeDef * hhrtim, assert_param(IS_HRTIM_OUTPUTPULSE(pSimplePWMChannelCfg->Pulse)); assert_param(IS_HRTIM_OUTPUTIDLELEVEL(pSimplePWMChannelCfg->IdleLevel)); - if(hhrtim->State == HAL_HRTIM_STATE_BUSY) + if (hhrtim->State == HAL_HRTIM_STATE_BUSY) { - return HAL_BUSY; + return HAL_BUSY; } /* Process Locked */ @@ -2003,28 +2003,28 @@ HAL_StatusTypeDef HAL_HRTIM_SimplePWMChannelConfig(HRTIM_HandleTypeDef * hhrtim, /* Configure timer compare unit */ switch (PWMChannel) { - case HRTIM_OUTPUT_TA1: - case HRTIM_OUTPUT_TB1: - case HRTIM_OUTPUT_TC1: - case HRTIM_OUTPUT_TD1: - case HRTIM_OUTPUT_TE1: + case HRTIM_OUTPUT_TA1: + case HRTIM_OUTPUT_TB1: + case HRTIM_OUTPUT_TC1: + case HRTIM_OUTPUT_TD1: + case HRTIM_OUTPUT_TE1: { hhrtim->Instance->sTimerxRegs[TimerIdx].CMP1xR = pSimplePWMChannelCfg->Pulse; OutputCfg.SetSource = HRTIM_OUTPUTSET_TIMCMP1; break; } - case HRTIM_OUTPUT_TA2: - case HRTIM_OUTPUT_TB2: - case HRTIM_OUTPUT_TC2: - case HRTIM_OUTPUT_TD2: - case HRTIM_OUTPUT_TE2: + case HRTIM_OUTPUT_TA2: + case HRTIM_OUTPUT_TB2: + case HRTIM_OUTPUT_TC2: + case HRTIM_OUTPUT_TD2: + case HRTIM_OUTPUT_TE2: { hhrtim->Instance->sTimerxRegs[TimerIdx].CMP2xR = pSimplePWMChannelCfg->Pulse; OutputCfg.SetSource = HRTIM_OUTPUTSET_TIMCMP2; break; } - default: + default: { OutputCfg.SetSource = HRTIM_OUTPUTSET_NONE; OutputCfg.ResetSource = HRTIM_OUTPUTRESET_NONE; @@ -2038,14 +2038,14 @@ HAL_StatusTypeDef HAL_HRTIM_SimplePWMChannelConfig(HRTIM_HandleTypeDef * hhrtim, } } - if(hhrtim->State == HAL_HRTIM_STATE_ERROR) + if (hhrtim->State == HAL_HRTIM_STATE_ERROR) { - return HAL_ERROR; + return HAL_ERROR; } /* Configure timer output */ OutputCfg.Polarity = (pSimplePWMChannelCfg->Polarity & HRTIM_OUTR_POL1); - OutputCfg.IdleLevel = (pSimplePWMChannelCfg->IdleLevel& HRTIM_OUTR_IDLES1); + OutputCfg.IdleLevel = (pSimplePWMChannelCfg->IdleLevel & HRTIM_OUTR_IDLES1); OutputCfg.FaultLevel = HRTIM_OUTPUTFAULTLEVEL_NONE; OutputCfg.IdleMode = HRTIM_OUTPUTIDLEMODE_NONE; OutputCfg.ChopperModeEnable = HRTIM_OUTPUTCHOPPERMODE_DISABLED; @@ -2094,11 +2094,11 @@ HAL_StatusTypeDef HAL_HRTIM_SimplePWMChannelConfig(HRTIM_HandleTypeDef * hhrtim, * @arg HRTIM_OUTPUT_TE2: Timer E - Output 2 * @retval HAL status */ -HAL_StatusTypeDef HAL_HRTIM_SimplePWMStart(HRTIM_HandleTypeDef * hhrtim, - uint32_t TimerIdx, - uint32_t PWMChannel) +HAL_StatusTypeDef HAL_HRTIM_SimplePWMStart(HRTIM_HandleTypeDef *hhrtim, + uint32_t TimerIdx, + uint32_t PWMChannel) { - /* Check the parameters */ + /* Check the parameters */ assert_param(IS_HRTIM_TIMER_OUTPUT(TimerIdx, PWMChannel)); /* Process Locked */ @@ -2144,11 +2144,11 @@ HAL_StatusTypeDef HAL_HRTIM_SimplePWMStart(HRTIM_HandleTypeDef * hhrtim, * @arg HRTIM_OUTPUT_TE2: Timer E - Output 2 * @retval HAL status */ -HAL_StatusTypeDef HAL_HRTIM_SimplePWMStop(HRTIM_HandleTypeDef * hhrtim, - uint32_t TimerIdx, - uint32_t PWMChannel) +HAL_StatusTypeDef HAL_HRTIM_SimplePWMStop(HRTIM_HandleTypeDef *hhrtim, + uint32_t TimerIdx, + uint32_t PWMChannel) { - /* Check the parameters */ + /* Check the parameters */ assert_param(IS_HRTIM_TIMER_OUTPUT(TimerIdx, PWMChannel)); /* Process Locked */ @@ -2195,11 +2195,11 @@ HAL_StatusTypeDef HAL_HRTIM_SimplePWMStop(HRTIM_HandleTypeDef * hhrtim, * @arg HRTIM_OUTPUT_TE2: Timer E - Output 2 * @retval HAL status */ -HAL_StatusTypeDef HAL_HRTIM_SimplePWMStart_IT(HRTIM_HandleTypeDef * hhrtim, - uint32_t TimerIdx, - uint32_t PWMChannel) +HAL_StatusTypeDef HAL_HRTIM_SimplePWMStart_IT(HRTIM_HandleTypeDef *hhrtim, + uint32_t TimerIdx, + uint32_t PWMChannel) { - /* Check the parameters */ + /* Check the parameters */ assert_param(IS_HRTIM_TIMER_OUTPUT(TimerIdx, PWMChannel)); /* Process Locked */ @@ -2213,27 +2213,27 @@ HAL_StatusTypeDef HAL_HRTIM_SimplePWMStart_IT(HRTIM_HandleTypeDef * hhrtim, /* Enable the timer interrupt (depends on the PWM output) */ switch (PWMChannel) { - case HRTIM_OUTPUT_TA1: - case HRTIM_OUTPUT_TB1: - case HRTIM_OUTPUT_TC1: - case HRTIM_OUTPUT_TD1: - case HRTIM_OUTPUT_TE1: + case HRTIM_OUTPUT_TA1: + case HRTIM_OUTPUT_TB1: + case HRTIM_OUTPUT_TC1: + case HRTIM_OUTPUT_TD1: + case HRTIM_OUTPUT_TE1: { __HAL_HRTIM_TIMER_ENABLE_IT(hhrtim, TimerIdx, HRTIM_TIM_IT_CMP1); break; } - case HRTIM_OUTPUT_TA2: - case HRTIM_OUTPUT_TB2: - case HRTIM_OUTPUT_TC2: - case HRTIM_OUTPUT_TD2: - case HRTIM_OUTPUT_TE2: + case HRTIM_OUTPUT_TA2: + case HRTIM_OUTPUT_TB2: + case HRTIM_OUTPUT_TC2: + case HRTIM_OUTPUT_TD2: + case HRTIM_OUTPUT_TE2: { __HAL_HRTIM_TIMER_ENABLE_IT(hhrtim, TimerIdx, HRTIM_TIM_IT_CMP2); break; } - default: + default: { hhrtim->State = HAL_HRTIM_STATE_ERROR; @@ -2244,9 +2244,9 @@ HAL_StatusTypeDef HAL_HRTIM_SimplePWMStart_IT(HRTIM_HandleTypeDef * hhrtim, } } - if(hhrtim->State == HAL_HRTIM_STATE_ERROR) + if (hhrtim->State == HAL_HRTIM_STATE_ERROR) { - return HAL_ERROR; + return HAL_ERROR; } /* Enable the timer counter */ @@ -2285,11 +2285,11 @@ HAL_StatusTypeDef HAL_HRTIM_SimplePWMStart_IT(HRTIM_HandleTypeDef * hhrtim, * @arg HRTIM_OUTPUT_TE2: Timer E - Output 2 * @retval HAL status */ -HAL_StatusTypeDef HAL_HRTIM_SimplePWMStop_IT(HRTIM_HandleTypeDef * hhrtim, - uint32_t TimerIdx, - uint32_t PWMChannel) +HAL_StatusTypeDef HAL_HRTIM_SimplePWMStop_IT(HRTIM_HandleTypeDef *hhrtim, + uint32_t TimerIdx, + uint32_t PWMChannel) { - /* Check the parameters */ + /* Check the parameters */ assert_param(IS_HRTIM_TIMER_OUTPUT(TimerIdx, PWMChannel)); /* Process Locked */ @@ -2303,27 +2303,27 @@ HAL_StatusTypeDef HAL_HRTIM_SimplePWMStop_IT(HRTIM_HandleTypeDef * hhrtim, /* Disable the timer interrupt (depends on the PWM output) */ switch (PWMChannel) { - case HRTIM_OUTPUT_TA1: - case HRTIM_OUTPUT_TB1: - case HRTIM_OUTPUT_TC1: - case HRTIM_OUTPUT_TD1: - case HRTIM_OUTPUT_TE1: + case HRTIM_OUTPUT_TA1: + case HRTIM_OUTPUT_TB1: + case HRTIM_OUTPUT_TC1: + case HRTIM_OUTPUT_TD1: + case HRTIM_OUTPUT_TE1: { __HAL_HRTIM_TIMER_DISABLE_IT(hhrtim, TimerIdx, HRTIM_TIM_IT_CMP1); break; } - case HRTIM_OUTPUT_TA2: - case HRTIM_OUTPUT_TB2: - case HRTIM_OUTPUT_TC2: - case HRTIM_OUTPUT_TD2: - case HRTIM_OUTPUT_TE2: + case HRTIM_OUTPUT_TA2: + case HRTIM_OUTPUT_TB2: + case HRTIM_OUTPUT_TC2: + case HRTIM_OUTPUT_TD2: + case HRTIM_OUTPUT_TE2: { __HAL_HRTIM_TIMER_DISABLE_IT(hhrtim, TimerIdx, HRTIM_TIM_IT_CMP2); break; } - default: + default: { hhrtim->State = HAL_HRTIM_STATE_ERROR; @@ -2334,9 +2334,9 @@ HAL_StatusTypeDef HAL_HRTIM_SimplePWMStop_IT(HRTIM_HandleTypeDef * hhrtim, } } - if(hhrtim->State == HAL_HRTIM_STATE_ERROR) + if (hhrtim->State == HAL_HRTIM_STATE_ERROR) { - return HAL_ERROR; + return HAL_ERROR; } /* Disable the timer counter */ @@ -2379,25 +2379,25 @@ HAL_StatusTypeDef HAL_HRTIM_SimplePWMStop_IT(HRTIM_HandleTypeDef * hhrtim, * from source to destination * @retval HAL status */ -HAL_StatusTypeDef HAL_HRTIM_SimplePWMStart_DMA(HRTIM_HandleTypeDef * hhrtim, - uint32_t TimerIdx, - uint32_t PWMChannel, - uint32_t SrcAddr, - uint32_t DestAddr, - uint32_t Length) +HAL_StatusTypeDef HAL_HRTIM_SimplePWMStart_DMA(HRTIM_HandleTypeDef *hhrtim, + uint32_t TimerIdx, + uint32_t PWMChannel, + uint32_t SrcAddr, + uint32_t DestAddr, + uint32_t Length) { - DMA_HandleTypeDef * hdma; + DMA_HandleTypeDef *hdma; /* Check the parameters */ assert_param(IS_HRTIM_TIMER_OUTPUT(TimerIdx, PWMChannel)); - if(hhrtim->State == HAL_HRTIM_STATE_BUSY) + if (hhrtim->State == HAL_HRTIM_STATE_BUSY) { - return HAL_BUSY; + return HAL_BUSY; } - if(hhrtim->State == HAL_HRTIM_STATE_READY) + if (hhrtim->State == HAL_HRTIM_STATE_READY) { - if((SrcAddr == 0U ) || (DestAddr == 0U ) || (Length == 0U)) + if ((SrcAddr == 0U) || (DestAddr == 0U) || (Length == 0U)) { return HAL_ERROR; } @@ -2434,39 +2434,39 @@ HAL_StatusTypeDef HAL_HRTIM_SimplePWMStart_DMA(HRTIM_HandleTypeDef * hhrtim, /* Enable the DMA channel */ if (HAL_DMA_Start_IT(hdma, SrcAddr, DestAddr, Length) != HAL_OK) - { - hhrtim->State = HAL_HRTIM_STATE_ERROR; + { + hhrtim->State = HAL_HRTIM_STATE_ERROR; - /* Process Unlocked */ - __HAL_UNLOCK(hhrtim); + /* Process Unlocked */ + __HAL_UNLOCK(hhrtim); - return HAL_ERROR; - } + return HAL_ERROR; + } /* Enable the timer DMA request */ switch (PWMChannel) { - case HRTIM_OUTPUT_TA1: - case HRTIM_OUTPUT_TB1: - case HRTIM_OUTPUT_TC1: - case HRTIM_OUTPUT_TD1: - case HRTIM_OUTPUT_TE1: + case HRTIM_OUTPUT_TA1: + case HRTIM_OUTPUT_TB1: + case HRTIM_OUTPUT_TC1: + case HRTIM_OUTPUT_TD1: + case HRTIM_OUTPUT_TE1: { __HAL_HRTIM_TIMER_ENABLE_DMA(hhrtim, TimerIdx, HRTIM_TIM_DMA_CMP1); break; } - case HRTIM_OUTPUT_TA2: - case HRTIM_OUTPUT_TB2: - case HRTIM_OUTPUT_TC2: - case HRTIM_OUTPUT_TD2: - case HRTIM_OUTPUT_TE2: + case HRTIM_OUTPUT_TA2: + case HRTIM_OUTPUT_TB2: + case HRTIM_OUTPUT_TC2: + case HRTIM_OUTPUT_TD2: + case HRTIM_OUTPUT_TE2: { __HAL_HRTIM_TIMER_ENABLE_DMA(hhrtim, TimerIdx, HRTIM_TIM_DMA_CMP2); break; } - default: + default: { hhrtim->State = HAL_HRTIM_STATE_ERROR; @@ -2477,9 +2477,9 @@ HAL_StatusTypeDef HAL_HRTIM_SimplePWMStart_DMA(HRTIM_HandleTypeDef * hhrtim, } } - if(hhrtim->State == HAL_HRTIM_STATE_ERROR) + if (hhrtim->State == HAL_HRTIM_STATE_ERROR) { - return HAL_ERROR; + return HAL_ERROR; } /* Enable the timer counter */ @@ -2518,9 +2518,9 @@ HAL_StatusTypeDef HAL_HRTIM_SimplePWMStart_DMA(HRTIM_HandleTypeDef * hhrtim, * @arg HRTIM_OUTPUT_TE2: Timer E - Output 2 * @retval HAL status */ -HAL_StatusTypeDef HAL_HRTIM_SimplePWMStop_DMA(HRTIM_HandleTypeDef * hhrtim, - uint32_t TimerIdx, - uint32_t PWMChannel) +HAL_StatusTypeDef HAL_HRTIM_SimplePWMStop_DMA(HRTIM_HandleTypeDef *hhrtim, + uint32_t TimerIdx, + uint32_t PWMChannel) { /* Check the parameters */ assert_param(IS_HRTIM_TIMER_OUTPUT(TimerIdx, PWMChannel)); @@ -2548,27 +2548,27 @@ HAL_StatusTypeDef HAL_HRTIM_SimplePWMStop_DMA(HRTIM_HandleTypeDef * hhrtim, /* Disable the timer DMA request */ switch (PWMChannel) { - case HRTIM_OUTPUT_TA1: - case HRTIM_OUTPUT_TB1: - case HRTIM_OUTPUT_TC1: - case HRTIM_OUTPUT_TD1: - case HRTIM_OUTPUT_TE1: + case HRTIM_OUTPUT_TA1: + case HRTIM_OUTPUT_TB1: + case HRTIM_OUTPUT_TC1: + case HRTIM_OUTPUT_TD1: + case HRTIM_OUTPUT_TE1: { __HAL_HRTIM_TIMER_DISABLE_DMA(hhrtim, TimerIdx, HRTIM_TIM_DMA_CMP1); break; } - case HRTIM_OUTPUT_TA2: - case HRTIM_OUTPUT_TB2: - case HRTIM_OUTPUT_TC2: - case HRTIM_OUTPUT_TD2: - case HRTIM_OUTPUT_TE2: + case HRTIM_OUTPUT_TA2: + case HRTIM_OUTPUT_TB2: + case HRTIM_OUTPUT_TC2: + case HRTIM_OUTPUT_TD2: + case HRTIM_OUTPUT_TE2: { __HAL_HRTIM_TIMER_DISABLE_DMA(hhrtim, TimerIdx, HRTIM_TIM_DMA_CMP2); break; } - default: + default: { hhrtim->State = HAL_HRTIM_STATE_ERROR; @@ -2579,9 +2579,9 @@ HAL_StatusTypeDef HAL_HRTIM_SimplePWMStop_DMA(HRTIM_HandleTypeDef * hhrtim, } } - if(hhrtim->State == HAL_HRTIM_STATE_ERROR) + if (hhrtim->State == HAL_HRTIM_STATE_ERROR) { - return HAL_ERROR; + return HAL_ERROR; } /* Disable the timer counter */ @@ -2600,7 +2600,7 @@ HAL_StatusTypeDef HAL_HRTIM_SimplePWMStop_DMA(HRTIM_HandleTypeDef * hhrtim, */ /** @defgroup HRTIM_Exported_Functions_Group5 Simple input capture functions - * @brief Simple input capture functions + * @brief Simple input capture functions @verbatim =============================================================================== ##### Simple input capture functions ##### @@ -2642,10 +2642,10 @@ HAL_StatusTypeDef HAL_HRTIM_SimplePWMStop_DMA(HRTIM_HandleTypeDef * hhrtim, * edges on event channel. * @retval HAL status */ -HAL_StatusTypeDef HAL_HRTIM_SimpleCaptureChannelConfig(HRTIM_HandleTypeDef * hhrtim, - uint32_t TimerIdx, - uint32_t CaptureChannel, - const HRTIM_SimpleCaptureChannelCfgTypeDef* pSimpleCaptureChannelCfg) +HAL_StatusTypeDef HAL_HRTIM_SimpleCaptureChannelConfig(HRTIM_HandleTypeDef *hhrtim, + uint32_t TimerIdx, + uint32_t CaptureChannel, + const HRTIM_SimpleCaptureChannelCfgTypeDef *pSimpleCaptureChannelCfg) { HRTIM_EventCfgTypeDef EventCfg; @@ -2659,9 +2659,9 @@ HAL_StatusTypeDef HAL_HRTIM_SimpleCaptureChannelConfig(HRTIM_HandleTypeDef * hhr assert_param(IS_HRTIM_EVENTFILTER(pSimpleCaptureChannelCfg->Event, pSimpleCaptureChannelCfg->EventFilter)); - if(hhrtim->State == HAL_HRTIM_STATE_BUSY) + if (hhrtim->State == HAL_HRTIM_STATE_BUSY) { - return HAL_BUSY; + return HAL_BUSY; } /* Process Locked */ @@ -2713,11 +2713,11 @@ HAL_StatusTypeDef HAL_HRTIM_SimpleCaptureChannelConfig(HRTIM_HandleTypeDef * hhr * units. It can be used directly and is active as soon as the timing * unit counter is enabled. */ -HAL_StatusTypeDef HAL_HRTIM_SimpleCaptureStart(HRTIM_HandleTypeDef * hhrtim, - uint32_t TimerIdx, - uint32_t CaptureChannel) +HAL_StatusTypeDef HAL_HRTIM_SimpleCaptureStart(HRTIM_HandleTypeDef *hhrtim, + uint32_t TimerIdx, + uint32_t CaptureChannel) { - /* Check the parameters */ + /* Check the parameters */ assert_param(IS_HRTIM_TIMING_UNIT(TimerIdx)); assert_param(IS_HRTIM_CAPTUREUNIT(CaptureChannel)); @@ -2729,19 +2729,19 @@ HAL_StatusTypeDef HAL_HRTIM_SimpleCaptureStart(HRTIM_HandleTypeDef * hhrtim, /* Set the capture unit trigger */ switch (CaptureChannel) { - case HRTIM_CAPTUREUNIT_1: + case HRTIM_CAPTUREUNIT_1: { hhrtim->Instance->sTimerxRegs[TimerIdx].CPT1xCR = hhrtim->TimerParam[TimerIdx].CaptureTrigger1; break; } - case HRTIM_CAPTUREUNIT_2: + case HRTIM_CAPTUREUNIT_2: { hhrtim->Instance->sTimerxRegs[TimerIdx].CPT2xCR = hhrtim->TimerParam[TimerIdx].CaptureTrigger2; break; } - default: + default: { hhrtim->State = HAL_HRTIM_STATE_ERROR; @@ -2752,9 +2752,9 @@ HAL_StatusTypeDef HAL_HRTIM_SimpleCaptureStart(HRTIM_HandleTypeDef * hhrtim, } } - if(hhrtim->State == HAL_HRTIM_STATE_ERROR) + if (hhrtim->State == HAL_HRTIM_STATE_ERROR) { - return HAL_ERROR; + return HAL_ERROR; } /* Enable the timer counter */ @@ -2784,14 +2784,14 @@ HAL_StatusTypeDef HAL_HRTIM_SimpleCaptureStart(HRTIM_HandleTypeDef * hhrtim, * @arg HRTIM_CAPTUREUNIT_2: Capture unit 2 * @retval HAL status */ -HAL_StatusTypeDef HAL_HRTIM_SimpleCaptureStop(HRTIM_HandleTypeDef * hhrtim, - uint32_t TimerIdx, - uint32_t CaptureChannel) +HAL_StatusTypeDef HAL_HRTIM_SimpleCaptureStop(HRTIM_HandleTypeDef *hhrtim, + uint32_t TimerIdx, + uint32_t CaptureChannel) { uint32_t hrtim_cpt1cr; uint32_t hrtim_cpt2cr; - /* Check the parameters */ + /* Check the parameters */ assert_param(IS_HRTIM_TIMING_UNIT(TimerIdx)); assert_param(IS_HRTIM_CAPTUREUNIT(CaptureChannel)); @@ -2803,19 +2803,19 @@ HAL_StatusTypeDef HAL_HRTIM_SimpleCaptureStop(HRTIM_HandleTypeDef * hhrtim, /* Set the capture unit trigger */ switch (CaptureChannel) { - case HRTIM_CAPTUREUNIT_1: + case HRTIM_CAPTUREUNIT_1: { hhrtim->Instance->sTimerxRegs[TimerIdx].CPT1xCR = HRTIM_CAPTURETRIGGER_NONE; break; } - case HRTIM_CAPTUREUNIT_2: + case HRTIM_CAPTUREUNIT_2: { hhrtim->Instance->sTimerxRegs[TimerIdx].CPT2xCR = HRTIM_CAPTURETRIGGER_NONE; break; } - default: + default: { hhrtim->State = HAL_HRTIM_STATE_ERROR; @@ -2826,9 +2826,9 @@ HAL_StatusTypeDef HAL_HRTIM_SimpleCaptureStop(HRTIM_HandleTypeDef * hhrtim, } } - if(hhrtim->State == HAL_HRTIM_STATE_ERROR) + if (hhrtim->State == HAL_HRTIM_STATE_ERROR) { - return HAL_ERROR; + return HAL_ERROR; } hrtim_cpt1cr = hhrtim->Instance->sTimerxRegs[TimerIdx].CPT1xCR; @@ -2866,11 +2866,11 @@ HAL_StatusTypeDef HAL_HRTIM_SimpleCaptureStop(HRTIM_HandleTypeDef * hhrtim, * @arg HRTIM_CAPTUREUNIT_2: Capture unit 2 * @retval HAL status */ -HAL_StatusTypeDef HAL_HRTIM_SimpleCaptureStart_IT(HRTIM_HandleTypeDef * hhrtim, - uint32_t TimerIdx, - uint32_t CaptureChannel) +HAL_StatusTypeDef HAL_HRTIM_SimpleCaptureStart_IT(HRTIM_HandleTypeDef *hhrtim, + uint32_t TimerIdx, + uint32_t CaptureChannel) { - /* Check the parameters */ + /* Check the parameters */ assert_param(IS_HRTIM_TIMING_UNIT(TimerIdx)); assert_param(IS_HRTIM_CAPTUREUNIT(CaptureChannel)); @@ -2882,7 +2882,7 @@ HAL_StatusTypeDef HAL_HRTIM_SimpleCaptureStart_IT(HRTIM_HandleTypeDef * hhrtim, /* Set the capture unit trigger */ switch (CaptureChannel) { - case HRTIM_CAPTUREUNIT_1: + case HRTIM_CAPTUREUNIT_1: { hhrtim->Instance->sTimerxRegs[TimerIdx].CPT1xCR = hhrtim->TimerParam[TimerIdx].CaptureTrigger1; @@ -2891,7 +2891,7 @@ HAL_StatusTypeDef HAL_HRTIM_SimpleCaptureStart_IT(HRTIM_HandleTypeDef * hhrtim, break; } - case HRTIM_CAPTUREUNIT_2: + case HRTIM_CAPTUREUNIT_2: { hhrtim->Instance->sTimerxRegs[TimerIdx].CPT2xCR = hhrtim->TimerParam[TimerIdx].CaptureTrigger2; @@ -2900,7 +2900,7 @@ HAL_StatusTypeDef HAL_HRTIM_SimpleCaptureStart_IT(HRTIM_HandleTypeDef * hhrtim, break; } - default: + default: { hhrtim->State = HAL_HRTIM_STATE_ERROR; @@ -2911,9 +2911,9 @@ HAL_StatusTypeDef HAL_HRTIM_SimpleCaptureStart_IT(HRTIM_HandleTypeDef * hhrtim, } } - if(hhrtim->State == HAL_HRTIM_STATE_ERROR) + if (hhrtim->State == HAL_HRTIM_STATE_ERROR) { - return HAL_ERROR; + return HAL_ERROR; } /* Enable the timer counter */ @@ -2944,15 +2944,15 @@ HAL_StatusTypeDef HAL_HRTIM_SimpleCaptureStart_IT(HRTIM_HandleTypeDef * hhrtim, * @arg HRTIM_CAPTUREUNIT_2: Capture unit 2 * @retval HAL status */ -HAL_StatusTypeDef HAL_HRTIM_SimpleCaptureStop_IT(HRTIM_HandleTypeDef * hhrtim, - uint32_t TimerIdx, - uint32_t CaptureChannel) +HAL_StatusTypeDef HAL_HRTIM_SimpleCaptureStop_IT(HRTIM_HandleTypeDef *hhrtim, + uint32_t TimerIdx, + uint32_t CaptureChannel) { uint32_t hrtim_cpt1cr; uint32_t hrtim_cpt2cr; - /* Check the parameters */ + /* Check the parameters */ assert_param(IS_HRTIM_TIMING_UNIT(TimerIdx)); assert_param(IS_HRTIM_CAPTUREUNIT(CaptureChannel)); @@ -2964,7 +2964,7 @@ HAL_StatusTypeDef HAL_HRTIM_SimpleCaptureStop_IT(HRTIM_HandleTypeDef * hhrtim, /* Set the capture unit trigger */ switch (CaptureChannel) { - case HRTIM_CAPTUREUNIT_1: + case HRTIM_CAPTUREUNIT_1: { hhrtim->Instance->sTimerxRegs[TimerIdx].CPT1xCR = HRTIM_CAPTURETRIGGER_NONE; @@ -2973,7 +2973,7 @@ HAL_StatusTypeDef HAL_HRTIM_SimpleCaptureStop_IT(HRTIM_HandleTypeDef * hhrtim, break; } - case HRTIM_CAPTUREUNIT_2: + case HRTIM_CAPTUREUNIT_2: { hhrtim->Instance->sTimerxRegs[TimerIdx].CPT2xCR = HRTIM_CAPTURETRIGGER_NONE; @@ -2982,7 +2982,7 @@ HAL_StatusTypeDef HAL_HRTIM_SimpleCaptureStop_IT(HRTIM_HandleTypeDef * hhrtim, break; } - default: + default: { hhrtim->State = HAL_HRTIM_STATE_ERROR; @@ -2993,9 +2993,9 @@ HAL_StatusTypeDef HAL_HRTIM_SimpleCaptureStop_IT(HRTIM_HandleTypeDef * hhrtim, } } - if(hhrtim->State == HAL_HRTIM_STATE_ERROR) + if (hhrtim->State == HAL_HRTIM_STATE_ERROR) { - return HAL_ERROR; + return HAL_ERROR; } hrtim_cpt1cr = hhrtim->Instance->sTimerxRegs[TimerIdx].CPT1xCR; @@ -3037,16 +3037,16 @@ HAL_StatusTypeDef HAL_HRTIM_SimpleCaptureStop_IT(HRTIM_HandleTypeDef * hhrtim, * from source to destination * @retval HAL status */ -HAL_StatusTypeDef HAL_HRTIM_SimpleCaptureStart_DMA(HRTIM_HandleTypeDef * hhrtim, - uint32_t TimerIdx, - uint32_t CaptureChannel, - uint32_t SrcAddr, - uint32_t DestAddr, - uint32_t Length) +HAL_StatusTypeDef HAL_HRTIM_SimpleCaptureStart_DMA(HRTIM_HandleTypeDef *hhrtim, + uint32_t TimerIdx, + uint32_t CaptureChannel, + uint32_t SrcAddr, + uint32_t DestAddr, + uint32_t Length) { - DMA_HandleTypeDef * hdma; + DMA_HandleTypeDef *hdma; - /* Check the parameters */ + /* Check the parameters */ assert_param(IS_HRTIM_TIMING_UNIT(TimerIdx)); assert_param(IS_HRTIM_CAPTUREUNIT(CaptureChannel)); @@ -3060,12 +3060,12 @@ HAL_StatusTypeDef HAL_HRTIM_SimpleCaptureStart_DMA(HRTIM_HandleTypeDef * hhrtim, if (hdma == NULL) { - hhrtim->State = HAL_HRTIM_STATE_ERROR; + hhrtim->State = HAL_HRTIM_STATE_ERROR; - /* Process Unlocked */ - __HAL_UNLOCK(hhrtim); + /* Process Unlocked */ + __HAL_UNLOCK(hhrtim); - return HAL_ERROR; + return HAL_ERROR; } /* Set the DMA error callback */ @@ -3076,18 +3076,18 @@ HAL_StatusTypeDef HAL_HRTIM_SimpleCaptureStart_DMA(HRTIM_HandleTypeDef * hhrtim, /* Enable the DMA channel */ if (HAL_DMA_Start_IT(hdma, SrcAddr, DestAddr, Length) != HAL_OK) - { - hhrtim->State = HAL_HRTIM_STATE_ERROR; + { + hhrtim->State = HAL_HRTIM_STATE_ERROR; - /* Process Unlocked */ - __HAL_UNLOCK(hhrtim); + /* Process Unlocked */ + __HAL_UNLOCK(hhrtim); - return HAL_ERROR; - } + return HAL_ERROR; + } switch (CaptureChannel) { - case HRTIM_CAPTUREUNIT_1: + case HRTIM_CAPTUREUNIT_1: { /* Set the capture unit trigger */ hhrtim->Instance->sTimerxRegs[TimerIdx].CPT1xCR = hhrtim->TimerParam[TimerIdx].CaptureTrigger1; @@ -3096,7 +3096,7 @@ HAL_StatusTypeDef HAL_HRTIM_SimpleCaptureStart_DMA(HRTIM_HandleTypeDef * hhrtim, break; } - case HRTIM_CAPTUREUNIT_2: + case HRTIM_CAPTUREUNIT_2: { /* Set the capture unit trigger */ hhrtim->Instance->sTimerxRegs[TimerIdx].CPT2xCR = hhrtim->TimerParam[TimerIdx].CaptureTrigger2; @@ -3106,7 +3106,7 @@ HAL_StatusTypeDef HAL_HRTIM_SimpleCaptureStart_DMA(HRTIM_HandleTypeDef * hhrtim, break; } - default: + default: { hhrtim->State = HAL_HRTIM_STATE_ERROR; @@ -3115,11 +3115,11 @@ HAL_StatusTypeDef HAL_HRTIM_SimpleCaptureStart_DMA(HRTIM_HandleTypeDef * hhrtim, break; } - } + } - if(hhrtim->State == HAL_HRTIM_STATE_ERROR) + if (hhrtim->State == HAL_HRTIM_STATE_ERROR) { - return HAL_ERROR; + return HAL_ERROR; } /* Enable the timer counter */ @@ -3150,9 +3150,9 @@ HAL_StatusTypeDef HAL_HRTIM_SimpleCaptureStart_DMA(HRTIM_HandleTypeDef * hhrtim, * @arg HRTIM_CAPTUREUNIT_2: Capture unit 2 * @retval HAL status */ -HAL_StatusTypeDef HAL_HRTIM_SimpleCaptureStop_DMA(HRTIM_HandleTypeDef * hhrtim, - uint32_t TimerIdx, - uint32_t CaptureChannel) +HAL_StatusTypeDef HAL_HRTIM_SimpleCaptureStop_DMA(HRTIM_HandleTypeDef *hhrtim, + uint32_t TimerIdx, + uint32_t CaptureChannel) { uint32_t hrtim_cpt1cr; @@ -3171,17 +3171,17 @@ HAL_StatusTypeDef HAL_HRTIM_SimpleCaptureStop_DMA(HRTIM_HandleTypeDef * hhrtim, /* Disable the DMA */ if (HAL_DMA_Abort(HRTIM_GetDMAHandleFromTimerIdx(hhrtim, TimerIdx)) != HAL_OK) { - hhrtim->State = HAL_HRTIM_STATE_ERROR; + hhrtim->State = HAL_HRTIM_STATE_ERROR; - /* Process Unlocked */ - __HAL_UNLOCK(hhrtim); + /* Process Unlocked */ + __HAL_UNLOCK(hhrtim); - return HAL_ERROR; + return HAL_ERROR; } switch (CaptureChannel) { - case HRTIM_CAPTUREUNIT_1: + case HRTIM_CAPTUREUNIT_1: { /* Reset the capture unit trigger */ hhrtim->Instance->sTimerxRegs[TimerIdx].CPT1xCR = HRTIM_CAPTURETRIGGER_NONE; @@ -3191,7 +3191,7 @@ HAL_StatusTypeDef HAL_HRTIM_SimpleCaptureStop_DMA(HRTIM_HandleTypeDef * hhrtim, break; } - case HRTIM_CAPTUREUNIT_2: + case HRTIM_CAPTUREUNIT_2: { /* Reset the capture unit trigger */ hhrtim->Instance->sTimerxRegs[TimerIdx].CPT2xCR = HRTIM_CAPTURETRIGGER_NONE; @@ -3201,7 +3201,7 @@ HAL_StatusTypeDef HAL_HRTIM_SimpleCaptureStop_DMA(HRTIM_HandleTypeDef * hhrtim, break; } - default: + default: { hhrtim->State = HAL_HRTIM_STATE_ERROR; @@ -3212,9 +3212,9 @@ HAL_StatusTypeDef HAL_HRTIM_SimpleCaptureStop_DMA(HRTIM_HandleTypeDef * hhrtim, } } - if(hhrtim->State == HAL_HRTIM_STATE_ERROR) + if (hhrtim->State == HAL_HRTIM_STATE_ERROR) { - return HAL_ERROR; + return HAL_ERROR; } hrtim_cpt1cr = hhrtim->Instance->sTimerxRegs[TimerIdx].CPT1xCR; @@ -3240,7 +3240,7 @@ HAL_StatusTypeDef HAL_HRTIM_SimpleCaptureStop_DMA(HRTIM_HandleTypeDef * hhrtim, */ /** @defgroup HRTIM_Exported_Functions_Group6 Simple one pulse functions - * @brief Simple one pulse functions + * @brief Simple one pulse functions @verbatim =============================================================================== ##### Simple one pulse functions ##### @@ -3297,10 +3297,10 @@ HAL_StatusTypeDef HAL_HRTIM_SimpleCaptureStop_DMA(HRTIM_HandleTypeDef * hhrtim, * second call will override the reset event related configuration data * provided in the first call. */ -HAL_StatusTypeDef HAL_HRTIM_SimpleOnePulseChannelConfig(HRTIM_HandleTypeDef * hhrtim, - uint32_t TimerIdx, - uint32_t OnePulseChannel, - const HRTIM_SimpleOnePulseChannelCfgTypeDef* pSimpleOnePulseChannelCfg) +HAL_StatusTypeDef HAL_HRTIM_SimpleOnePulseChannelConfig(HRTIM_HandleTypeDef *hhrtim, + uint32_t TimerIdx, + uint32_t OnePulseChannel, + const HRTIM_SimpleOnePulseChannelCfgTypeDef *pSimpleOnePulseChannelCfg) { HRTIM_OutputCfgTypeDef OutputCfg; HRTIM_EventCfgTypeDef EventCfg; @@ -3317,9 +3317,9 @@ HAL_StatusTypeDef HAL_HRTIM_SimpleOnePulseChannelConfig(HRTIM_HandleTypeDef * hh assert_param(IS_HRTIM_EVENTFILTER(pSimpleOnePulseChannelCfg->Event, pSimpleOnePulseChannelCfg->EventFilter)); - if(hhrtim->State == HAL_HRTIM_STATE_BUSY) + if (hhrtim->State == HAL_HRTIM_STATE_BUSY) { - return HAL_BUSY; + return HAL_BUSY; } /* Process Locked */ @@ -3330,29 +3330,29 @@ HAL_StatusTypeDef HAL_HRTIM_SimpleOnePulseChannelConfig(HRTIM_HandleTypeDef * hh /* Configure timer compare unit */ switch (OnePulseChannel) { - case HRTIM_OUTPUT_TA1: - case HRTIM_OUTPUT_TB1: - case HRTIM_OUTPUT_TC1: - case HRTIM_OUTPUT_TD1: - case HRTIM_OUTPUT_TE1: + case HRTIM_OUTPUT_TA1: + case HRTIM_OUTPUT_TB1: + case HRTIM_OUTPUT_TC1: + case HRTIM_OUTPUT_TD1: + case HRTIM_OUTPUT_TE1: { hhrtim->Instance->sTimerxRegs[TimerIdx].CMP1xR = pSimpleOnePulseChannelCfg->Pulse; OutputCfg.SetSource = HRTIM_OUTPUTSET_TIMCMP1; break; } - case HRTIM_OUTPUT_TA2: - case HRTIM_OUTPUT_TB2: - case HRTIM_OUTPUT_TC2: - case HRTIM_OUTPUT_TD2: - case HRTIM_OUTPUT_TE2: + case HRTIM_OUTPUT_TA2: + case HRTIM_OUTPUT_TB2: + case HRTIM_OUTPUT_TC2: + case HRTIM_OUTPUT_TD2: + case HRTIM_OUTPUT_TE2: { hhrtim->Instance->sTimerxRegs[TimerIdx].CMP2xR = pSimpleOnePulseChannelCfg->Pulse; OutputCfg.SetSource = HRTIM_OUTPUTSET_TIMCMP2; break; } - default: + default: { OutputCfg.SetSource = HRTIM_OUTPUTSET_NONE; OutputCfg.ResetSource = HRTIM_OUTPUTRESET_NONE; @@ -3366,13 +3366,13 @@ HAL_StatusTypeDef HAL_HRTIM_SimpleOnePulseChannelConfig(HRTIM_HandleTypeDef * hh } } - if(hhrtim->State == HAL_HRTIM_STATE_ERROR) + if (hhrtim->State == HAL_HRTIM_STATE_ERROR) { - return HAL_ERROR; + return HAL_ERROR; } /* Configure timer output */ - OutputCfg.Polarity = (pSimpleOnePulseChannelCfg->OutputPolarity & HRTIM_OUTR_POL1); + OutputCfg.Polarity = (pSimpleOnePulseChannelCfg->OutputPolarity & HRTIM_OUTR_POL1); OutputCfg.IdleLevel = (pSimpleOnePulseChannelCfg->OutputIdleLevel & HRTIM_OUTR_IDLES1); OutputCfg.FaultLevel = HRTIM_OUTPUTFAULTLEVEL_NONE; OutputCfg.IdleMode = HRTIM_OUTPUTIDLEMODE_NONE; @@ -3389,7 +3389,7 @@ HAL_StatusTypeDef HAL_HRTIM_SimpleOnePulseChannelConfig(HRTIM_HandleTypeDef * hh EventCfg.FastMode = HRTIM_EVENTFASTMODE_DISABLE; EventCfg.Filter = (pSimpleOnePulseChannelCfg->EventFilter & HRTIM_EECR3_EE6F); EventCfg.Polarity = (pSimpleOnePulseChannelCfg->EventPolarity & HRTIM_OUTR_POL1); - EventCfg.Sensitivity = (pSimpleOnePulseChannelCfg->EventSensitivity &HRTIM_EECR1_EE1SNS); + EventCfg.Sensitivity = (pSimpleOnePulseChannelCfg->EventSensitivity & HRTIM_EECR1_EE1SNS); EventCfg.Source = HRTIM_EVENTSRC_1; HRTIM_EventConfig(hhrtim, @@ -3433,7 +3433,7 @@ HAL_StatusTypeDef HAL_HRTIM_SimpleOnePulseChannelConfig(HRTIM_HandleTypeDef * hh * @arg HRTIM_OUTPUT_TE2: Timer E - Output 2 * @retval HAL status */ -HAL_StatusTypeDef HAL_HRTIM_SimpleOnePulseStart(HRTIM_HandleTypeDef * hhrtim, +HAL_StatusTypeDef HAL_HRTIM_SimpleOnePulseStart(HRTIM_HandleTypeDef *hhrtim, uint32_t TimerIdx, uint32_t OnePulseChannel) { @@ -3483,9 +3483,9 @@ HAL_StatusTypeDef HAL_HRTIM_SimpleOnePulseStart(HRTIM_HandleTypeDef * hhrtim, * @arg HRTIM_OUTPUT_TE2: Timer E - Output 2 * @retval HAL status */ -HAL_StatusTypeDef HAL_HRTIM_SimpleOnePulseStop(HRTIM_HandleTypeDef * hhrtim, - uint32_t TimerIdx, - uint32_t OnePulseChannel) +HAL_StatusTypeDef HAL_HRTIM_SimpleOnePulseStop(HRTIM_HandleTypeDef *hhrtim, + uint32_t TimerIdx, + uint32_t OnePulseChannel) { /* Check the parameters */ assert_param(IS_HRTIM_TIMER_OUTPUT(TimerIdx, OnePulseChannel)); @@ -3534,9 +3534,9 @@ HAL_StatusTypeDef HAL_HRTIM_SimpleOnePulseStop(HRTIM_HandleTypeDef * hhrtim, * @arg HRTIM_OUTPUT_TE2: Timer E - Output 2 * @retval HAL status */ -HAL_StatusTypeDef HAL_HRTIM_SimpleOnePulseStart_IT(HRTIM_HandleTypeDef * hhrtim, - uint32_t TimerIdx, - uint32_t OnePulseChannel) +HAL_StatusTypeDef HAL_HRTIM_SimpleOnePulseStart_IT(HRTIM_HandleTypeDef *hhrtim, + uint32_t TimerIdx, + uint32_t OnePulseChannel) { /* Check the parameters */ assert_param(IS_HRTIM_TIMER_OUTPUT(TimerIdx, OnePulseChannel)); @@ -3552,27 +3552,27 @@ HAL_StatusTypeDef HAL_HRTIM_SimpleOnePulseStart_IT(HRTIM_HandleTypeDef * hhrtim, /* Enable the timer interrupt (depends on the OnePulse output) */ switch (OnePulseChannel) { - case HRTIM_OUTPUT_TA1: - case HRTIM_OUTPUT_TB1: - case HRTIM_OUTPUT_TC1: - case HRTIM_OUTPUT_TD1: - case HRTIM_OUTPUT_TE1: + case HRTIM_OUTPUT_TA1: + case HRTIM_OUTPUT_TB1: + case HRTIM_OUTPUT_TC1: + case HRTIM_OUTPUT_TD1: + case HRTIM_OUTPUT_TE1: { __HAL_HRTIM_TIMER_ENABLE_IT(hhrtim, TimerIdx, HRTIM_TIM_IT_CMP1); break; } - case HRTIM_OUTPUT_TA2: - case HRTIM_OUTPUT_TB2: - case HRTIM_OUTPUT_TC2: - case HRTIM_OUTPUT_TD2: - case HRTIM_OUTPUT_TE2: + case HRTIM_OUTPUT_TA2: + case HRTIM_OUTPUT_TB2: + case HRTIM_OUTPUT_TC2: + case HRTIM_OUTPUT_TD2: + case HRTIM_OUTPUT_TE2: { __HAL_HRTIM_TIMER_ENABLE_IT(hhrtim, TimerIdx, HRTIM_TIM_IT_CMP2); break; } - default: + default: { hhrtim->State = HAL_HRTIM_STATE_ERROR; @@ -3583,9 +3583,9 @@ HAL_StatusTypeDef HAL_HRTIM_SimpleOnePulseStart_IT(HRTIM_HandleTypeDef * hhrtim, } } - if(hhrtim->State == HAL_HRTIM_STATE_ERROR) + if (hhrtim->State == HAL_HRTIM_STATE_ERROR) { - return HAL_ERROR; + return HAL_ERROR; } /* Enable the timer counter */ @@ -3624,9 +3624,9 @@ HAL_StatusTypeDef HAL_HRTIM_SimpleOnePulseStart_IT(HRTIM_HandleTypeDef * hhrtim, * @arg HRTIM_OUTPUT_TE2: Timer E - Output 2 * @retval HAL status */ -HAL_StatusTypeDef HAL_HRTIM_SimpleOnePulseStop_IT(HRTIM_HandleTypeDef * hhrtim, - uint32_t TimerIdx, - uint32_t OnePulseChannel) +HAL_StatusTypeDef HAL_HRTIM_SimpleOnePulseStop_IT(HRTIM_HandleTypeDef *hhrtim, + uint32_t TimerIdx, + uint32_t OnePulseChannel) { /* Check the parameters */ assert_param(IS_HRTIM_TIMER_OUTPUT(TimerIdx, OnePulseChannel)); @@ -3642,27 +3642,27 @@ HAL_StatusTypeDef HAL_HRTIM_SimpleOnePulseStop_IT(HRTIM_HandleTypeDef * hhrtim, /* Disable the timer interrupt (depends on the OnePulse output) */ switch (OnePulseChannel) { - case HRTIM_OUTPUT_TA1: - case HRTIM_OUTPUT_TB1: - case HRTIM_OUTPUT_TC1: - case HRTIM_OUTPUT_TD1: - case HRTIM_OUTPUT_TE1: + case HRTIM_OUTPUT_TA1: + case HRTIM_OUTPUT_TB1: + case HRTIM_OUTPUT_TC1: + case HRTIM_OUTPUT_TD1: + case HRTIM_OUTPUT_TE1: { __HAL_HRTIM_TIMER_DISABLE_IT(hhrtim, TimerIdx, HRTIM_TIM_IT_CMP1); break; } - case HRTIM_OUTPUT_TA2: - case HRTIM_OUTPUT_TB2: - case HRTIM_OUTPUT_TC2: - case HRTIM_OUTPUT_TD2: - case HRTIM_OUTPUT_TE2: + case HRTIM_OUTPUT_TA2: + case HRTIM_OUTPUT_TB2: + case HRTIM_OUTPUT_TC2: + case HRTIM_OUTPUT_TD2: + case HRTIM_OUTPUT_TE2: { __HAL_HRTIM_TIMER_DISABLE_IT(hhrtim, TimerIdx, HRTIM_TIM_IT_CMP2); break; } - default: + default: { hhrtim->State = HAL_HRTIM_STATE_ERROR; @@ -3673,9 +3673,9 @@ HAL_StatusTypeDef HAL_HRTIM_SimpleOnePulseStop_IT(HRTIM_HandleTypeDef * hhrtim, } } - if(hhrtim->State == HAL_HRTIM_STATE_ERROR) + if (hhrtim->State == HAL_HRTIM_STATE_ERROR) { - return HAL_ERROR; + return HAL_ERROR; } /* Disable the timer counter */ @@ -3694,7 +3694,7 @@ HAL_StatusTypeDef HAL_HRTIM_SimpleOnePulseStop_IT(HRTIM_HandleTypeDef * hhrtim, */ /** @defgroup HRTIM_Exported_Functions_Group7 Configuration functions - * @brief HRTIM configuration functions + * @brief HRTIM configuration functions @verbatim =============================================================================== ##### HRTIM configuration functions ##### @@ -3721,8 +3721,8 @@ HAL_StatusTypeDef HAL_HRTIM_SimpleOnePulseStop_IT(HRTIM_HandleTypeDef * hhrtim, * @note This function must be called before starting the burst mode * controller */ -HAL_StatusTypeDef HAL_HRTIM_BurstModeConfig(HRTIM_HandleTypeDef * hhrtim, - const HRTIM_BurstModeCfgTypeDef* pBurstModeCfg) +HAL_StatusTypeDef HAL_HRTIM_BurstModeConfig(HRTIM_HandleTypeDef *hhrtim, + const HRTIM_BurstModeCfgTypeDef *pBurstModeCfg) { uint32_t hrtim_bmcr; @@ -3733,9 +3733,9 @@ HAL_StatusTypeDef HAL_HRTIM_BurstModeConfig(HRTIM_HandleTypeDef * hhrtim, assert_param(IS_HRTIM_BURSTMODEPRELOAD(pBurstModeCfg->PreloadEnable)); assert_param(IS_HRTIM_BURSTMODETRIGGER(pBurstModeCfg->Trigger)); - if(hhrtim->State == HAL_HRTIM_STATE_BUSY) + if (hhrtim->State == HAL_HRTIM_STATE_BUSY) { - return HAL_BUSY; + return HAL_BUSY; } /* Process Locked */ @@ -3801,9 +3801,9 @@ HAL_StatusTypeDef HAL_HRTIM_BurstModeConfig(HRTIM_HandleTypeDef * hhrtim, * @note This function must be called before starting the timer * @retval HAL status */ -HAL_StatusTypeDef HAL_HRTIM_EventConfig(HRTIM_HandleTypeDef * hhrtim, +HAL_StatusTypeDef HAL_HRTIM_EventConfig(HRTIM_HandleTypeDef *hhrtim, uint32_t Event, - const HRTIM_EventCfgTypeDef* pEventCfg) + const HRTIM_EventCfgTypeDef *pEventCfg) { /* Check parameters */ assert_param(IS_HRTIM_EVENT(Event)); @@ -3813,9 +3813,9 @@ HAL_StatusTypeDef HAL_HRTIM_EventConfig(HRTIM_HandleTypeDef * hhrtim, assert_param(IS_HRTIM_EVENTFASTMODE(Event, pEventCfg->FastMode)); assert_param(IS_HRTIM_EVENTFILTER(Event, pEventCfg->Filter)); - if(hhrtim->State == HAL_HRTIM_STATE_BUSY) + if (hhrtim->State == HAL_HRTIM_STATE_BUSY) { - return HAL_BUSY; + return HAL_BUSY; } /* Process Locked */ @@ -3846,15 +3846,15 @@ HAL_StatusTypeDef HAL_HRTIM_EventConfig(HRTIM_HandleTypeDef * hhrtim, * @note This function must be called before starting the timer * @retval HAL status */ -HAL_StatusTypeDef HAL_HRTIM_EventPrescalerConfig(HRTIM_HandleTypeDef * hhrtim, +HAL_StatusTypeDef HAL_HRTIM_EventPrescalerConfig(HRTIM_HandleTypeDef *hhrtim, uint32_t Prescaler) { /* Check parameters */ assert_param(IS_HRTIM_EVENTPRESCALER(Prescaler)); - if(hhrtim->State == HAL_HRTIM_STATE_BUSY) + if (hhrtim->State == HAL_HRTIM_STATE_BUSY) { - return HAL_BUSY; + return HAL_BUSY; } /* Process Locked */ @@ -3888,9 +3888,9 @@ HAL_StatusTypeDef HAL_HRTIM_EventPrescalerConfig(HRTIM_HandleTypeDef * hhrtim, * enabling faults inputs * @retval HAL status */ -HAL_StatusTypeDef HAL_HRTIM_FaultConfig(HRTIM_HandleTypeDef * hhrtim, +HAL_StatusTypeDef HAL_HRTIM_FaultConfig(HRTIM_HandleTypeDef *hhrtim, uint32_t Fault, - const HRTIM_FaultCfgTypeDef* pFaultCfg) + const HRTIM_FaultCfgTypeDef *pFaultCfg) { uint32_t hrtim_fltinr1; uint32_t hrtim_fltinr2; @@ -3902,9 +3902,9 @@ HAL_StatusTypeDef HAL_HRTIM_FaultConfig(HRTIM_HandleTypeDef * hhrtim, assert_param(IS_HRTIM_FAULTFILTER(pFaultCfg->Filter)); assert_param(IS_HRTIM_FAULTLOCK(pFaultCfg->Lock)); - if(hhrtim->State == HAL_HRTIM_STATE_BUSY) + if (hhrtim->State == HAL_HRTIM_STATE_BUSY) { - return HAL_BUSY; + return HAL_BUSY; } /* Process Locked */ @@ -3918,7 +3918,7 @@ HAL_StatusTypeDef HAL_HRTIM_FaultConfig(HRTIM_HandleTypeDef * hhrtim, switch (Fault) { - case HRTIM_FAULT_1: + case HRTIM_FAULT_1: { hrtim_fltinr1 &= ~(HRTIM_FLTINR1_FLT1P | HRTIM_FLTINR1_FLT1SRC | HRTIM_FLTINR1_FLT1F | HRTIM_FLTINR1_FLT1LCK); hrtim_fltinr1 |= (pFaultCfg->Polarity & HRTIM_FLTINR1_FLT1P); @@ -3928,7 +3928,7 @@ HAL_StatusTypeDef HAL_HRTIM_FaultConfig(HRTIM_HandleTypeDef * hhrtim, break; } - case HRTIM_FAULT_2: + case HRTIM_FAULT_2: { hrtim_fltinr1 &= ~(HRTIM_FLTINR1_FLT2P | HRTIM_FLTINR1_FLT2SRC | HRTIM_FLTINR1_FLT2F | HRTIM_FLTINR1_FLT2LCK); hrtim_fltinr1 |= ((pFaultCfg->Polarity << 8U) & HRTIM_FLTINR1_FLT2P); @@ -3938,7 +3938,7 @@ HAL_StatusTypeDef HAL_HRTIM_FaultConfig(HRTIM_HandleTypeDef * hhrtim, break; } - case HRTIM_FAULT_3: + case HRTIM_FAULT_3: { hrtim_fltinr1 &= ~(HRTIM_FLTINR1_FLT3P | HRTIM_FLTINR1_FLT3SRC | HRTIM_FLTINR1_FLT3F | HRTIM_FLTINR1_FLT3LCK); hrtim_fltinr1 |= ((pFaultCfg->Polarity << 16U) & HRTIM_FLTINR1_FLT3P); @@ -3946,9 +3946,9 @@ HAL_StatusTypeDef HAL_HRTIM_FaultConfig(HRTIM_HandleTypeDef * hhrtim, hrtim_fltinr1 |= ((pFaultCfg->Filter << 16U) & HRTIM_FLTINR1_FLT3F); hrtim_fltinr1 |= ((pFaultCfg->Lock << 16U) & HRTIM_FLTINR1_FLT3LCK); break; - } + } - case HRTIM_FAULT_4: + case HRTIM_FAULT_4: { hrtim_fltinr1 &= ~(HRTIM_FLTINR1_FLT4P | HRTIM_FLTINR1_FLT4SRC | HRTIM_FLTINR1_FLT4F | HRTIM_FLTINR1_FLT4LCK); hrtim_fltinr1 |= ((pFaultCfg->Polarity << 24U) & HRTIM_FLTINR1_FLT4P); @@ -3958,7 +3958,7 @@ HAL_StatusTypeDef HAL_HRTIM_FaultConfig(HRTIM_HandleTypeDef * hhrtim, break; } - case HRTIM_FAULT_5: + case HRTIM_FAULT_5: { hrtim_fltinr2 &= ~(HRTIM_FLTINR2_FLT5P | HRTIM_FLTINR2_FLT5SRC | HRTIM_FLTINR2_FLT5F | HRTIM_FLTINR2_FLT5LCK); hrtim_fltinr2 |= (pFaultCfg->Polarity & HRTIM_FLTINR2_FLT5P); @@ -3968,7 +3968,7 @@ HAL_StatusTypeDef HAL_HRTIM_FaultConfig(HRTIM_HandleTypeDef * hhrtim, break; } - default: + default: { hhrtim->State = HAL_HRTIM_STATE_ERROR; @@ -3979,9 +3979,9 @@ HAL_StatusTypeDef HAL_HRTIM_FaultConfig(HRTIM_HandleTypeDef * hhrtim, } } - if(hhrtim->State == HAL_HRTIM_STATE_ERROR) + if (hhrtim->State == HAL_HRTIM_STATE_ERROR) { - return HAL_ERROR; + return HAL_ERROR; } /* Update the HRTIM registers except LOCK bit */ @@ -3989,8 +3989,8 @@ HAL_StatusTypeDef HAL_HRTIM_FaultConfig(HRTIM_HandleTypeDef * hhrtim, hhrtim->Instance->sCommonRegs.FLTINR2 = (hrtim_fltinr2 & (~(HRTIM_FLTINR2_FLTxLCK))); /* Update the HRTIM registers LOCK bit */ - SET_BIT(hhrtim->Instance->sCommonRegs.FLTINR1,(hrtim_fltinr1 & HRTIM_FLTINR1_FLTxLCK)); - SET_BIT(hhrtim->Instance->sCommonRegs.FLTINR2,(hrtim_fltinr2 & HRTIM_FLTINR2_FLTxLCK)); + SET_BIT(hhrtim->Instance->sCommonRegs.FLTINR1, (hrtim_fltinr1 & HRTIM_FLTINR1_FLTxLCK)); + SET_BIT(hhrtim->Instance->sCommonRegs.FLTINR2, (hrtim_fltinr2 & HRTIM_FLTINR2_FLTxLCK)); hhrtim->State = HAL_HRTIM_STATE_READY; @@ -4013,15 +4013,15 @@ HAL_StatusTypeDef HAL_HRTIM_FaultConfig(HRTIM_HandleTypeDef * hhrtim, * @note This function must be called before starting the timer and before * enabling faults inputs */ -HAL_StatusTypeDef HAL_HRTIM_FaultPrescalerConfig(HRTIM_HandleTypeDef * hhrtim, +HAL_StatusTypeDef HAL_HRTIM_FaultPrescalerConfig(HRTIM_HandleTypeDef *hhrtim, uint32_t Prescaler) { /* Check parameters */ assert_param(IS_HRTIM_FAULTPRESCALER(Prescaler)); - if(hhrtim->State == HAL_HRTIM_STATE_BUSY) + if (hhrtim->State == HAL_HRTIM_STATE_BUSY) { - return HAL_BUSY; + return HAL_BUSY; } /* Process Locked */ @@ -4056,9 +4056,9 @@ HAL_StatusTypeDef HAL_HRTIM_FaultPrescalerConfig(HRTIM_HandleTypeDef * hhrtim, * @arg HRTIM_FAULTMODECTL_DISABLED: Fault(s) disabled * @retval None */ -void HAL_HRTIM_FaultModeCtl(HRTIM_HandleTypeDef * hhrtim, - uint32_t Faults, - uint32_t Enable) +void HAL_HRTIM_FaultModeCtl(HRTIM_HandleTypeDef *hhrtim, + uint32_t Faults, + uint32_t Enable) { /* Check parameters */ assert_param(IS_HRTIM_FAULT(Faults)); @@ -4100,9 +4100,9 @@ void HAL_HRTIM_FaultModeCtl(HRTIM_HandleTypeDef * hhrtim, * @retval HAL status * @note This function must be called before starting the timer */ -HAL_StatusTypeDef HAL_HRTIM_ADCTriggerConfig(HRTIM_HandleTypeDef * hhrtim, +HAL_StatusTypeDef HAL_HRTIM_ADCTriggerConfig(HRTIM_HandleTypeDef *hhrtim, uint32_t ADCTrigger, - const HRTIM_ADCTriggerCfgTypeDef* pADCTriggerCfg) + const HRTIM_ADCTriggerCfgTypeDef *pADCTriggerCfg) { uint32_t hrtim_cr1; @@ -4110,9 +4110,9 @@ HAL_StatusTypeDef HAL_HRTIM_ADCTriggerConfig(HRTIM_HandleTypeDef * hhrtim, assert_param(IS_HRTIM_ADCTRIGGER(ADCTrigger)); assert_param(IS_HRTIM_ADCTRIGGERUPDATE(pADCTriggerCfg->UpdateSource)); - if(hhrtim->State == HAL_HRTIM_STATE_BUSY) + if (hhrtim->State == HAL_HRTIM_STATE_BUSY) { - return HAL_BUSY; + return HAL_BUSY; } /* Process Locked */ @@ -4125,7 +4125,7 @@ HAL_StatusTypeDef HAL_HRTIM_ADCTriggerConfig(HRTIM_HandleTypeDef * hhrtim, switch (ADCTrigger) { - case HRTIM_ADCTRIGGER_1: + case HRTIM_ADCTRIGGER_1: { hrtim_cr1 &= ~(HRTIM_CR1_ADC1USRC); hrtim_cr1 |= (pADCTriggerCfg->UpdateSource & HRTIM_CR1_ADC1USRC); @@ -4135,7 +4135,7 @@ HAL_StatusTypeDef HAL_HRTIM_ADCTriggerConfig(HRTIM_HandleTypeDef * hhrtim, break; } - case HRTIM_ADCTRIGGER_2: + case HRTIM_ADCTRIGGER_2: { hrtim_cr1 &= ~(HRTIM_CR1_ADC2USRC); hrtim_cr1 |= ((pADCTriggerCfg->UpdateSource << 3U) & HRTIM_CR1_ADC2USRC); @@ -4145,7 +4145,7 @@ HAL_StatusTypeDef HAL_HRTIM_ADCTriggerConfig(HRTIM_HandleTypeDef * hhrtim, break; } - case HRTIM_ADCTRIGGER_3: + case HRTIM_ADCTRIGGER_3: { hrtim_cr1 &= ~(HRTIM_CR1_ADC3USRC); hrtim_cr1 |= ((pADCTriggerCfg->UpdateSource << 6U) & HRTIM_CR1_ADC3USRC); @@ -4155,7 +4155,7 @@ HAL_StatusTypeDef HAL_HRTIM_ADCTriggerConfig(HRTIM_HandleTypeDef * hhrtim, break; } - case HRTIM_ADCTRIGGER_4: + case HRTIM_ADCTRIGGER_4: { hrtim_cr1 &= ~(HRTIM_CR1_ADC4USRC); hrtim_cr1 |= ((pADCTriggerCfg->UpdateSource << 9U) & HRTIM_CR1_ADC4USRC); @@ -4165,7 +4165,7 @@ HAL_StatusTypeDef HAL_HRTIM_ADCTriggerConfig(HRTIM_HandleTypeDef * hhrtim, break; } - default: + default: { hhrtim->State = HAL_HRTIM_STATE_ERROR; @@ -4176,9 +4176,9 @@ HAL_StatusTypeDef HAL_HRTIM_ADCTriggerConfig(HRTIM_HandleTypeDef * hhrtim, } } - if(hhrtim->State == HAL_HRTIM_STATE_ERROR) + if (hhrtim->State == HAL_HRTIM_STATE_ERROR) { - return HAL_ERROR; + return HAL_ERROR; } /* Update the HRTIM registers */ @@ -4198,7 +4198,7 @@ HAL_StatusTypeDef HAL_HRTIM_ADCTriggerConfig(HRTIM_HandleTypeDef * hhrtim, */ /** @defgroup HRTIM_Exported_Functions_Group8 Timer waveform configuration and functions - * @brief HRTIM timer configuration and control functions + * @brief HRTIM timer configuration and control functions @verbatim =============================================================================== ##### HRTIM timer configuration and control functions ##### @@ -4252,9 +4252,9 @@ HAL_StatusTypeDef HAL_HRTIM_ADCTriggerConfig(HRTIM_HandleTypeDef * hhrtim, * @retval HAL status * @note This function must be called before starting the timer */ -HAL_StatusTypeDef HAL_HRTIM_WaveformTimerConfig(HRTIM_HandleTypeDef * hhrtim, +HAL_StatusTypeDef HAL_HRTIM_WaveformTimerConfig(HRTIM_HandleTypeDef *hhrtim, uint32_t TimerIdx, - const HRTIM_TimerCfgTypeDef * pTimerCfg) + const HRTIM_TimerCfgTypeDef *pTimerCfg) { /* Check parameters */ assert_param(IS_HRTIM_TIMERINDEX(TimerIdx)); @@ -4268,9 +4268,9 @@ HAL_StatusTypeDef HAL_HRTIM_WaveformTimerConfig(HRTIM_HandleTypeDef * hhrtim, assert_param(IS_HRTIM_TIMERBURSTMODE(pTimerCfg->BurstMode)); assert_param(IS_HRTIM_UPDATEONREPETITION(pTimerCfg->RepetitionUpdate)); - if(hhrtim->State == HAL_HRTIM_STATE_BUSY) + if (hhrtim->State == HAL_HRTIM_STATE_BUSY) { - return HAL_BUSY; + return HAL_BUSY; } /* Process Locked */ @@ -4353,10 +4353,10 @@ HAL_StatusTypeDef HAL_HRTIM_WaveformTimerConfig(HRTIM_HandleTypeDef * hhrtim, * @note This function must be called before starting the timer * @retval HAL status */ -HAL_StatusTypeDef HAL_HRTIM_TimerEventFilteringConfig(HRTIM_HandleTypeDef * hhrtim, +HAL_StatusTypeDef HAL_HRTIM_TimerEventFilteringConfig(HRTIM_HandleTypeDef *hhrtim, uint32_t TimerIdx, uint32_t Event, - const HRTIM_TimerEventFilteringCfgTypeDef* pTimerEventFilteringCfg) + const HRTIM_TimerEventFilteringCfgTypeDef *pTimerEventFilteringCfg) { /* Check parameters */ assert_param(IS_HRTIM_TIMING_UNIT(TimerIdx)); @@ -4365,9 +4365,9 @@ HAL_StatusTypeDef HAL_HRTIM_TimerEventFilteringConfig(HRTIM_HandleTypeDef * hhrt assert_param(IS_HRTIM_TIMEVENTLATCH(pTimerEventFilteringCfg->Latch)); - if(hhrtim->State == HAL_HRTIM_STATE_BUSY) + if (hhrtim->State == HAL_HRTIM_STATE_BUSY) { - return HAL_BUSY; + return HAL_BUSY; } /* Process Locked */ @@ -4378,75 +4378,85 @@ HAL_StatusTypeDef HAL_HRTIM_TimerEventFilteringConfig(HRTIM_HandleTypeDef * hhrt /* Configure timer event filtering capabilities */ switch (Event) { - case HRTIM_EVENT_NONE: + case HRTIM_EVENT_NONE: { CLEAR_REG(hhrtim->Instance->sTimerxRegs[TimerIdx].EEFxR1); CLEAR_REG(hhrtim->Instance->sTimerxRegs[TimerIdx].EEFxR2); break; } - case HRTIM_EVENT_1: + case HRTIM_EVENT_1: { - MODIFY_REG(hhrtim->Instance->sTimerxRegs[TimerIdx].EEFxR1, (HRTIM_EEFR1_EE1FLTR | HRTIM_EEFR1_EE1LTCH), (pTimerEventFilteringCfg->Filter | pTimerEventFilteringCfg->Latch)); + MODIFY_REG(hhrtim->Instance->sTimerxRegs[TimerIdx].EEFxR1, (HRTIM_EEFR1_EE1FLTR | HRTIM_EEFR1_EE1LTCH), + (pTimerEventFilteringCfg->Filter | pTimerEventFilteringCfg->Latch)); break; } - case HRTIM_EVENT_2: + case HRTIM_EVENT_2: { - MODIFY_REG(hhrtim->Instance->sTimerxRegs[TimerIdx].EEFxR1, (HRTIM_EEFR1_EE2FLTR | HRTIM_EEFR1_EE2LTCH), ((pTimerEventFilteringCfg->Filter | pTimerEventFilteringCfg->Latch) << 6U) ); + MODIFY_REG(hhrtim->Instance->sTimerxRegs[TimerIdx].EEFxR1, (HRTIM_EEFR1_EE2FLTR | HRTIM_EEFR1_EE2LTCH), + ((pTimerEventFilteringCfg->Filter | pTimerEventFilteringCfg->Latch) << 6U)); break; } - case HRTIM_EVENT_3: + case HRTIM_EVENT_3: { - MODIFY_REG(hhrtim->Instance->sTimerxRegs[TimerIdx].EEFxR1, (HRTIM_EEFR1_EE3FLTR | HRTIM_EEFR1_EE3LTCH), ((pTimerEventFilteringCfg->Filter | pTimerEventFilteringCfg->Latch) << 12U) ); + MODIFY_REG(hhrtim->Instance->sTimerxRegs[TimerIdx].EEFxR1, (HRTIM_EEFR1_EE3FLTR | HRTIM_EEFR1_EE3LTCH), + ((pTimerEventFilteringCfg->Filter | pTimerEventFilteringCfg->Latch) << 12U)); break; } - case HRTIM_EVENT_4: + case HRTIM_EVENT_4: { - MODIFY_REG(hhrtim->Instance->sTimerxRegs[TimerIdx].EEFxR1, (HRTIM_EEFR1_EE4FLTR | HRTIM_EEFR1_EE4LTCH), ((pTimerEventFilteringCfg->Filter | pTimerEventFilteringCfg->Latch) << 18U) ); + MODIFY_REG(hhrtim->Instance->sTimerxRegs[TimerIdx].EEFxR1, (HRTIM_EEFR1_EE4FLTR | HRTIM_EEFR1_EE4LTCH), + ((pTimerEventFilteringCfg->Filter | pTimerEventFilteringCfg->Latch) << 18U)); break; } - case HRTIM_EVENT_5: + case HRTIM_EVENT_5: { - MODIFY_REG(hhrtim->Instance->sTimerxRegs[TimerIdx].EEFxR1, (HRTIM_EEFR1_EE5FLTR | HRTIM_EEFR1_EE5LTCH), ((pTimerEventFilteringCfg->Filter | pTimerEventFilteringCfg->Latch) << 24U) ); + MODIFY_REG(hhrtim->Instance->sTimerxRegs[TimerIdx].EEFxR1, (HRTIM_EEFR1_EE5FLTR | HRTIM_EEFR1_EE5LTCH), + ((pTimerEventFilteringCfg->Filter | pTimerEventFilteringCfg->Latch) << 24U)); break; } - case HRTIM_EVENT_6: + case HRTIM_EVENT_6: { - MODIFY_REG(hhrtim->Instance->sTimerxRegs[TimerIdx].EEFxR2, (HRTIM_EEFR2_EE6FLTR | HRTIM_EEFR2_EE6LTCH), (pTimerEventFilteringCfg->Filter | pTimerEventFilteringCfg->Latch) ); + MODIFY_REG(hhrtim->Instance->sTimerxRegs[TimerIdx].EEFxR2, (HRTIM_EEFR2_EE6FLTR | HRTIM_EEFR2_EE6LTCH), + (pTimerEventFilteringCfg->Filter | pTimerEventFilteringCfg->Latch)); break; } - case HRTIM_EVENT_7: + case HRTIM_EVENT_7: { - MODIFY_REG(hhrtim->Instance->sTimerxRegs[TimerIdx].EEFxR2, (HRTIM_EEFR2_EE7FLTR | HRTIM_EEFR2_EE7LTCH), ((pTimerEventFilteringCfg->Filter | pTimerEventFilteringCfg->Latch) << 6U) ); + MODIFY_REG(hhrtim->Instance->sTimerxRegs[TimerIdx].EEFxR2, (HRTIM_EEFR2_EE7FLTR | HRTIM_EEFR2_EE7LTCH), + ((pTimerEventFilteringCfg->Filter | pTimerEventFilteringCfg->Latch) << 6U)); break; } - case HRTIM_EVENT_8: + case HRTIM_EVENT_8: { - MODIFY_REG(hhrtim->Instance->sTimerxRegs[TimerIdx].EEFxR2, (HRTIM_EEFR2_EE8FLTR | HRTIM_EEFR2_EE8LTCH), ((pTimerEventFilteringCfg->Filter | pTimerEventFilteringCfg->Latch) << 12U) ); + MODIFY_REG(hhrtim->Instance->sTimerxRegs[TimerIdx].EEFxR2, (HRTIM_EEFR2_EE8FLTR | HRTIM_EEFR2_EE8LTCH), + ((pTimerEventFilteringCfg->Filter | pTimerEventFilteringCfg->Latch) << 12U)); break; } - case HRTIM_EVENT_9: + case HRTIM_EVENT_9: { - MODIFY_REG(hhrtim->Instance->sTimerxRegs[TimerIdx].EEFxR2, (HRTIM_EEFR2_EE9FLTR | HRTIM_EEFR2_EE9LTCH), ((pTimerEventFilteringCfg->Filter | pTimerEventFilteringCfg->Latch) << 18U) ); + MODIFY_REG(hhrtim->Instance->sTimerxRegs[TimerIdx].EEFxR2, (HRTIM_EEFR2_EE9FLTR | HRTIM_EEFR2_EE9LTCH), + ((pTimerEventFilteringCfg->Filter | pTimerEventFilteringCfg->Latch) << 18U)); break; } - case HRTIM_EVENT_10: + case HRTIM_EVENT_10: { - MODIFY_REG(hhrtim->Instance->sTimerxRegs[TimerIdx].EEFxR2, (HRTIM_EEFR2_EE10FLTR | HRTIM_EEFR2_EE10LTCH), ((pTimerEventFilteringCfg->Filter | pTimerEventFilteringCfg->Latch) << 24U) ); + MODIFY_REG(hhrtim->Instance->sTimerxRegs[TimerIdx].EEFxR2, (HRTIM_EEFR2_EE10FLTR | HRTIM_EEFR2_EE10LTCH), + ((pTimerEventFilteringCfg->Filter | pTimerEventFilteringCfg->Latch) << 24U)); break; } - default: - { + default: + { hhrtim->State = HAL_HRTIM_STATE_ERROR; /* Process Unlocked */ @@ -4456,9 +4466,9 @@ HAL_StatusTypeDef HAL_HRTIM_TimerEventFilteringConfig(HRTIM_HandleTypeDef * hhrt } } - if(hhrtim->State == HAL_HRTIM_STATE_ERROR) + if (hhrtim->State == HAL_HRTIM_STATE_ERROR) { - return HAL_ERROR; + return HAL_ERROR; } hhrtim->State = HAL_HRTIM_STATE_READY; @@ -4483,9 +4493,9 @@ HAL_StatusTypeDef HAL_HRTIM_TimerEventFilteringConfig(HRTIM_HandleTypeDef * hhrt * @retval HAL status * @note This function must be called before starting the timer */ -HAL_StatusTypeDef HAL_HRTIM_DeadTimeConfig(HRTIM_HandleTypeDef * hhrtim, +HAL_StatusTypeDef HAL_HRTIM_DeadTimeConfig(HRTIM_HandleTypeDef *hhrtim, uint32_t TimerIdx, - const HRTIM_DeadTimeCfgTypeDef* pDeadTimeCfg) + const HRTIM_DeadTimeCfgTypeDef *pDeadTimeCfg) { uint32_t hrtim_dtr; @@ -4499,9 +4509,9 @@ HAL_StatusTypeDef HAL_HRTIM_DeadTimeConfig(HRTIM_HandleTypeDef * hhrtim, assert_param(IS_HRTIM_TIMDEADTIME_FALLINGLOCK(pDeadTimeCfg->FallingLock)); assert_param(IS_HRTIM_TIMDEADTIME_FALLINGSIGNLOCK(pDeadTimeCfg->FallingSignLock)); - if(hhrtim->State == HAL_HRTIM_STATE_BUSY) + if (hhrtim->State == HAL_HRTIM_STATE_BUSY) { - return HAL_BUSY; + return HAL_BUSY; } /* Process Locked */ @@ -4522,9 +4532,9 @@ HAL_StatusTypeDef HAL_HRTIM_DeadTimeConfig(HRTIM_HandleTypeDef * hhrtim, /* Update the HRTIM registers */ MODIFY_REG(hhrtim->Instance->sTimerxRegs[TimerIdx].DTxR, ( - HRTIM_DTR_DTR | HRTIM_DTR_SDTR | HRTIM_DTR_DTPRSC | - HRTIM_DTR_DTRSLK | HRTIM_DTR_DTRLK | HRTIM_DTR_DTF | - HRTIM_DTR_SDTF | HRTIM_DTR_DTFSLK | HRTIM_DTR_DTFLK), hrtim_dtr); + HRTIM_DTR_DTR | HRTIM_DTR_SDTR | HRTIM_DTR_DTPRSC | + HRTIM_DTR_DTRSLK | HRTIM_DTR_DTRLK | HRTIM_DTR_DTF | + HRTIM_DTR_SDTF | HRTIM_DTR_DTFSLK | HRTIM_DTR_DTFLK), hrtim_dtr); hhrtim->State = HAL_HRTIM_STATE_READY; @@ -4548,9 +4558,9 @@ HAL_StatusTypeDef HAL_HRTIM_DeadTimeConfig(HRTIM_HandleTypeDef * hhrtim, * @retval HAL status * @note This function must be called before configuring the timer output(s) */ -HAL_StatusTypeDef HAL_HRTIM_ChopperModeConfig(HRTIM_HandleTypeDef * hhrtim, +HAL_StatusTypeDef HAL_HRTIM_ChopperModeConfig(HRTIM_HandleTypeDef *hhrtim, uint32_t TimerIdx, - const HRTIM_ChopperModeCfgTypeDef* pChopperModeCfg) + const HRTIM_ChopperModeCfgTypeDef *pChopperModeCfg) { uint32_t hrtim_chpr; @@ -4560,9 +4570,9 @@ HAL_StatusTypeDef HAL_HRTIM_ChopperModeConfig(HRTIM_HandleTypeDef * hhrtim, assert_param(IS_HRTIM_CHOPPER_DUTYCYCLE(pChopperModeCfg->DutyCycle)); assert_param(IS_HRTIM_CHOPPER_PULSEWIDTH(pChopperModeCfg->StartPulse)); - if(hhrtim->State == HAL_HRTIM_STATE_BUSY) + if (hhrtim->State == HAL_HRTIM_STATE_BUSY) { - return HAL_BUSY; + return HAL_BUSY; } /* Process Locked */ @@ -4625,16 +4635,16 @@ HAL_StatusTypeDef HAL_HRTIM_ChopperModeConfig(HRTIM_HandleTypeDef * hhrtim, * @retval HAL status * @note This function must be called before starting the timer */ -HAL_StatusTypeDef HAL_HRTIM_BurstDMAConfig(HRTIM_HandleTypeDef * hhrtim, +HAL_StatusTypeDef HAL_HRTIM_BurstDMAConfig(HRTIM_HandleTypeDef *hhrtim, uint32_t TimerIdx, uint32_t RegistersToUpdate) { /* Check parameters */ assert_param(IS_HRTIM_TIMER_BURSTDMA(TimerIdx, RegistersToUpdate)); - if(hhrtim->State == HAL_HRTIM_STATE_BUSY) + if (hhrtim->State == HAL_HRTIM_STATE_BUSY) { - return HAL_BUSY; + return HAL_BUSY; } /* Process Locked */ @@ -4645,44 +4655,44 @@ HAL_StatusTypeDef HAL_HRTIM_BurstDMAConfig(HRTIM_HandleTypeDef * hhrtim, /* Set the burst DMA timer update register */ switch (TimerIdx) { - case HRTIM_TIMERINDEX_TIMER_A: + case HRTIM_TIMERINDEX_TIMER_A: { hhrtim->Instance->sCommonRegs.BDTAUPR = RegistersToUpdate; break; } - case HRTIM_TIMERINDEX_TIMER_B: + case HRTIM_TIMERINDEX_TIMER_B: { hhrtim->Instance->sCommonRegs.BDTBUPR = RegistersToUpdate; break; } - case HRTIM_TIMERINDEX_TIMER_C: + case HRTIM_TIMERINDEX_TIMER_C: { hhrtim->Instance->sCommonRegs.BDTCUPR = RegistersToUpdate; break; } - case HRTIM_TIMERINDEX_TIMER_D: + case HRTIM_TIMERINDEX_TIMER_D: { hhrtim->Instance->sCommonRegs.BDTDUPR = RegistersToUpdate; break; } - case HRTIM_TIMERINDEX_TIMER_E: + case HRTIM_TIMERINDEX_TIMER_E: { hhrtim->Instance->sCommonRegs.BDTEUPR = RegistersToUpdate; break; } - case HRTIM_TIMERINDEX_MASTER: + case HRTIM_TIMERINDEX_MASTER: { hhrtim->Instance->sCommonRegs.BDMUPR = RegistersToUpdate; break; } - default: - { + default: + { hhrtim->State = HAL_HRTIM_STATE_ERROR; /* Process Unlocked */ @@ -4692,9 +4702,9 @@ HAL_StatusTypeDef HAL_HRTIM_BurstDMAConfig(HRTIM_HandleTypeDef * hhrtim, } } - if(hhrtim->State == HAL_HRTIM_STATE_ERROR) + if (hhrtim->State == HAL_HRTIM_STATE_ERROR) { - return HAL_ERROR; + return HAL_ERROR; } hhrtim->State = HAL_HRTIM_STATE_READY; @@ -4732,17 +4742,17 @@ HAL_StatusTypeDef HAL_HRTIM_BurstDMAConfig(HRTIM_HandleTypeDef * hhrtim, * @retval HAL status * @note This function must be called before starting the timer */ -HAL_StatusTypeDef HAL_HRTIM_WaveformCompareConfig(HRTIM_HandleTypeDef * hhrtim, +HAL_StatusTypeDef HAL_HRTIM_WaveformCompareConfig(HRTIM_HandleTypeDef *hhrtim, uint32_t TimerIdx, uint32_t CompareUnit, - const HRTIM_CompareCfgTypeDef* pCompareCfg) + const HRTIM_CompareCfgTypeDef *pCompareCfg) { /* Check parameters */ assert_param(IS_HRTIM_TIMERINDEX(TimerIdx)); - if(hhrtim->State == HAL_HRTIM_STATE_BUSY) + if (hhrtim->State == HAL_HRTIM_STATE_BUSY) { - return HAL_BUSY; + return HAL_BUSY; } /* Process Locked */ @@ -4756,43 +4766,43 @@ HAL_StatusTypeDef HAL_HRTIM_WaveformCompareConfig(HRTIM_HandleTypeDef * hhrtim, switch (CompareUnit) { case HRTIM_COMPAREUNIT_1: - { + { hhrtim->Instance->sMasterRegs.MCMP1R = pCompareCfg->CompareValue; break; - } + } case HRTIM_COMPAREUNIT_2: - { + { hhrtim->Instance->sMasterRegs.MCMP2R = pCompareCfg->CompareValue; break; - } + } case HRTIM_COMPAREUNIT_3: - { + { hhrtim->Instance->sMasterRegs.MCMP3R = pCompareCfg->CompareValue; break; - } + } case HRTIM_COMPAREUNIT_4: - { + { hhrtim->Instance->sMasterRegs.MCMP4R = pCompareCfg->CompareValue; break; - } + } default: - { + { hhrtim->State = HAL_HRTIM_STATE_ERROR; /* Process Unlocked */ __HAL_UNLOCK(hhrtim); break; - } + } } - if(hhrtim->State == HAL_HRTIM_STATE_ERROR) + if (hhrtim->State == HAL_HRTIM_STATE_ERROR) { - return HAL_ERROR; + return HAL_ERROR; } } @@ -4800,14 +4810,14 @@ HAL_StatusTypeDef HAL_HRTIM_WaveformCompareConfig(HRTIM_HandleTypeDef * hhrtim, { switch (CompareUnit) { - case HRTIM_COMPAREUNIT_1: + case HRTIM_COMPAREUNIT_1: { /* Set the compare value */ hhrtim->Instance->sTimerxRegs[TimerIdx].CMP1xR = pCompareCfg->CompareValue; break; } - case HRTIM_COMPAREUNIT_2: + case HRTIM_COMPAREUNIT_2: { /* Check parameters */ assert_param(IS_HRTIM_COMPAREUNIT_AUTODELAYEDMODE(CompareUnit, pCompareCfg->AutoDelayedMode)); @@ -4842,17 +4852,17 @@ HAL_StatusTypeDef HAL_HRTIM_WaveformCompareConfig(HRTIM_HandleTypeDef * hhrtim, /* Clear HRTIM_TIMxCR.DELCMP2 bitfield */ MODIFY_REG(hhrtim->Instance->sTimerxRegs[TimerIdx].TIMxCR, HRTIM_TIMCR_DELCMP2, 0U); } - break; + break; } - case HRTIM_COMPAREUNIT_3: + case HRTIM_COMPAREUNIT_3: { /* Set the compare value */ hhrtim->Instance->sTimerxRegs[TimerIdx].CMP3xR = pCompareCfg->CompareValue; break; } - case HRTIM_COMPAREUNIT_4: + case HRTIM_COMPAREUNIT_4: { /* Check parameters */ assert_param(IS_HRTIM_COMPAREUNIT_AUTODELAYEDMODE(CompareUnit, pCompareCfg->AutoDelayedMode)); @@ -4887,24 +4897,24 @@ HAL_StatusTypeDef HAL_HRTIM_WaveformCompareConfig(HRTIM_HandleTypeDef * hhrtim, /* Clear HRTIM_TIMxCR.DELCMP4 bitfield */ MODIFY_REG(hhrtim->Instance->sTimerxRegs[TimerIdx].TIMxCR, HRTIM_TIMCR_DELCMP4, 0U); } - break; + break; } - default: - { - hhrtim->State = HAL_HRTIM_STATE_ERROR; + default: + { + hhrtim->State = HAL_HRTIM_STATE_ERROR; - /* Process Unlocked */ - __HAL_UNLOCK(hhrtim); + /* Process Unlocked */ + __HAL_UNLOCK(hhrtim); - break; - } - } + break; + } + } - if(hhrtim->State == HAL_HRTIM_STATE_ERROR) - { - return HAL_ERROR; - } + if (hhrtim->State == HAL_HRTIM_STATE_ERROR) + { + return HAL_ERROR; + } } hhrtim->State = HAL_HRTIM_STATE_READY; @@ -4933,18 +4943,18 @@ HAL_StatusTypeDef HAL_HRTIM_WaveformCompareConfig(HRTIM_HandleTypeDef * hhrtim, * @retval HAL status * @note This function must be called before starting the timer */ -HAL_StatusTypeDef HAL_HRTIM_WaveformCaptureConfig(HRTIM_HandleTypeDef * hhrtim, +HAL_StatusTypeDef HAL_HRTIM_WaveformCaptureConfig(HRTIM_HandleTypeDef *hhrtim, uint32_t TimerIdx, uint32_t CaptureUnit, - const HRTIM_CaptureCfgTypeDef* pCaptureCfg) + const HRTIM_CaptureCfgTypeDef *pCaptureCfg) { /* Check parameters */ assert_param(IS_HRTIM_TIMER_CAPTURETRIGGER(TimerIdx, pCaptureCfg->Trigger)); - if(hhrtim->State == HAL_HRTIM_STATE_BUSY) + if (hhrtim->State == HAL_HRTIM_STATE_BUSY) { - return HAL_BUSY; + return HAL_BUSY; } /* Process Locked */ @@ -4955,19 +4965,19 @@ HAL_StatusTypeDef HAL_HRTIM_WaveformCaptureConfig(HRTIM_HandleTypeDef * hhrtim, /* Configure the capture unit */ switch (CaptureUnit) { - case HRTIM_CAPTUREUNIT_1: + case HRTIM_CAPTUREUNIT_1: { WRITE_REG(hhrtim->Instance->sTimerxRegs[TimerIdx].CPT1xCR, pCaptureCfg->Trigger); break; } - case HRTIM_CAPTUREUNIT_2: + case HRTIM_CAPTUREUNIT_2: { WRITE_REG(hhrtim->Instance->sTimerxRegs[TimerIdx].CPT2xCR, pCaptureCfg->Trigger); break; } - default: + default: { hhrtim->State = HAL_HRTIM_STATE_ERROR; @@ -4978,9 +4988,9 @@ HAL_StatusTypeDef HAL_HRTIM_WaveformCaptureConfig(HRTIM_HandleTypeDef * hhrtim, } } - if(hhrtim->State == HAL_HRTIM_STATE_ERROR) + if (hhrtim->State == HAL_HRTIM_STATE_ERROR) { - return HAL_ERROR; + return HAL_ERROR; } @@ -5019,10 +5029,10 @@ HAL_StatusTypeDef HAL_HRTIM_WaveformCaptureConfig(HRTIM_HandleTypeDef * hhrtim, * @note This function must be called before configuring the timer and after * configuring the deadtime insertion feature (if required). */ -HAL_StatusTypeDef HAL_HRTIM_WaveformOutputConfig(HRTIM_HandleTypeDef * hhrtim, - uint32_t TimerIdx, - uint32_t Output, - const HRTIM_OutputCfgTypeDef * pOutputCfg) +HAL_StatusTypeDef HAL_HRTIM_WaveformOutputConfig(HRTIM_HandleTypeDef *hhrtim, + uint32_t TimerIdx, + uint32_t Output, + const HRTIM_OutputCfgTypeDef *pOutputCfg) { /* Check parameters */ assert_param(IS_HRTIM_TIMER_OUTPUT(TimerIdx, Output)); @@ -5033,9 +5043,9 @@ HAL_StatusTypeDef HAL_HRTIM_WaveformOutputConfig(HRTIM_HandleTypeDef * hhrtim, assert_param(IS_HRTIM_OUTPUTCHOPPERMODE(pOutputCfg->ChopperModeEnable)); assert_param(IS_HRTIM_OUTPUTBURSTMODEENTRY(pOutputCfg->BurstModeEntryDelayed)); - if(hhrtim->State == HAL_HRTIM_STATE_BUSY) + if (hhrtim->State == HAL_HRTIM_STATE_BUSY) { - return HAL_BUSY; + return HAL_BUSY; } /* Process Locked */ @@ -5087,7 +5097,7 @@ HAL_StatusTypeDef HAL_HRTIM_WaveformOutputConfig(HRTIM_HandleTypeDef * hhrtim, * @note The 'software set/reset trigger' bit in the output set/reset registers * is automatically reset by hardware */ -HAL_StatusTypeDef HAL_HRTIM_WaveformSetOutputLevel(HRTIM_HandleTypeDef * hhrtim, +HAL_StatusTypeDef HAL_HRTIM_WaveformSetOutputLevel(HRTIM_HandleTypeDef *hhrtim, uint32_t TimerIdx, uint32_t Output, uint32_t OutputLevel) @@ -5096,9 +5106,9 @@ HAL_StatusTypeDef HAL_HRTIM_WaveformSetOutputLevel(HRTIM_HandleTypeDef * hhrtim, assert_param(IS_HRTIM_TIMER_OUTPUT(TimerIdx, Output)); assert_param(IS_HRTIM_OUTPUTLEVEL(OutputLevel)); - if(hhrtim->State == HAL_HRTIM_STATE_BUSY) + if (hhrtim->State == HAL_HRTIM_STATE_BUSY) { - return HAL_BUSY; + return HAL_BUSY; } /* Process Locked */ @@ -5109,16 +5119,16 @@ HAL_StatusTypeDef HAL_HRTIM_WaveformSetOutputLevel(HRTIM_HandleTypeDef * hhrtim, /* Force timer output level */ switch (Output) { - case HRTIM_OUTPUT_TA1: - case HRTIM_OUTPUT_TB1: - case HRTIM_OUTPUT_TC1: - case HRTIM_OUTPUT_TD1: - case HRTIM_OUTPUT_TE1: + case HRTIM_OUTPUT_TA1: + case HRTIM_OUTPUT_TB1: + case HRTIM_OUTPUT_TC1: + case HRTIM_OUTPUT_TD1: + case HRTIM_OUTPUT_TE1: { if (OutputLevel == HRTIM_OUTPUTLEVEL_ACTIVE) { /* Force output to its active state */ - SET_BIT(hhrtim->Instance->sTimerxRegs[TimerIdx].SETx1R,HRTIM_SET1R_SST); + SET_BIT(hhrtim->Instance->sTimerxRegs[TimerIdx].SETx1R, HRTIM_SET1R_SST); } else { @@ -5128,11 +5138,11 @@ HAL_StatusTypeDef HAL_HRTIM_WaveformSetOutputLevel(HRTIM_HandleTypeDef * hhrtim, break; } - case HRTIM_OUTPUT_TA2: - case HRTIM_OUTPUT_TB2: - case HRTIM_OUTPUT_TC2: - case HRTIM_OUTPUT_TD2: - case HRTIM_OUTPUT_TE2: + case HRTIM_OUTPUT_TA2: + case HRTIM_OUTPUT_TB2: + case HRTIM_OUTPUT_TC2: + case HRTIM_OUTPUT_TD2: + case HRTIM_OUTPUT_TE2: { if (OutputLevel == HRTIM_OUTPUTLEVEL_ACTIVE) { @@ -5147,7 +5157,7 @@ HAL_StatusTypeDef HAL_HRTIM_WaveformSetOutputLevel(HRTIM_HandleTypeDef * hhrtim, break; } - default: + default: { hhrtim->State = HAL_HRTIM_STATE_ERROR; @@ -5158,9 +5168,9 @@ HAL_StatusTypeDef HAL_HRTIM_WaveformSetOutputLevel(HRTIM_HandleTypeDef * hhrtim, } } - if(hhrtim->State == HAL_HRTIM_STATE_ERROR) + if (hhrtim->State == HAL_HRTIM_STATE_ERROR) { - return HAL_ERROR; + return HAL_ERROR; } hhrtim->State = HAL_HRTIM_STATE_READY; @@ -5189,10 +5199,10 @@ HAL_StatusTypeDef HAL_HRTIM_WaveformSetOutputLevel(HRTIM_HandleTypeDef * hhrtim, * @arg HRTIM_OUTPUT_TE2: Timer E - Output 2 * @retval HAL status */ -HAL_StatusTypeDef HAL_HRTIM_WaveformOutputStart(HRTIM_HandleTypeDef * hhrtim, +HAL_StatusTypeDef HAL_HRTIM_WaveformOutputStart(HRTIM_HandleTypeDef *hhrtim, uint32_t OutputsToStart) { - /* Check the parameters */ + /* Check the parameters */ assert_param(IS_HRTIM_OUTPUT(OutputsToStart)); /* Process Locked */ @@ -5229,10 +5239,10 @@ HAL_StatusTypeDef HAL_HRTIM_WaveformOutputStart(HRTIM_HandleTypeDef * hhrtim, * @arg HRTIM_OUTPUT_TE2: Timer E - Output 2 * @retval HAL status */ -HAL_StatusTypeDef HAL_HRTIM_WaveformOutputStop(HRTIM_HandleTypeDef * hhrtim, +HAL_StatusTypeDef HAL_HRTIM_WaveformOutputStop(HRTIM_HandleTypeDef *hhrtim, uint32_t OutputsToStop) { - /* Check the parameters */ + /* Check the parameters */ assert_param(IS_HRTIM_OUTPUT(OutputsToStop)); /* Process Locked */ @@ -5265,8 +5275,8 @@ HAL_StatusTypeDef HAL_HRTIM_WaveformOutputStop(HRTIM_HandleTypeDef * hhrtim, * @arg HRTIM_TIMERID_TIMER_E * @retval HAL status */ -HAL_StatusTypeDef HAL_HRTIM_WaveformCountStart(HRTIM_HandleTypeDef * hhrtim, - uint32_t Timers) +HAL_StatusTypeDef HAL_HRTIM_WaveformCountStart(HRTIM_HandleTypeDef *hhrtim, + uint32_t Timers) { /* Check the parameters */ assert_param(IS_HRTIM_TIMERID(Timers)); @@ -5302,8 +5312,8 @@ HAL_StatusTypeDef HAL_HRTIM_WaveformCountStart(HRTIM_HandleTypeDef * hhrtim, * @retval HAL status * @note The counter of a timer is stopped only if all timer outputs are disabled */ -HAL_StatusTypeDef HAL_HRTIM_WaveformCountStop(HRTIM_HandleTypeDef * hhrtim, - uint32_t Timers) +HAL_StatusTypeDef HAL_HRTIM_WaveformCountStop(HRTIM_HandleTypeDef *hhrtim, + uint32_t Timers) { /* Check the parameters */ assert_param(IS_HRTIM_TIMERID(Timers)); @@ -5342,8 +5352,8 @@ HAL_StatusTypeDef HAL_HRTIM_WaveformCountStop(HRTIM_HandleTypeDef * hhrtim, * function. * @retval HAL status */ -HAL_StatusTypeDef HAL_HRTIM_WaveformCountStart_IT(HRTIM_HandleTypeDef * hhrtim, - uint32_t Timers) +HAL_StatusTypeDef HAL_HRTIM_WaveformCountStart_IT(HRTIM_HandleTypeDef *hhrtim, + uint32_t Timers) { uint8_t timer_idx; @@ -5356,7 +5366,7 @@ HAL_StatusTypeDef HAL_HRTIM_WaveformCountStart_IT(HRTIM_HandleTypeDef * hhrtim, hhrtim->State = HAL_HRTIM_STATE_BUSY; /* Enable HRTIM interrupts (if required) */ - __HAL_HRTIM_ENABLE_IT(hhrtim, hhrtim->Init.HRTIMInterruptResquests); + __HAL_HRTIM_ENABLE_IT(hhrtim, hhrtim->Init.HRTIMInterruptRequests); /* Enable master timer related interrupts (if required) */ if ((Timers & HRTIM_TIMERID_MASTER) != 0U) @@ -5386,7 +5396,8 @@ HAL_StatusTypeDef HAL_HRTIM_WaveformCountStart_IT(HRTIM_HandleTypeDef * hhrtim, /* Process Unlocked */ __HAL_UNLOCK(hhrtim); - return HAL_OK;} + return HAL_OK; +} /** * @brief Stop the counter of the designated timer(s) operating in waveform mode @@ -5404,8 +5415,8 @@ HAL_StatusTypeDef HAL_HRTIM_WaveformCountStart_IT(HRTIM_HandleTypeDef * hhrtim, * @note The counter of a timer is stopped only if all timer outputs are disabled * @note All enabled timer related interrupts are disabled. */ -HAL_StatusTypeDef HAL_HRTIM_WaveformCountStop_IT(HRTIM_HandleTypeDef * hhrtim, - uint32_t Timers) +HAL_StatusTypeDef HAL_HRTIM_WaveformCountStop_IT(HRTIM_HandleTypeDef *hhrtim, + uint32_t Timers) { /* ++ WA */ __IO uint32_t delai = (uint32_t)(0x17FU); @@ -5422,7 +5433,7 @@ HAL_StatusTypeDef HAL_HRTIM_WaveformCountStop_IT(HRTIM_HandleTypeDef * hhrtim, hhrtim->State = HAL_HRTIM_STATE_BUSY; /* Disable HRTIM interrupts (if required) */ - __HAL_HRTIM_DISABLE_IT(hhrtim, hhrtim->Init.HRTIMInterruptResquests); + __HAL_HRTIM_DISABLE_IT(hhrtim, hhrtim->Init.HRTIMInterruptRequests); /* Disable master timer related interrupts (if required) */ if ((Timers & HRTIM_TIMERID_MASTER) != 0U) @@ -5476,18 +5487,18 @@ HAL_StatusTypeDef HAL_HRTIM_WaveformCountStop_IT(HRTIM_HandleTypeDef * hhrtim, * size of each DMA transfer are specified at timer configuration time * (see HAL_HRTIM_WaveformTimerConfig) */ -HAL_StatusTypeDef HAL_HRTIM_WaveformCountStart_DMA(HRTIM_HandleTypeDef * hhrtim, - uint32_t Timers) +HAL_StatusTypeDef HAL_HRTIM_WaveformCountStart_DMA(HRTIM_HandleTypeDef *hhrtim, + uint32_t Timers) { uint8_t timer_idx; - DMA_HandleTypeDef * hdma; + DMA_HandleTypeDef *hdma; /* Check the parameters */ assert_param(IS_HRTIM_TIMERID(Timers)); - if(hhrtim->State == HAL_HRTIM_STATE_BUSY) + if (hhrtim->State == HAL_HRTIM_STATE_BUSY) { - return HAL_BUSY; + return HAL_BUSY; } hhrtim->State = HAL_HRTIM_STATE_BUSY; @@ -5498,29 +5509,29 @@ HAL_StatusTypeDef HAL_HRTIM_WaveformCountStart_DMA(HRTIM_HandleTypeDef * hhrtim, if (((Timers & HRTIM_TIMERID_MASTER) != (uint32_t)RESET) && (hhrtim->TimerParam[HRTIM_TIMERINDEX_MASTER].DMARequests != 0U)) { - /* Set the DMA error callback */ - hhrtim->hdmaMaster->XferErrorCallback = HRTIM_DMAError ; + /* Set the DMA error callback */ + hhrtim->hdmaMaster->XferErrorCallback = HRTIM_DMAError ; - /* Set the DMA transfer completed callback */ - hhrtim->hdmaMaster->XferCpltCallback = HRTIM_DMAMasterCplt; + /* Set the DMA transfer completed callback */ + hhrtim->hdmaMaster->XferCpltCallback = HRTIM_DMAMasterCplt; - /* Enable the DMA channel */ - if (HAL_DMA_Start_IT(hhrtim->hdmaMaster, - hhrtim->TimerParam[HRTIM_TIMERINDEX_MASTER].DMASrcAddress, - hhrtim->TimerParam[HRTIM_TIMERINDEX_MASTER].DMADstAddress, - hhrtim->TimerParam[HRTIM_TIMERINDEX_MASTER].DMASize) != HAL_OK) + /* Enable the DMA channel */ + if (HAL_DMA_Start_IT(hhrtim->hdmaMaster, + hhrtim->TimerParam[HRTIM_TIMERINDEX_MASTER].DMASrcAddress, + hhrtim->TimerParam[HRTIM_TIMERINDEX_MASTER].DMADstAddress, + hhrtim->TimerParam[HRTIM_TIMERINDEX_MASTER].DMASize) != HAL_OK) { - hhrtim->State = HAL_HRTIM_STATE_ERROR; + hhrtim->State = HAL_HRTIM_STATE_ERROR; - /* Process Unlocked */ - __HAL_UNLOCK(hhrtim); + /* Process Unlocked */ + __HAL_UNLOCK(hhrtim); - return HAL_ERROR; - } + return HAL_ERROR; + } - /* Enable the timer DMA request */ - __HAL_HRTIM_MASTER_ENABLE_DMA(hhrtim, - hhrtim->TimerParam[HRTIM_TIMERINDEX_MASTER].DMARequests); + /* Enable the timer DMA request */ + __HAL_HRTIM_MASTER_ENABLE_DMA(hhrtim, + hhrtim->TimerParam[HRTIM_TIMERINDEX_MASTER].DMARequests); } for (timer_idx = HRTIM_TIMERINDEX_TIMER_A ; @@ -5528,7 +5539,7 @@ HAL_StatusTypeDef HAL_HRTIM_WaveformCountStart_DMA(HRTIM_HandleTypeDef * hhrtim, timer_idx++) { if (((Timers & TimerIdxToTimerId[timer_idx]) != (uint32_t)RESET) && - (hhrtim->TimerParam[timer_idx].DMARequests != 0U)) + (hhrtim->TimerParam[timer_idx].DMARequests != 0U)) { /* Get the timer DMA handler */ hdma = HRTIM_GetDMAHandleFromTimerIdx(hhrtim, timer_idx); @@ -5543,7 +5554,7 @@ HAL_StatusTypeDef HAL_HRTIM_WaveformCountStart_DMA(HRTIM_HandleTypeDef * hhrtim, return HAL_ERROR; } - /* Set the DMA error callback */ + /* Set the DMA error callback */ hdma->XferErrorCallback = HRTIM_DMAError ; /* Set the DMA transfer completed callback */ @@ -5551,17 +5562,17 @@ HAL_StatusTypeDef HAL_HRTIM_WaveformCountStart_DMA(HRTIM_HandleTypeDef * hhrtim, /* Enable the DMA channel */ if (HAL_DMA_Start_IT(hdma, - hhrtim->TimerParam[timer_idx].DMASrcAddress, - hhrtim->TimerParam[timer_idx].DMADstAddress, - hhrtim->TimerParam[timer_idx].DMASize) != HAL_OK) - { - hhrtim->State = HAL_HRTIM_STATE_ERROR; + hhrtim->TimerParam[timer_idx].DMASrcAddress, + hhrtim->TimerParam[timer_idx].DMADstAddress, + hhrtim->TimerParam[timer_idx].DMASize) != HAL_OK) + { + hhrtim->State = HAL_HRTIM_STATE_ERROR; - /* Process Unlocked */ - __HAL_UNLOCK(hhrtim); + /* Process Unlocked */ + __HAL_UNLOCK(hhrtim); - return HAL_ERROR; - } + return HAL_ERROR; + } /* Enable the timer DMA request */ __HAL_HRTIM_TIMER_ENABLE_DMA(hhrtim, @@ -5597,8 +5608,8 @@ HAL_StatusTypeDef HAL_HRTIM_WaveformCountStart_DMA(HRTIM_HandleTypeDef * hhrtim, * @note The counter of a timer is stopped only if all timer outputs are disabled * @note All enabled timer related DMA requests are disabled. */ -HAL_StatusTypeDef HAL_HRTIM_WaveformCountStop_DMA(HRTIM_HandleTypeDef * hhrtim, - uint32_t Timers) +HAL_StatusTypeDef HAL_HRTIM_WaveformCountStop_DMA(HRTIM_HandleTypeDef *hhrtim, + uint32_t Timers) { uint8_t timer_idx; @@ -5613,14 +5624,14 @@ HAL_StatusTypeDef HAL_HRTIM_WaveformCountStop_DMA(HRTIM_HandleTypeDef * hhrtim, /* Disable the DMA */ if (HAL_DMA_Abort(hhrtim->hdmaMaster) != HAL_OK) { - hhrtim->State = HAL_HRTIM_STATE_ERROR; + hhrtim->State = HAL_HRTIM_STATE_ERROR; } else { - hhrtim->State = HAL_HRTIM_STATE_READY; - /* Disable the DMA request(s) */ - __HAL_HRTIM_MASTER_DISABLE_DMA(hhrtim, - hhrtim->TimerParam[HRTIM_TIMERINDEX_MASTER].DMARequests); + hhrtim->State = HAL_HRTIM_STATE_READY; + /* Disable the DMA request(s) */ + __HAL_HRTIM_MASTER_DISABLE_DMA(hhrtim, + hhrtim->TimerParam[HRTIM_TIMERINDEX_MASTER].DMARequests); } } @@ -5654,11 +5665,11 @@ HAL_StatusTypeDef HAL_HRTIM_WaveformCountStop_DMA(HRTIM_HandleTypeDef * hhrtim, if (hhrtim->State == HAL_HRTIM_STATE_ERROR) { - return HAL_ERROR; + return HAL_ERROR; } else { - return HAL_OK; + return HAL_OK; } } @@ -5672,15 +5683,15 @@ HAL_StatusTypeDef HAL_HRTIM_WaveformCountStop_DMA(HRTIM_HandleTypeDef * hhrtim, * @retval HAL status * @note This function must be called after starting the timer(s) */ -HAL_StatusTypeDef HAL_HRTIM_BurstModeCtl(HRTIM_HandleTypeDef * hhrtim, +HAL_StatusTypeDef HAL_HRTIM_BurstModeCtl(HRTIM_HandleTypeDef *hhrtim, uint32_t Enable) { /* Check parameters */ assert_param(IS_HRTIM_BURSTMODECTL(Enable)); - if(hhrtim->State == HAL_HRTIM_STATE_BUSY) + if (hhrtim->State == HAL_HRTIM_STATE_BUSY) { - return HAL_BUSY; + return HAL_BUSY; } /* Process Locked */ @@ -5706,9 +5717,9 @@ HAL_StatusTypeDef HAL_HRTIM_BurstModeCtl(HRTIM_HandleTypeDef * hhrtim, */ HAL_StatusTypeDef HAL_HRTIM_BurstModeSoftwareTrigger(HRTIM_HandleTypeDef *hhrtim) { - if(hhrtim->State == HAL_HRTIM_STATE_BUSY) + if (hhrtim->State == HAL_HRTIM_STATE_BUSY) { - return HAL_BUSY; + return HAL_BUSY; } /* Process Locked */ @@ -5745,7 +5756,7 @@ HAL_StatusTypeDef HAL_HRTIM_BurstModeSoftwareTrigger(HRTIM_HandleTypeDef *hhrtim * @note The 'software capture' bit in the capure configuration register is * automatically reset by hardware */ -HAL_StatusTypeDef HAL_HRTIM_SoftwareCapture(HRTIM_HandleTypeDef * hhrtim, +HAL_StatusTypeDef HAL_HRTIM_SoftwareCapture(HRTIM_HandleTypeDef *hhrtim, uint32_t TimerIdx, uint32_t CaptureUnit) { @@ -5753,9 +5764,9 @@ HAL_StatusTypeDef HAL_HRTIM_SoftwareCapture(HRTIM_HandleTypeDef * hhrtim, assert_param(IS_HRTIM_TIMING_UNIT(TimerIdx)); assert_param(IS_HRTIM_CAPTUREUNIT(CaptureUnit)); - if(hhrtim->State == HAL_HRTIM_STATE_BUSY) + if (hhrtim->State == HAL_HRTIM_STATE_BUSY) { - return HAL_BUSY; + return HAL_BUSY; } /* Process Locked */ @@ -5766,32 +5777,32 @@ HAL_StatusTypeDef HAL_HRTIM_SoftwareCapture(HRTIM_HandleTypeDef * hhrtim, /* Force a software capture on concerned capture unit */ switch (CaptureUnit) { - case HRTIM_CAPTUREUNIT_1: + case HRTIM_CAPTUREUNIT_1: { SET_BIT(hhrtim->Instance->sTimerxRegs[TimerIdx].CPT1xCR, HRTIM_CPT1CR_SWCPT); break; } - case HRTIM_CAPTUREUNIT_2: + case HRTIM_CAPTUREUNIT_2: { SET_BIT(hhrtim->Instance->sTimerxRegs[TimerIdx].CPT2xCR, HRTIM_CPT2CR_SWCPT); break; } - default: + default: { hhrtim->State = HAL_HRTIM_STATE_ERROR; /* Process Unlocked */ __HAL_UNLOCK(hhrtim); - break; + break; } } - if(hhrtim->State == HAL_HRTIM_STATE_ERROR) + if (hhrtim->State == HAL_HRTIM_STATE_ERROR) { - return HAL_ERROR; + return HAL_ERROR; } hhrtim->State = HAL_HRTIM_STATE_READY; @@ -5817,15 +5828,15 @@ HAL_StatusTypeDef HAL_HRTIM_SoftwareCapture(HRTIM_HandleTypeDef * hhrtim, * @note The 'software update' bits in the HRTIM control register 2 register are * automatically reset by hardware */ -HAL_StatusTypeDef HAL_HRTIM_SoftwareUpdate(HRTIM_HandleTypeDef * hhrtim, +HAL_StatusTypeDef HAL_HRTIM_SoftwareUpdate(HRTIM_HandleTypeDef *hhrtim, uint32_t Timers) { /* Check parameters */ assert_param(IS_HRTIM_TIMERUPDATE(Timers)); - if(hhrtim->State == HAL_HRTIM_STATE_BUSY) + if (hhrtim->State == HAL_HRTIM_STATE_BUSY) { - return HAL_BUSY; + return HAL_BUSY; } /* Process Locked */ @@ -5859,15 +5870,15 @@ HAL_StatusTypeDef HAL_HRTIM_SoftwareUpdate(HRTIM_HandleTypeDef * hhrtim, * @note The 'software reset' bits in the HRTIM control register 2 are * automatically reset by hardware */ -HAL_StatusTypeDef HAL_HRTIM_SoftwareReset(HRTIM_HandleTypeDef * hhrtim, +HAL_StatusTypeDef HAL_HRTIM_SoftwareReset(HRTIM_HandleTypeDef *hhrtim, uint32_t Timers) { /* Check parameters */ assert_param(IS_HRTIM_TIMERRESET(Timers)); - if(hhrtim->State == HAL_HRTIM_STATE_BUSY) + if (hhrtim->State == HAL_HRTIM_STATE_BUSY) { - return HAL_BUSY; + return HAL_BUSY; } /* Process Locked */ @@ -5915,18 +5926,18 @@ HAL_StatusTypeDef HAL_HRTIM_BurstDMATransfer(HRTIM_HandleTypeDef *hhrtim, uint32_t BurstBufferAddress, uint32_t BurstBufferLength) { - DMA_HandleTypeDef * hdma; + DMA_HandleTypeDef *hdma; /* Check the parameters */ assert_param(IS_HRTIM_TIMERINDEX(TimerIdx)); - if(hhrtim->State == HAL_HRTIM_STATE_BUSY) + if (hhrtim->State == HAL_HRTIM_STATE_BUSY) { - return HAL_BUSY; + return HAL_BUSY; } - if(hhrtim->State == HAL_HRTIM_STATE_READY) + if (hhrtim->State == HAL_HRTIM_STATE_READY) { - if((BurstBufferAddress == 0U ) || (BurstBufferLength == 0U)) + if ((BurstBufferAddress == 0U) || (BurstBufferLength == 0U)) { return HAL_ERROR; } @@ -5960,17 +5971,17 @@ HAL_StatusTypeDef HAL_HRTIM_BurstDMATransfer(HRTIM_HandleTypeDef *hhrtim, /* Enable the DMA channel */ if (HAL_DMA_Start_IT(hdma, - BurstBufferAddress, - (uint32_t)&(hhrtim->Instance->sCommonRegs.BDMADR), - BurstBufferLength) != HAL_OK) - { - hhrtim->State = HAL_HRTIM_STATE_ERROR; + BurstBufferAddress, + (uint32_t) &(hhrtim->Instance->sCommonRegs.BDMADR), + BurstBufferLength) != HAL_OK) + { + hhrtim->State = HAL_HRTIM_STATE_ERROR; - /* Process Unlocked */ - __HAL_UNLOCK(hhrtim); + /* Process Unlocked */ + __HAL_UNLOCK(hhrtim); - return HAL_ERROR; - } + return HAL_ERROR; + } hhrtim->State = HAL_HRTIM_STATE_READY; @@ -5995,9 +6006,9 @@ HAL_StatusTypeDef HAL_HRTIM_BurstDMATransfer(HRTIM_HandleTypeDef *hhrtim, * @retval HAL status */ HAL_StatusTypeDef HAL_HRTIM_UpdateEnable(HRTIM_HandleTypeDef *hhrtim, - uint32_t Timers) + uint32_t Timers) { - /* Check the parameters */ + /* Check the parameters */ assert_param(IS_HRTIM_TIMERUPDATE(Timers)); /* Process Locked */ @@ -6014,7 +6025,7 @@ HAL_StatusTypeDef HAL_HRTIM_UpdateEnable(HRTIM_HandleTypeDef *hhrtim, __HAL_UNLOCK(hhrtim); return HAL_OK; - } +} /** * @brief Disable the transfer from preload to active registers for one @@ -6050,14 +6061,14 @@ HAL_StatusTypeDef HAL_HRTIM_UpdateDisable(HRTIM_HandleTypeDef *hhrtim, __HAL_UNLOCK(hhrtim); return HAL_OK; - } +} /** * @} */ /** @defgroup HRTIM_Exported_Functions_Group9 Peripheral state functions - * @brief Peripheral State functions + * @brief Peripheral State functions @verbatim =============================================================================== ##### Peripheral State functions ##### @@ -6082,7 +6093,7 @@ HAL_StatusTypeDef HAL_HRTIM_UpdateDisable(HRTIM_HandleTypeDef *hhrtim, * @param hhrtim pointer to HAL HRTIM handle * @retval HAL state */ -HAL_HRTIM_StateTypeDef HAL_HRTIM_GetState(const HRTIM_HandleTypeDef* hhrtim) +HAL_HRTIM_StateTypeDef HAL_HRTIM_GetState(const HRTIM_HandleTypeDef *hhrtim) { /* Return HRTIM state */ return hhrtim->State; @@ -6104,7 +6115,7 @@ HAL_HRTIM_StateTypeDef HAL_HRTIM_GetState(const HRTIM_HandleTypeDef* hhrtim) * @arg HRTIM_CAPTUREUNIT_2: Capture unit 2 * @retval Captured value */ -uint32_t HAL_HRTIM_GetCapturedValue(const HRTIM_HandleTypeDef * hhrtim, +uint32_t HAL_HRTIM_GetCapturedValue(const HRTIM_HandleTypeDef *hhrtim, uint32_t TimerIdx, uint32_t CaptureUnit) { @@ -6117,21 +6128,21 @@ uint32_t HAL_HRTIM_GetCapturedValue(const HRTIM_HandleTypeDef * hhrtim, /* Read captured value */ switch (CaptureUnit) { - case HRTIM_CAPTUREUNIT_1: + case HRTIM_CAPTUREUNIT_1: { captured_value = hhrtim->Instance->sTimerxRegs[TimerIdx].CPT1xR; break; } - case HRTIM_CAPTUREUNIT_2: + case HRTIM_CAPTUREUNIT_2: { captured_value = hhrtim->Instance->sTimerxRegs[TimerIdx].CPT2xR; break; } - default: - { - captured_value = 0xFFFFFFFFUL; + default: + { + captured_value = 0xFFFFFFFFUL; break; } @@ -6167,7 +6178,7 @@ uint32_t HAL_HRTIM_GetCapturedValue(const HRTIM_HandleTypeDef * hhrtim, * @note Returned output level is taken before the output stage (chopper, * polarity). */ -uint32_t HAL_HRTIM_WaveformGetOutputLevel(const HRTIM_HandleTypeDef * hhrtim, +uint32_t HAL_HRTIM_WaveformGetOutputLevel(const HRTIM_HandleTypeDef *hhrtim, uint32_t TimerIdx, uint32_t Output) { @@ -6179,11 +6190,11 @@ uint32_t HAL_HRTIM_WaveformGetOutputLevel(const HRTIM_HandleTypeDef * hhrtim, /* Read the output level */ switch (Output) { - case HRTIM_OUTPUT_TA1: - case HRTIM_OUTPUT_TB1: - case HRTIM_OUTPUT_TC1: - case HRTIM_OUTPUT_TD1: - case HRTIM_OUTPUT_TE1: + case HRTIM_OUTPUT_TA1: + case HRTIM_OUTPUT_TB1: + case HRTIM_OUTPUT_TC1: + case HRTIM_OUTPUT_TD1: + case HRTIM_OUTPUT_TE1: { if ((hhrtim->Instance->sTimerxRegs[TimerIdx].TIMxISR & HRTIM_TIMISR_O1CPY) != (uint32_t)RESET) { @@ -6193,14 +6204,14 @@ uint32_t HAL_HRTIM_WaveformGetOutputLevel(const HRTIM_HandleTypeDef * hhrtim, { output_level = HRTIM_OUTPUTLEVEL_INACTIVE; } - break; + break; } - case HRTIM_OUTPUT_TA2: - case HRTIM_OUTPUT_TB2: - case HRTIM_OUTPUT_TC2: - case HRTIM_OUTPUT_TD2: - case HRTIM_OUTPUT_TE2: + case HRTIM_OUTPUT_TA2: + case HRTIM_OUTPUT_TB2: + case HRTIM_OUTPUT_TC2: + case HRTIM_OUTPUT_TD2: + case HRTIM_OUTPUT_TE2: { if ((hhrtim->Instance->sTimerxRegs[TimerIdx].TIMxISR & HRTIM_TIMISR_O2CPY) != (uint32_t)RESET) { @@ -6213,7 +6224,7 @@ uint32_t HAL_HRTIM_WaveformGetOutputLevel(const HRTIM_HandleTypeDef * hhrtim, break; } - default: + default: { output_level = 0xFFFFFFFFUL; break; @@ -6247,7 +6258,7 @@ uint32_t HAL_HRTIM_WaveformGetOutputLevel(const HRTIM_HandleTypeDef * hhrtim, * @arg HRTIM_OUTPUT_TE2: Timer E - Output 2 * @retval Output state */ -uint32_t HAL_HRTIM_WaveformGetOutputState(const HRTIM_HandleTypeDef * hhrtim, +uint32_t HAL_HRTIM_WaveformGetOutputState(const HRTIM_HandleTypeDef *hhrtim, uint32_t TimerIdx, uint32_t Output) { @@ -6263,67 +6274,67 @@ uint32_t HAL_HRTIM_WaveformGetOutputState(const HRTIM_HandleTypeDef * hhrtim, /* Set output state according to output control status and output disable status */ switch (Output) { - case HRTIM_OUTPUT_TA1: + case HRTIM_OUTPUT_TA1: { output_bit = HRTIM_OENR_TA1OEN; break; } - case HRTIM_OUTPUT_TA2: + case HRTIM_OUTPUT_TA2: { output_bit = HRTIM_OENR_TA2OEN; break; } - case HRTIM_OUTPUT_TB1: + case HRTIM_OUTPUT_TB1: { output_bit = HRTIM_OENR_TB1OEN; break; } - case HRTIM_OUTPUT_TB2: + case HRTIM_OUTPUT_TB2: { output_bit = HRTIM_OENR_TB2OEN; break; } - case HRTIM_OUTPUT_TC1: + case HRTIM_OUTPUT_TC1: { output_bit = HRTIM_OENR_TC1OEN; break; } - case HRTIM_OUTPUT_TC2: + case HRTIM_OUTPUT_TC2: { output_bit = HRTIM_OENR_TC2OEN; break; } - case HRTIM_OUTPUT_TD1: + case HRTIM_OUTPUT_TD1: { output_bit = HRTIM_OENR_TD1OEN; break; } - case HRTIM_OUTPUT_TD2: + case HRTIM_OUTPUT_TD2: { output_bit = HRTIM_OENR_TD2OEN; break; } - case HRTIM_OUTPUT_TE1: + case HRTIM_OUTPUT_TE1: { output_bit = HRTIM_OENR_TE1OEN; break; } - case HRTIM_OUTPUT_TE2: + case HRTIM_OUTPUT_TE2: { output_bit = HRTIM_OENR_TE2OEN; break; } - default: + default: { output_bit = 0UL; break; @@ -6349,7 +6360,7 @@ uint32_t HAL_HRTIM_WaveformGetOutputState(const HRTIM_HandleTypeDef * hhrtim, } } - return(output_state); + return (output_state); } /** @@ -6377,7 +6388,7 @@ uint32_t HAL_HRTIM_WaveformGetOutputState(const HRTIM_HandleTypeDef * hhrtim, * @arg HRTIM_OUTPUT_TE2: Timer E - Output 2 * @retval Delayed protection status */ -uint32_t HAL_HRTIM_GetDelayedProtectionStatus(const HRTIM_HandleTypeDef * hhrtim, +uint32_t HAL_HRTIM_GetDelayedProtectionStatus(const HRTIM_HandleTypeDef *hhrtim, uint32_t TimerIdx, uint32_t Output) { @@ -6389,11 +6400,11 @@ uint32_t HAL_HRTIM_GetDelayedProtectionStatus(const HRTIM_HandleTypeDef * hhrtim /* Read the delayed protection status */ switch (Output) { - case HRTIM_OUTPUT_TA1: - case HRTIM_OUTPUT_TB1: - case HRTIM_OUTPUT_TC1: - case HRTIM_OUTPUT_TD1: - case HRTIM_OUTPUT_TE1: + case HRTIM_OUTPUT_TA1: + case HRTIM_OUTPUT_TB1: + case HRTIM_OUTPUT_TC1: + case HRTIM_OUTPUT_TD1: + case HRTIM_OUTPUT_TE1: { if ((hhrtim->Instance->sTimerxRegs[TimerIdx].TIMxISR & HRTIM_TIMISR_O1STAT) != (uint32_t)RESET) { @@ -6408,11 +6419,11 @@ uint32_t HAL_HRTIM_GetDelayedProtectionStatus(const HRTIM_HandleTypeDef * hhrtim break; } - case HRTIM_OUTPUT_TA2: - case HRTIM_OUTPUT_TB2: - case HRTIM_OUTPUT_TC2: - case HRTIM_OUTPUT_TD2: - case HRTIM_OUTPUT_TE2: + case HRTIM_OUTPUT_TA2: + case HRTIM_OUTPUT_TB2: + case HRTIM_OUTPUT_TC2: + case HRTIM_OUTPUT_TD2: + case HRTIM_OUTPUT_TE2: { if ((hhrtim->Instance->sTimerxRegs[TimerIdx].TIMxISR & HRTIM_TIMISR_O2STAT) != (uint32_t)RESET) { @@ -6427,7 +6438,7 @@ uint32_t HAL_HRTIM_GetDelayedProtectionStatus(const HRTIM_HandleTypeDef * hhrtim break; } - default: + default: { delayed_protection_status = 0xFFFFFFFFUL; break; @@ -6442,7 +6453,7 @@ uint32_t HAL_HRTIM_GetDelayedProtectionStatus(const HRTIM_HandleTypeDef * hhrtim * @param hhrtim pointer to HAL HRTIM handle * @retval Burst mode controller status */ -uint32_t HAL_HRTIM_GetBurstStatus(const HRTIM_HandleTypeDef * hhrtim) +uint32_t HAL_HRTIM_GetBurstStatus(const HRTIM_HandleTypeDef *hhrtim) { uint32_t burst_mode_status; @@ -6465,7 +6476,7 @@ uint32_t HAL_HRTIM_GetBurstStatus(const HRTIM_HandleTypeDef * hhrtim) * @arg HRTIM_TIMERINDEX_TIMER_E for timer E * @retval Burst mode controller status */ -uint32_t HAL_HRTIM_GetCurrentPushPullStatus(const HRTIM_HandleTypeDef * hhrtim, +uint32_t HAL_HRTIM_GetCurrentPushPullStatus(const HRTIM_HandleTypeDef *hhrtim, uint32_t TimerIdx) { uint32_t current_pushpull_status; @@ -6493,7 +6504,7 @@ uint32_t HAL_HRTIM_GetCurrentPushPullStatus(const HRTIM_HandleTypeDef * hhrtim, * @arg HRTIM_TIMERINDEX_TIMER_E for timer E * @retval Idle Push Pull Status */ -uint32_t HAL_HRTIM_GetIdlePushPullStatus(const HRTIM_HandleTypeDef * hhrtim, +uint32_t HAL_HRTIM_GetIdlePushPullStatus(const HRTIM_HandleTypeDef *hhrtim, uint32_t TimerIdx) { uint32_t idle_pushpull_status; @@ -6512,25 +6523,25 @@ uint32_t HAL_HRTIM_GetIdlePushPullStatus(const HRTIM_HandleTypeDef * hhrtim, */ /** @defgroup HRTIM_Exported_Functions_Group10 Interrupts handling - * @brief Functions called when HRTIM generates an interrupt - * 7 interrupts can be generated by the master timer: - * - Master timer registers update - * - Synchronization event received - * - Master timer repetition event - * - Master Compare 1 to 4 event - * 14 interrupts can be generated by each timing unit: - * - Delayed protection triggered - * - Counter reset or roll-over event - * - Output 1 and output 2 reset (transition active to inactive) - * - Output 1 and output 2 set (transition inactive to active) - * - Capture 1 and 2 events - * - Timing unit registers update - * - Repetition event - * - Compare 1 to 4 event - * 8 global interrupts are generated for the whole HRTIM: - * - System fault and Fault 1 to 5 (regardless of the timing unit attribution) - * - DLL calibration done - * - Burst mode period completed + * @brief Functions called when HRTIM generates an interrupt + * 7 interrupts can be generated by the master timer: + * - Master timer registers update + * - Synchronization event received + * - Master timer repetition event + * - Master Compare 1 to 4 event + * 14 interrupts can be generated by each timing unit: + * - Delayed protection triggered + * - Counter reset or roll-over event + * - Output 1 and output 2 reset (transition active to inactive) + * - Output 1 and output 2 set (transition inactive to active) + * - Capture 1 and 2 events + * - Timing unit registers update + * - Repetition event + * - Compare 1 to 4 event + * 8 global interrupts are generated for the whole HRTIM: + * - System fault and Fault 1 to 5 (regardless of the timing unit attribution) + * - DLL calibration done + * - Burst mode period completed @verbatim =============================================================================== ##### HRTIM interrupts handling ##### @@ -6580,7 +6591,7 @@ uint32_t HAL_HRTIM_GetIdlePushPullStatus(const HRTIM_HandleTypeDef * hhrtim, * This parameter can be any value of HRTIM_Timer_Index * @retval None */ -void HAL_HRTIM_IRQHandler(HRTIM_HandleTypeDef * hhrtim, +void HAL_HRTIM_IRQHandler(HRTIM_HandleTypeDef *hhrtim, uint32_t TimerIdx) { /* HRTIM interrupts handling */ @@ -6606,7 +6617,7 @@ void HAL_HRTIM_IRQHandler(HRTIM_HandleTypeDef * hhrtim, * @param hhrtim pointer to HAL HRTIM handle * @retval None * @retval None */ -__weak void HAL_HRTIM_Fault1Callback(HRTIM_HandleTypeDef * hhrtim) +__weak void HAL_HRTIM_Fault1Callback(HRTIM_HandleTypeDef *hhrtim) { /* Prevent unused argument(s) compilation warning */ UNUSED(hhrtim); @@ -6621,7 +6632,7 @@ __weak void HAL_HRTIM_Fault1Callback(HRTIM_HandleTypeDef * hhrtim) * @param hhrtim pointer to HAL HRTIM handle * @retval None */ -__weak void HAL_HRTIM_Fault2Callback(HRTIM_HandleTypeDef * hhrtim) +__weak void HAL_HRTIM_Fault2Callback(HRTIM_HandleTypeDef *hhrtim) { /* Prevent unused argument(s) compilation warning */ UNUSED(hhrtim); @@ -6636,7 +6647,7 @@ __weak void HAL_HRTIM_Fault2Callback(HRTIM_HandleTypeDef * hhrtim) * @param hhrtim pointer to HAL HRTIM handle * @retval None */ -__weak void HAL_HRTIM_Fault3Callback(HRTIM_HandleTypeDef * hhrtim) +__weak void HAL_HRTIM_Fault3Callback(HRTIM_HandleTypeDef *hhrtim) { /* Prevent unused argument(s) compilation warning */ UNUSED(hhrtim); @@ -6651,7 +6662,7 @@ __weak void HAL_HRTIM_Fault3Callback(HRTIM_HandleTypeDef * hhrtim) * @param hhrtim pointer to HAL HRTIM handle * @retval None */ -__weak void HAL_HRTIM_Fault4Callback(HRTIM_HandleTypeDef * hhrtim) +__weak void HAL_HRTIM_Fault4Callback(HRTIM_HandleTypeDef *hhrtim) { /* Prevent unused argument(s) compilation warning */ UNUSED(hhrtim); @@ -6666,7 +6677,7 @@ __weak void HAL_HRTIM_Fault4Callback(HRTIM_HandleTypeDef * hhrtim) * @param hhrtim pointer to HAL HRTIM handle * @retval None */ -__weak void HAL_HRTIM_Fault5Callback(HRTIM_HandleTypeDef * hhrtim) +__weak void HAL_HRTIM_Fault5Callback(HRTIM_HandleTypeDef *hhrtim) { /* Prevent unused argument(s) compilation warning */ UNUSED(hhrtim); @@ -6681,7 +6692,7 @@ __weak void HAL_HRTIM_Fault5Callback(HRTIM_HandleTypeDef * hhrtim) * @param hhrtim pointer to HAL HRTIM handle * @retval None */ -__weak void HAL_HRTIM_SystemFaultCallback(HRTIM_HandleTypeDef * hhrtim) +__weak void HAL_HRTIM_SystemFaultCallback(HRTIM_HandleTypeDef *hhrtim) { /* Prevent unused argument(s) compilation warning */ UNUSED(hhrtim); @@ -6696,7 +6707,7 @@ __weak void HAL_HRTIM_SystemFaultCallback(HRTIM_HandleTypeDef * hhrtim) * @param hhrtim pointer to HAL HRTIM handle * @retval None */ -__weak void HAL_HRTIM_DLLCalibrationReadyCallback(HRTIM_HandleTypeDef * hhrtim) +__weak void HAL_HRTIM_DLLCalibrationReadyCallback(HRTIM_HandleTypeDef *hhrtim) { /* Prevent unused argument(s) compilation warning */ UNUSED(hhrtim); @@ -6711,7 +6722,7 @@ __weak void HAL_HRTIM_DLLCalibrationReadyCallback(HRTIM_HandleTypeDef * hhrtim) * @param hhrtim pointer to HAL HRTIM handle * @retval None */ -__weak void HAL_HRTIM_BurstModePeriodCallback(HRTIM_HandleTypeDef * hhrtim) +__weak void HAL_HRTIM_BurstModePeriodCallback(HRTIM_HandleTypeDef *hhrtim) { /* Prevent unused argument(s) compilation warning */ UNUSED(hhrtim); @@ -6726,7 +6737,7 @@ __weak void HAL_HRTIM_BurstModePeriodCallback(HRTIM_HandleTypeDef * hhrtim) * @param hhrtim pointer to HAL HRTIM handle * @retval None */ -__weak void HAL_HRTIM_SynchronizationEventCallback(HRTIM_HandleTypeDef * hhrtim) +__weak void HAL_HRTIM_SynchronizationEventCallback(HRTIM_HandleTypeDef *hhrtim) { /* Prevent unused argument(s) compilation warning */ UNUSED(hhrtim); @@ -6749,7 +6760,7 @@ __weak void HAL_HRTIM_SynchronizationEventCallback(HRTIM_HandleTypeDef * hhrtim) * @arg HRTIM_TIMERINDEX_TIMER_E for timer E * @retval None */ -__weak void HAL_HRTIM_RegistersUpdateCallback(HRTIM_HandleTypeDef * hhrtim, +__weak void HAL_HRTIM_RegistersUpdateCallback(HRTIM_HandleTypeDef *hhrtim, uint32_t TimerIdx) { /* Prevent unused argument(s) compilation warning */ @@ -6774,7 +6785,7 @@ __weak void HAL_HRTIM_RegistersUpdateCallback(HRTIM_HandleTypeDef * hhrtim, * @arg HRTIM_TIMERINDEX_TIMER_E for timer E * @retval None */ -__weak void HAL_HRTIM_RepetitionEventCallback(HRTIM_HandleTypeDef * hhrtim, +__weak void HAL_HRTIM_RepetitionEventCallback(HRTIM_HandleTypeDef *hhrtim, uint32_t TimerIdx) { /* Prevent unused argument(s) compilation warning */ @@ -6800,8 +6811,8 @@ __weak void HAL_HRTIM_RepetitionEventCallback(HRTIM_HandleTypeDef * hhrtim, * @arg HRTIM_TIMERINDEX_TIMER_E for timer E * @retval None */ -__weak void HAL_HRTIM_Compare1EventCallback(HRTIM_HandleTypeDef * hhrtim, - uint32_t TimerIdx) +__weak void HAL_HRTIM_Compare1EventCallback(HRTIM_HandleTypeDef *hhrtim, + uint32_t TimerIdx) { /* Prevent unused argument(s) compilation warning */ UNUSED(hhrtim); @@ -6826,8 +6837,8 @@ __weak void HAL_HRTIM_Compare1EventCallback(HRTIM_HandleTypeDef * hhrtim, * @arg HRTIM_TIMERINDEX_TIMER_D for timer D * @arg HRTIM_TIMERINDEX_TIMER_E for timer E */ -__weak void HAL_HRTIM_Compare2EventCallback(HRTIM_HandleTypeDef * hhrtim, - uint32_t TimerIdx) +__weak void HAL_HRTIM_Compare2EventCallback(HRTIM_HandleTypeDef *hhrtim, + uint32_t TimerIdx) { /* Prevent unused argument(s) compilation warning */ UNUSED(hhrtim); @@ -6852,8 +6863,8 @@ __weak void HAL_HRTIM_Compare2EventCallback(HRTIM_HandleTypeDef * hhrtim, * @arg HRTIM_TIMERINDEX_TIMER_E for timer E * @retval None */ -__weak void HAL_HRTIM_Compare3EventCallback(HRTIM_HandleTypeDef * hhrtim, - uint32_t TimerIdx) +__weak void HAL_HRTIM_Compare3EventCallback(HRTIM_HandleTypeDef *hhrtim, + uint32_t TimerIdx) { /* Prevent unused argument(s) compilation warning */ UNUSED(hhrtim); @@ -6878,8 +6889,8 @@ __weak void HAL_HRTIM_Compare3EventCallback(HRTIM_HandleTypeDef * hhrtim, * @arg HRTIM_TIMERINDEX_TIMER_E for timer E * @retval None */ -__weak void HAL_HRTIM_Compare4EventCallback(HRTIM_HandleTypeDef * hhrtim, - uint32_t TimerIdx) +__weak void HAL_HRTIM_Compare4EventCallback(HRTIM_HandleTypeDef *hhrtim, + uint32_t TimerIdx) { /* Prevent unused argument(s) compilation warning */ UNUSED(hhrtim); @@ -6902,8 +6913,8 @@ __weak void HAL_HRTIM_Compare4EventCallback(HRTIM_HandleTypeDef * hhrtim, * @arg HRTIM_TIMERINDEX_TIMER_E for timer E * @retval None */ -__weak void HAL_HRTIM_Capture1EventCallback(HRTIM_HandleTypeDef * hhrtim, - uint32_t TimerIdx) +__weak void HAL_HRTIM_Capture1EventCallback(HRTIM_HandleTypeDef *hhrtim, + uint32_t TimerIdx) { /* Prevent unused argument(s) compilation warning */ UNUSED(hhrtim); @@ -6926,8 +6937,8 @@ __weak void HAL_HRTIM_Capture1EventCallback(HRTIM_HandleTypeDef * hhrtim, * @arg HRTIM_TIMERINDEX_TIMER_E for timer E * @retval None */ -__weak void HAL_HRTIM_Capture2EventCallback(HRTIM_HandleTypeDef * hhrtim, - uint32_t TimerIdx) +__weak void HAL_HRTIM_Capture2EventCallback(HRTIM_HandleTypeDef *hhrtim, + uint32_t TimerIdx) { /* Prevent unused argument(s) compilation warning */ UNUSED(hhrtim); @@ -6951,8 +6962,8 @@ __weak void HAL_HRTIM_Capture2EventCallback(HRTIM_HandleTypeDef * hhrtim, * @arg HRTIM_TIMERINDEX_TIMER_E for timer E * @retval None */ -__weak void HAL_HRTIM_DelayedProtectionCallback(HRTIM_HandleTypeDef * hhrtim, - uint32_t TimerIdx) +__weak void HAL_HRTIM_DelayedProtectionCallback(HRTIM_HandleTypeDef *hhrtim, + uint32_t TimerIdx) { /* Prevent unused argument(s) compilation warning */ UNUSED(hhrtim); @@ -6976,8 +6987,8 @@ __weak void HAL_HRTIM_DelayedProtectionCallback(HRTIM_HandleTypeDef * hhrtim, * @arg HRTIM_TIMERINDEX_TIMER_E for timer E * @retval None */ -__weak void HAL_HRTIM_CounterResetCallback(HRTIM_HandleTypeDef * hhrtim, - uint32_t TimerIdx) +__weak void HAL_HRTIM_CounterResetCallback(HRTIM_HandleTypeDef *hhrtim, + uint32_t TimerIdx) { /* Prevent unused argument(s) compilation warning */ UNUSED(hhrtim); @@ -7000,8 +7011,8 @@ __weak void HAL_HRTIM_CounterResetCallback(HRTIM_HandleTypeDef * hhrtim, * @arg HRTIM_TIMERINDEX_TIMER_E for timer E * @retval None */ -__weak void HAL_HRTIM_Output1SetCallback(HRTIM_HandleTypeDef * hhrtim, - uint32_t TimerIdx) +__weak void HAL_HRTIM_Output1SetCallback(HRTIM_HandleTypeDef *hhrtim, + uint32_t TimerIdx) { /* Prevent unused argument(s) compilation warning */ UNUSED(hhrtim); @@ -7024,8 +7035,8 @@ __weak void HAL_HRTIM_Output1SetCallback(HRTIM_HandleTypeDef * hhrtim, * @arg HRTIM_TIMERINDEX_TIMER_E for timer E * @retval None */ -__weak void HAL_HRTIM_Output1ResetCallback(HRTIM_HandleTypeDef * hhrtim, - uint32_t TimerIdx) +__weak void HAL_HRTIM_Output1ResetCallback(HRTIM_HandleTypeDef *hhrtim, + uint32_t TimerIdx) { /* Prevent unused argument(s) compilation warning */ UNUSED(hhrtim); @@ -7048,8 +7059,8 @@ __weak void HAL_HRTIM_Output1ResetCallback(HRTIM_HandleTypeDef * hhrtim, * @arg HRTIM_TIMERINDEX_TIMER_E for timer E * @retval None */ -__weak void HAL_HRTIM_Output2SetCallback(HRTIM_HandleTypeDef * hhrtim, - uint32_t TimerIdx) +__weak void HAL_HRTIM_Output2SetCallback(HRTIM_HandleTypeDef *hhrtim, + uint32_t TimerIdx) { /* Prevent unused argument(s) compilation warning */ UNUSED(hhrtim); @@ -7072,8 +7083,8 @@ __weak void HAL_HRTIM_Output2SetCallback(HRTIM_HandleTypeDef * hhrtim, * @arg HRTIM_TIMERINDEX_TIMER_E for timer E * @retval None */ -__weak void HAL_HRTIM_Output2ResetCallback(HRTIM_HandleTypeDef * hhrtim, - uint32_t TimerIdx) +__weak void HAL_HRTIM_Output2ResetCallback(HRTIM_HandleTypeDef *hhrtim, + uint32_t TimerIdx) { /* Prevent unused argument(s) compilation warning */ UNUSED(hhrtim); @@ -7097,7 +7108,7 @@ __weak void HAL_HRTIM_Output2ResetCallback(HRTIM_HandleTypeDef * hhrtim, * @arg HRTIM_TIMERINDEX_TIMER_E for timer E * @retval None */ -__weak void HAL_HRTIM_BurstDMATransferCallback(HRTIM_HandleTypeDef * hhrtim, +__weak void HAL_HRTIM_BurstDMATransferCallback(HRTIM_HandleTypeDef *hhrtim, uint32_t TimerIdx) { /* Prevent unused argument(s) compilation warning */ @@ -7145,7 +7156,7 @@ __weak void HAL_HRTIM_ErrorCallback(HRTIM_HandleTypeDef *hhrtim) * @param pCallback Callback function pointer * @retval HAL status */ -HAL_StatusTypeDef HAL_HRTIM_RegisterCallback(HRTIM_HandleTypeDef * hhrtim, +HAL_StatusTypeDef HAL_HRTIM_RegisterCallback(HRTIM_HandleTypeDef *hhrtim, HAL_HRTIM_CallbackIDTypeDef CallbackID, pHRTIM_CallbackTypeDef pCallback) { @@ -7278,7 +7289,7 @@ HAL_StatusTypeDef HAL_HRTIM_RegisterCallback(HRTIM_HandleTypeDef * hhrtim, * @arg HAL_HRTIM_MSPDEINIT_CB_ID * @retval HAL status */ -HAL_StatusTypeDef HAL_HRTIM_UnRegisterCallback(HRTIM_HandleTypeDef * hhrtim, +HAL_StatusTypeDef HAL_HRTIM_UnRegisterCallback(HRTIM_HandleTypeDef *hhrtim, HAL_HRTIM_CallbackIDTypeDef CallbackID) { HAL_StatusTypeDef status = HAL_OK; @@ -7290,82 +7301,82 @@ HAL_StatusTypeDef HAL_HRTIM_UnRegisterCallback(HRTIM_HandleTypeDef * hhrtim, { switch (CallbackID) { - case HAL_HRTIM_FAULT1CALLBACK_CB_ID : - hhrtim->Fault1Callback = HAL_HRTIM_Fault1Callback; - break; + case HAL_HRTIM_FAULT1CALLBACK_CB_ID : + hhrtim->Fault1Callback = HAL_HRTIM_Fault1Callback; + break; - case HAL_HRTIM_FAULT2CALLBACK_CB_ID : - hhrtim->Fault2Callback = HAL_HRTIM_Fault2Callback; - break; + case HAL_HRTIM_FAULT2CALLBACK_CB_ID : + hhrtim->Fault2Callback = HAL_HRTIM_Fault2Callback; + break; - case HAL_HRTIM_FAULT3CALLBACK_CB_ID : - hhrtim->Fault3Callback = HAL_HRTIM_Fault3Callback; - break; + case HAL_HRTIM_FAULT3CALLBACK_CB_ID : + hhrtim->Fault3Callback = HAL_HRTIM_Fault3Callback; + break; - case HAL_HRTIM_FAULT4CALLBACK_CB_ID : - hhrtim->Fault4Callback = HAL_HRTIM_Fault4Callback; - break; + case HAL_HRTIM_FAULT4CALLBACK_CB_ID : + hhrtim->Fault4Callback = HAL_HRTIM_Fault4Callback; + break; - case HAL_HRTIM_FAULT5CALLBACK_CB_ID : - hhrtim->Fault5Callback = HAL_HRTIM_Fault5Callback; - break; + case HAL_HRTIM_FAULT5CALLBACK_CB_ID : + hhrtim->Fault5Callback = HAL_HRTIM_Fault5Callback; + break; - case HAL_HRTIM_SYSTEMFAULTCALLBACK_CB_ID : - hhrtim->SystemFaultCallback = HAL_HRTIM_SystemFaultCallback; - break; + case HAL_HRTIM_SYSTEMFAULTCALLBACK_CB_ID : + hhrtim->SystemFaultCallback = HAL_HRTIM_SystemFaultCallback; + break; - case HAL_HRTIM_DLLCALBRATIONREADYCALLBACK_CB_ID : - hhrtim->DLLCalibrationReadyCallback = HAL_HRTIM_DLLCalibrationReadyCallback; - break; + case HAL_HRTIM_DLLCALBRATIONREADYCALLBACK_CB_ID : + hhrtim->DLLCalibrationReadyCallback = HAL_HRTIM_DLLCalibrationReadyCallback; + break; - case HAL_HRTIM_BURSTMODEPERIODCALLBACK_CB_ID : - hhrtim->BurstModePeriodCallback = HAL_HRTIM_BurstModePeriodCallback; - break; + case HAL_HRTIM_BURSTMODEPERIODCALLBACK_CB_ID : + hhrtim->BurstModePeriodCallback = HAL_HRTIM_BurstModePeriodCallback; + break; - case HAL_HRTIM_SYNCHRONIZATIONEVENTCALLBACK_CB_ID : - hhrtim->SynchronizationEventCallback = HAL_HRTIM_SynchronizationEventCallback; - break; + case HAL_HRTIM_SYNCHRONIZATIONEVENTCALLBACK_CB_ID : + hhrtim->SynchronizationEventCallback = HAL_HRTIM_SynchronizationEventCallback; + break; - case HAL_HRTIM_ERRORCALLBACK_CB_ID : - hhrtim->ErrorCallback = HAL_HRTIM_ErrorCallback; - break; + case HAL_HRTIM_ERRORCALLBACK_CB_ID : + hhrtim->ErrorCallback = HAL_HRTIM_ErrorCallback; + break; - case HAL_HRTIM_MSPINIT_CB_ID : - hhrtim->MspInitCallback = HAL_HRTIM_MspInit; - break; + case HAL_HRTIM_MSPINIT_CB_ID : + hhrtim->MspInitCallback = HAL_HRTIM_MspInit; + break; - case HAL_HRTIM_MSPDEINIT_CB_ID : - hhrtim->MspDeInitCallback = HAL_HRTIM_MspDeInit; - break; + case HAL_HRTIM_MSPDEINIT_CB_ID : + hhrtim->MspDeInitCallback = HAL_HRTIM_MspDeInit; + break; - default : - /* Update the state */ - hhrtim->State = HAL_HRTIM_STATE_INVALID_CALLBACK; + default : + /* Update the state */ + hhrtim->State = HAL_HRTIM_STATE_INVALID_CALLBACK; - /* Return error status */ - status = HAL_ERROR; - break; + /* Return error status */ + status = HAL_ERROR; + break; } } else if (HAL_HRTIM_STATE_RESET == hhrtim->State) { switch (CallbackID) { - case HAL_HRTIM_MSPINIT_CB_ID : - hhrtim->MspInitCallback = HAL_HRTIM_MspInit; - break; + case HAL_HRTIM_MSPINIT_CB_ID : + hhrtim->MspInitCallback = HAL_HRTIM_MspInit; + break; - case HAL_HRTIM_MSPDEINIT_CB_ID : - hhrtim->MspDeInitCallback = HAL_HRTIM_MspDeInit; - break; + case HAL_HRTIM_MSPDEINIT_CB_ID : + hhrtim->MspDeInitCallback = HAL_HRTIM_MspDeInit; + break; - default : - /* Update the state */ - hhrtim->State = HAL_HRTIM_STATE_INVALID_CALLBACK; + default : + /* Update the state */ + hhrtim->State = HAL_HRTIM_STATE_INVALID_CALLBACK; - /* Return error status */ - status = HAL_ERROR; - break; + /* Return error status */ + status = HAL_ERROR; + break; } } else @@ -7406,7 +7417,7 @@ HAL_StatusTypeDef HAL_HRTIM_UnRegisterCallback(HRTIM_HandleTypeDef * hhrtim, * @param pCallback Callback function pointer * @retval HAL status */ -HAL_StatusTypeDef HAL_HRTIM_TIMxRegisterCallback(HRTIM_HandleTypeDef * hhrtim, +HAL_StatusTypeDef HAL_HRTIM_TIMxRegisterCallback(HRTIM_HandleTypeDef *hhrtim, HAL_HRTIM_CallbackIDTypeDef CallbackID, pHRTIM_TIMxCallbackTypeDef pCallback) { @@ -7487,7 +7498,7 @@ HAL_StatusTypeDef HAL_HRTIM_TIMxRegisterCallback(HRTIM_HandleTypeDef * hhrtim, hhrtim->BurstDMATransferCallback = pCallback; break; - default : + default : /* Update the state */ hhrtim->State = HAL_HRTIM_STATE_INVALID_CALLBACK; @@ -7533,7 +7544,7 @@ HAL_StatusTypeDef HAL_HRTIM_TIMxRegisterCallback(HRTIM_HandleTypeDef * hhrtim, * @arg HAL_HRTIM_BURSTDMATRANSFERCALLBACK_CB_ID * @retval HAL status */ -HAL_StatusTypeDef HAL_HRTIM_TIMxUnRegisterCallback(HRTIM_HandleTypeDef * hhrtim, +HAL_StatusTypeDef HAL_HRTIM_TIMxUnRegisterCallback(HRTIM_HandleTypeDef *hhrtim, HAL_HRTIM_CallbackIDTypeDef CallbackID) { HAL_StatusTypeDef status = HAL_OK; @@ -7605,7 +7616,7 @@ HAL_StatusTypeDef HAL_HRTIM_TIMxUnRegisterCallback(HRTIM_HandleTypeDef * hhrtim, hhrtim->BurstDMATransferCallback = HAL_HRTIM_BurstDMATransferCallback; break; - default : + default : /* Update the state */ hhrtim->State = HAL_HRTIM_STATE_INVALID_CALLBACK; @@ -7647,8 +7658,8 @@ HAL_StatusTypeDef HAL_HRTIM_TIMxUnRegisterCallback(HRTIM_HandleTypeDef * hhrtim, * @param pTimeBaseCfg pointer to the time base configuration structure * @retval None */ -static void HRTIM_MasterBase_Config(HRTIM_HandleTypeDef * hhrtim, - const HRTIM_TimeBaseCfgTypeDef * pTimeBaseCfg) +static void HRTIM_MasterBase_Config(HRTIM_HandleTypeDef *hhrtim, + const HRTIM_TimeBaseCfgTypeDef *pTimeBaseCfg) { uint32_t hrtim_mcr; @@ -7676,9 +7687,9 @@ static void HRTIM_MasterBase_Config(HRTIM_HandleTypeDef * hhrtim, * @param pTimeBaseCfg pointer to the time base configuration structure * @retval None */ -static void HRTIM_TimingUnitBase_Config(HRTIM_HandleTypeDef * hhrtim, - uint32_t TimerIdx , - const HRTIM_TimeBaseCfgTypeDef * pTimeBaseCfg) +static void HRTIM_TimingUnitBase_Config(HRTIM_HandleTypeDef *hhrtim, + uint32_t TimerIdx, + const HRTIM_TimeBaseCfgTypeDef *pTimeBaseCfg) { uint32_t hrtim_timcr; @@ -7705,8 +7716,8 @@ static void HRTIM_TimingUnitBase_Config(HRTIM_HandleTypeDef * hhrtim, * @param pTimerCfg pointer to the timer configuration data structure * @retval None */ -static void HRTIM_MasterWaveform_Config(HRTIM_HandleTypeDef * hhrtim, - const HRTIM_TimerCfgTypeDef * pTimerCfg) +static void HRTIM_MasterWaveform_Config(HRTIM_HandleTypeDef *hhrtim, + const HRTIM_TimerCfgTypeDef *pTimerCfg) { uint32_t hrtim_mcr; uint32_t hrtim_bmcr; @@ -7759,9 +7770,9 @@ static void HRTIM_MasterWaveform_Config(HRTIM_HandleTypeDef * hhrtim, * @param pTimerCfg pointer to the timer configuration data structure * @retval None */ -static void HRTIM_TimingUnitWaveform_Config(HRTIM_HandleTypeDef * hhrtim, +static void HRTIM_TimingUnitWaveform_Config(HRTIM_HandleTypeDef *hhrtim, uint32_t TimerIdx, - const HRTIM_TimerCfgTypeDef * pTimerCfg) + const HRTIM_TimerCfgTypeDef *pTimerCfg) { uint32_t hrtim_timcr; uint32_t hrtim_timfltr; @@ -7841,11 +7852,11 @@ static void HRTIM_TimingUnitWaveform_Config(HRTIM_HandleTypeDef * hhrtim, Delayed Idle is available whatever the timer operating mode (regular, push-pull) Balanced Idle is only available in push-pull mode */ - if ( ((pTimerCfg->DelayedProtectionMode != HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_BALANCED_EEV6) + if (((pTimerCfg->DelayedProtectionMode != HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_BALANCED_EEV6) && (pTimerCfg->DelayedProtectionMode != HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_BALANCED_EEV7)) - || (pTimerCfg->PushPull == HRTIM_TIMPUSHPULLMODE_ENABLED)) + || (pTimerCfg->PushPull == HRTIM_TIMPUSHPULLMODE_ENABLED)) { - hrtim_timoutr &= ~(HRTIM_OUTR_DLYPRT| HRTIM_OUTR_DLYPRTEN); + hrtim_timoutr &= ~(HRTIM_OUTR_DLYPRT | HRTIM_OUTR_DLYPRTEN); hrtim_timoutr |= pTimerCfg->DelayedProtectionMode; } @@ -7855,43 +7866,43 @@ static void HRTIM_TimingUnitWaveform_Config(HRTIM_HandleTypeDef * hhrtim, /* Set the timer burst mode */ switch (TimerIdx) { - case HRTIM_TIMERINDEX_TIMER_A: + case HRTIM_TIMERINDEX_TIMER_A: { hrtim_bmcr &= ~(HRTIM_BMCR_TABM); - hrtim_bmcr |= ( pTimerCfg->BurstMode << 1U); + hrtim_bmcr |= (pTimerCfg->BurstMode << 1U); break; } - case HRTIM_TIMERINDEX_TIMER_B: + case HRTIM_TIMERINDEX_TIMER_B: { hrtim_bmcr &= ~(HRTIM_BMCR_TBBM); - hrtim_bmcr |= ( pTimerCfg->BurstMode << 2U); + hrtim_bmcr |= (pTimerCfg->BurstMode << 2U); break; } - case HRTIM_TIMERINDEX_TIMER_C: + case HRTIM_TIMERINDEX_TIMER_C: { hrtim_bmcr &= ~(HRTIM_BMCR_TCBM); - hrtim_bmcr |= ( pTimerCfg->BurstMode << 3U); + hrtim_bmcr |= (pTimerCfg->BurstMode << 3U); break; } - case HRTIM_TIMERINDEX_TIMER_D: + case HRTIM_TIMERINDEX_TIMER_D: { hrtim_bmcr &= ~(HRTIM_BMCR_TDBM); - hrtim_bmcr |= ( pTimerCfg->BurstMode << 4U); + hrtim_bmcr |= (pTimerCfg->BurstMode << 4U); break; } - case HRTIM_TIMERINDEX_TIMER_E: + case HRTIM_TIMERINDEX_TIMER_E: { hrtim_bmcr &= ~(HRTIM_BMCR_TEBM); - hrtim_bmcr |= ( pTimerCfg->BurstMode << 5U); + hrtim_bmcr |= (pTimerCfg->BurstMode << 5U); break; } - default: - break; + default: + break; } /* Update the HRTIM registers */ @@ -7910,7 +7921,7 @@ static void HRTIM_TimingUnitWaveform_Config(HRTIM_HandleTypeDef * hhrtim, * @param Event Event reference * @retval None */ -static void HRTIM_CaptureUnitConfig(HRTIM_HandleTypeDef * hhrtim, +static void HRTIM_CaptureUnitConfig(HRTIM_HandleTypeDef *hhrtim, uint32_t TimerIdx, uint32_t CaptureUnit, uint32_t Event) @@ -7919,86 +7930,86 @@ static void HRTIM_CaptureUnitConfig(HRTIM_HandleTypeDef * hhrtim, switch (Event) { - case HRTIM_EVENT_1: + case HRTIM_EVENT_1: { CaptureTrigger = HRTIM_CAPTURETRIGGER_EEV_1; break; } - case HRTIM_EVENT_2: + case HRTIM_EVENT_2: { CaptureTrigger = HRTIM_CAPTURETRIGGER_EEV_2; break; } - case HRTIM_EVENT_3: + case HRTIM_EVENT_3: { CaptureTrigger = HRTIM_CAPTURETRIGGER_EEV_3; break; } - case HRTIM_EVENT_4: + case HRTIM_EVENT_4: { CaptureTrigger = HRTIM_CAPTURETRIGGER_EEV_4; break; } - case HRTIM_EVENT_5: + case HRTIM_EVENT_5: { CaptureTrigger = HRTIM_CAPTURETRIGGER_EEV_5; break; } - case HRTIM_EVENT_6: + case HRTIM_EVENT_6: { CaptureTrigger = HRTIM_CAPTURETRIGGER_EEV_6; break; } - case HRTIM_EVENT_7: + case HRTIM_EVENT_7: { CaptureTrigger = HRTIM_CAPTURETRIGGER_EEV_7; break; } - case HRTIM_EVENT_8: + case HRTIM_EVENT_8: { CaptureTrigger = HRTIM_CAPTURETRIGGER_EEV_8; break; } - case HRTIM_EVENT_9: + case HRTIM_EVENT_9: { CaptureTrigger = HRTIM_CAPTURETRIGGER_EEV_9; break; } - case HRTIM_EVENT_10: + case HRTIM_EVENT_10: { CaptureTrigger = HRTIM_CAPTURETRIGGER_EEV_10; break; } - default: - break; + default: + break; } switch (CaptureUnit) { - case HRTIM_CAPTUREUNIT_1: + case HRTIM_CAPTUREUNIT_1: { hhrtim->TimerParam[TimerIdx].CaptureTrigger1 = CaptureTrigger; break; } - case HRTIM_CAPTUREUNIT_2: + case HRTIM_CAPTUREUNIT_2: { hhrtim->TimerParam[TimerIdx].CaptureTrigger2 = CaptureTrigger; break; } - default: - break; + default: + break; } } @@ -8010,10 +8021,10 @@ static void HRTIM_CaptureUnitConfig(HRTIM_HandleTypeDef * hhrtim, * @param pOutputCfg pointer to the output configuration data structure * @retval None */ -static void HRTIM_OutputConfig(HRTIM_HandleTypeDef * hhrtim, +static void HRTIM_OutputConfig(HRTIM_HandleTypeDef *hhrtim, uint32_t TimerIdx, uint32_t Output, - const HRTIM_OutputCfgTypeDef * pOutputCfg) + const HRTIM_OutputCfgTypeDef *pOutputCfg) { uint32_t hrtim_outr; uint32_t hrtim_dtr; @@ -8025,11 +8036,11 @@ static void HRTIM_OutputConfig(HRTIM_HandleTypeDef * hhrtim, switch (Output) { - case HRTIM_OUTPUT_TA1: - case HRTIM_OUTPUT_TB1: - case HRTIM_OUTPUT_TC1: - case HRTIM_OUTPUT_TD1: - case HRTIM_OUTPUT_TE1: + case HRTIM_OUTPUT_TA1: + case HRTIM_OUTPUT_TB1: + case HRTIM_OUTPUT_TC1: + case HRTIM_OUTPUT_TD1: + case HRTIM_OUTPUT_TE1: { /* Set the output set/reset crossbar */ hhrtim->Instance->sTimerxRegs[TimerIdx].SETx1R = pOutputCfg->SetSource; @@ -8037,11 +8048,11 @@ static void HRTIM_OutputConfig(HRTIM_HandleTypeDef * hhrtim, break; } - case HRTIM_OUTPUT_TA2: - case HRTIM_OUTPUT_TB2: - case HRTIM_OUTPUT_TC2: - case HRTIM_OUTPUT_TD2: - case HRTIM_OUTPUT_TE2: + case HRTIM_OUTPUT_TA2: + case HRTIM_OUTPUT_TB2: + case HRTIM_OUTPUT_TC2: + case HRTIM_OUTPUT_TD2: + case HRTIM_OUTPUT_TE2: { /* Set the output set/reset crossbar */ hhrtim->Instance->sTimerxRegs[TimerIdx].SETx2R = pOutputCfg->SetSource; @@ -8050,15 +8061,15 @@ static void HRTIM_OutputConfig(HRTIM_HandleTypeDef * hhrtim, break; } - default: - break; + default: + break; } /* Clear output config */ hrtim_outr &= ~((HRTIM_OUTR_POL1 | HRTIM_OUTR_IDLM1 | - HRTIM_OUTR_IDLES1| - HRTIM_OUTR_FAULT1| + HRTIM_OUTR_IDLES1 | + HRTIM_OUTR_FAULT1 | HRTIM_OUTR_CHP1 | HRTIM_OUTR_DIDL1) << shift); @@ -8101,7 +8112,7 @@ static void HRTIM_OutputConfig(HRTIM_HandleTypeDef * hhrtim, * @param pEventCfg pointer to the event channel configuration data structure * @retval None */ -static void HRTIM_EventConfig(HRTIM_HandleTypeDef * hhrtim, +static void HRTIM_EventConfig(HRTIM_HandleTypeDef *hhrtim, uint32_t Event, const HRTIM_EventCfgTypeDef *pEventCfg) { @@ -8116,7 +8127,7 @@ static void HRTIM_EventConfig(HRTIM_HandleTypeDef * hhrtim, switch (Event) { - case HRTIM_EVENT_NONE: + case HRTIM_EVENT_NONE: { /* Update the HRTIM registers */ hhrtim->Instance->sCommonRegs.EECR1 = 0U; @@ -8125,7 +8136,7 @@ static void HRTIM_EventConfig(HRTIM_HandleTypeDef * hhrtim, break; } - case HRTIM_EVENT_1: + case HRTIM_EVENT_1: { hrtim_eecr1 &= ~(HRTIM_EECR1_EE1SRC | HRTIM_EECR1_EE1POL | HRTIM_EECR1_EE1SNS | HRTIM_EECR1_EE1FAST); hrtim_eecr1 |= (pEventCfg->Source & HRTIM_EECR1_EE1SRC); @@ -8139,7 +8150,7 @@ static void HRTIM_EventConfig(HRTIM_HandleTypeDef * hhrtim, break; } - case HRTIM_EVENT_2: + case HRTIM_EVENT_2: { hrtim_eecr1 &= ~(HRTIM_EECR1_EE2SRC | HRTIM_EECR1_EE2POL | HRTIM_EECR1_EE2SNS | HRTIM_EECR1_EE2FAST); hrtim_eecr1 |= ((pEventCfg->Source << 6U) & HRTIM_EECR1_EE2SRC); @@ -8153,7 +8164,7 @@ static void HRTIM_EventConfig(HRTIM_HandleTypeDef * hhrtim, break; } - case HRTIM_EVENT_3: + case HRTIM_EVENT_3: { hrtim_eecr1 &= ~(HRTIM_EECR1_EE3SRC | HRTIM_EECR1_EE3POL | HRTIM_EECR1_EE3SNS | HRTIM_EECR1_EE3FAST); hrtim_eecr1 |= ((pEventCfg->Source << 12U) & HRTIM_EECR1_EE3SRC); @@ -8167,7 +8178,7 @@ static void HRTIM_EventConfig(HRTIM_HandleTypeDef * hhrtim, break; } - case HRTIM_EVENT_4: + case HRTIM_EVENT_4: { hrtim_eecr1 &= ~(HRTIM_EECR1_EE4SRC | HRTIM_EECR1_EE4POL | HRTIM_EECR1_EE4SNS | HRTIM_EECR1_EE4FAST); hrtim_eecr1 |= ((pEventCfg->Source << 18U) & HRTIM_EECR1_EE4SRC); @@ -8181,7 +8192,7 @@ static void HRTIM_EventConfig(HRTIM_HandleTypeDef * hhrtim, break; } - case HRTIM_EVENT_5: + case HRTIM_EVENT_5: { hrtim_eecr1 &= ~(HRTIM_EECR1_EE5SRC | HRTIM_EECR1_EE5POL | HRTIM_EECR1_EE5SNS | HRTIM_EECR1_EE5FAST); hrtim_eecr1 |= ((pEventCfg->Source << 24U) & HRTIM_EECR1_EE5SRC); @@ -8195,7 +8206,7 @@ static void HRTIM_EventConfig(HRTIM_HandleTypeDef * hhrtim, break; } - case HRTIM_EVENT_6: + case HRTIM_EVENT_6: { hrtim_eecr2 &= ~(HRTIM_EECR2_EE6SRC | HRTIM_EECR2_EE6POL | HRTIM_EECR2_EE6SNS); hrtim_eecr2 |= (pEventCfg->Source & HRTIM_EECR2_EE6SRC); @@ -8209,7 +8220,7 @@ static void HRTIM_EventConfig(HRTIM_HandleTypeDef * hhrtim, break; } - case HRTIM_EVENT_7: + case HRTIM_EVENT_7: { hrtim_eecr2 &= ~(HRTIM_EECR2_EE7SRC | HRTIM_EECR2_EE7POL | HRTIM_EECR2_EE7SNS); hrtim_eecr2 |= ((pEventCfg->Source << 6U) & HRTIM_EECR2_EE7SRC); @@ -8223,21 +8234,21 @@ static void HRTIM_EventConfig(HRTIM_HandleTypeDef * hhrtim, break; } - case HRTIM_EVENT_8: + case HRTIM_EVENT_8: { hrtim_eecr2 &= ~(HRTIM_EECR2_EE8SRC | HRTIM_EECR2_EE8POL | HRTIM_EECR2_EE8SNS); hrtim_eecr2 |= ((pEventCfg->Source << 12U) & HRTIM_EECR2_EE8SRC); hrtim_eecr2 |= ((pEventCfg->Polarity << 12U) & HRTIM_EECR2_EE8POL); hrtim_eecr2 |= ((pEventCfg->Sensitivity << 12U) & HRTIM_EECR2_EE8SNS); hrtim_eecr3 &= ~(HRTIM_EECR3_EE8F); - hrtim_eecr3 |= ((pEventCfg->Filter << 12U) & HRTIM_EECR3_EE8F ); + hrtim_eecr3 |= ((pEventCfg->Filter << 12U) & HRTIM_EECR3_EE8F); /* Update the HRTIM registers */ hhrtim->Instance->sCommonRegs.EECR2 = hrtim_eecr2; hhrtim->Instance->sCommonRegs.EECR3 = hrtim_eecr3; break; } - case HRTIM_EVENT_9: + case HRTIM_EVENT_9: { hrtim_eecr2 &= ~(HRTIM_EECR2_EE9SRC | HRTIM_EECR2_EE9POL | HRTIM_EECR2_EE9SNS); hrtim_eecr2 |= ((pEventCfg->Source << 18U) & HRTIM_EECR2_EE9SRC); @@ -8251,7 +8262,7 @@ static void HRTIM_EventConfig(HRTIM_HandleTypeDef * hhrtim, break; } - case HRTIM_EVENT_10: + case HRTIM_EVENT_10: { hrtim_eecr2 &= ~(HRTIM_EECR2_EE10SRC | HRTIM_EECR2_EE10POL | HRTIM_EECR2_EE10SNS); hrtim_eecr2 |= ((pEventCfg->Source << 24U) & HRTIM_EECR2_EE10SRC); @@ -8265,8 +8276,8 @@ static void HRTIM_EventConfig(HRTIM_HandleTypeDef * hhrtim, break; } - default: - break; + default: + break; } } @@ -8277,74 +8288,74 @@ static void HRTIM_EventConfig(HRTIM_HandleTypeDef * hhrtim, * @param Event Event channel identifier * @retval None */ -static void HRTIM_TIM_ResetConfig(HRTIM_HandleTypeDef * hhrtim, +static void HRTIM_TIM_ResetConfig(HRTIM_HandleTypeDef *hhrtim, uint32_t TimerIdx, uint32_t Event) { switch (Event) { - case HRTIM_EVENT_1: + case HRTIM_EVENT_1: { hhrtim->Instance->sTimerxRegs[TimerIdx].RSTxR = HRTIM_TIMRESETTRIGGER_EEV_1; break; } - case HRTIM_EVENT_2: + case HRTIM_EVENT_2: { hhrtim->Instance->sTimerxRegs[TimerIdx].RSTxR = HRTIM_TIMRESETTRIGGER_EEV_2; break; } - case HRTIM_EVENT_3: + case HRTIM_EVENT_3: { hhrtim->Instance->sTimerxRegs[TimerIdx].RSTxR = HRTIM_TIMRESETTRIGGER_EEV_3; break; } - case HRTIM_EVENT_4: + case HRTIM_EVENT_4: { hhrtim->Instance->sTimerxRegs[TimerIdx].RSTxR = HRTIM_TIMRESETTRIGGER_EEV_4; break; } - case HRTIM_EVENT_5: + case HRTIM_EVENT_5: { hhrtim->Instance->sTimerxRegs[TimerIdx].RSTxR = HRTIM_TIMRESETTRIGGER_EEV_5; break; } - case HRTIM_EVENT_6: + case HRTIM_EVENT_6: { hhrtim->Instance->sTimerxRegs[TimerIdx].RSTxR = HRTIM_TIMRESETTRIGGER_EEV_6; break; } - case HRTIM_EVENT_7: + case HRTIM_EVENT_7: { hhrtim->Instance->sTimerxRegs[TimerIdx].RSTxR = HRTIM_TIMRESETTRIGGER_EEV_7; break; } - case HRTIM_EVENT_8: + case HRTIM_EVENT_8: { hhrtim->Instance->sTimerxRegs[TimerIdx].RSTxR = HRTIM_TIMRESETTRIGGER_EEV_8; break; } - case HRTIM_EVENT_9: + case HRTIM_EVENT_9: { hhrtim->Instance->sTimerxRegs[TimerIdx].RSTxR = HRTIM_TIMRESETTRIGGER_EEV_9; break; } - case HRTIM_EVENT_10: + case HRTIM_EVENT_10: { hhrtim->Instance->sTimerxRegs[TimerIdx].RSTxR = HRTIM_TIMRESETTRIGGER_EEV_10; break; } - default: - break; + default: + break; } } @@ -8367,7 +8378,7 @@ static void HRTIM_TIM_ResetConfig(HRTIM_HandleTypeDef * hhrtim, * @arg HRTIM_OUTPUT_TE2: Timer E - Output 2 * @retval Interrupt to enable or disable */ -static uint32_t HRTIM_GetITFromOCMode(const HRTIM_HandleTypeDef * hhrtim, +static uint32_t HRTIM_GetITFromOCMode(const HRTIM_HandleTypeDef *hhrtim, uint32_t TimerIdx, uint32_t OCChannel) { @@ -8377,13 +8388,13 @@ static uint32_t HRTIM_GetITFromOCMode(const HRTIM_HandleTypeDef * hhrtim, switch (OCChannel) { - case HRTIM_OUTPUT_TA1: - case HRTIM_OUTPUT_TB1: - case HRTIM_OUTPUT_TC1: - case HRTIM_OUTPUT_TD1: - case HRTIM_OUTPUT_TE1: + case HRTIM_OUTPUT_TA1: + case HRTIM_OUTPUT_TB1: + case HRTIM_OUTPUT_TC1: + case HRTIM_OUTPUT_TD1: + case HRTIM_OUTPUT_TE1: { - /* Retreives actual OC mode and set interrupt accordingly */ + /* Retrieves actual OC mode and set interrupt accordingly */ hrtim_set = hhrtim->Instance->sTimerxRegs[TimerIdx].SETx1R; hrtim_reset = hhrtim->Instance->sTimerxRegs[TimerIdx].RSTx1R; @@ -8396,29 +8407,29 @@ static uint32_t HRTIM_GetITFromOCMode(const HRTIM_HandleTypeDef * hhrtim, else if (((hrtim_set & HRTIM_OUTPUTSET_TIMCMP1) == HRTIM_OUTPUTSET_TIMCMP1) && (hrtim_reset == 0U)) { - /* OC mode: HRTIM_BASICOCMODE_ACTIVE */ + /* OC mode: HRTIM_BASICOCMODE_ACTIVE */ interrupt = HRTIM_TIM_IT_SET1; } else if ((hrtim_set == 0U) && ((hrtim_reset & HRTIM_OUTPUTRESET_TIMCMP1) == HRTIM_OUTPUTRESET_TIMCMP1)) { - /* OC mode: HRTIM_BASICOCMODE_INACTIVE */ + /* OC mode: HRTIM_BASICOCMODE_INACTIVE */ interrupt = HRTIM_TIM_IT_RST1; } else { - /* nothing to do */ + /* nothing to do */ } break; } - case HRTIM_OUTPUT_TA2: - case HRTIM_OUTPUT_TB2: - case HRTIM_OUTPUT_TC2: - case HRTIM_OUTPUT_TD2: - case HRTIM_OUTPUT_TE2: + case HRTIM_OUTPUT_TA2: + case HRTIM_OUTPUT_TB2: + case HRTIM_OUTPUT_TC2: + case HRTIM_OUTPUT_TD2: + case HRTIM_OUTPUT_TE2: { - /* Retreives actual OC mode and set interrupt accordingly */ + /* Retrieves actual OC mode and set interrupt accordingly */ hrtim_set = hhrtim->Instance->sTimerxRegs[TimerIdx].SETx2R; hrtim_reset = hhrtim->Instance->sTimerxRegs[TimerIdx].RSTx2R; @@ -8431,24 +8442,24 @@ static uint32_t HRTIM_GetITFromOCMode(const HRTIM_HandleTypeDef * hhrtim, else if (((hrtim_set & HRTIM_OUTPUTSET_TIMCMP2) == HRTIM_OUTPUTSET_TIMCMP2) && (hrtim_reset == 0U)) { - /* OC mode: HRTIM_BASICOCMODE_ACTIVE */ + /* OC mode: HRTIM_BASICOCMODE_ACTIVE */ interrupt = HRTIM_TIM_IT_SET2; } else if ((hrtim_set == 0U) && ((hrtim_reset & HRTIM_OUTPUTRESET_TIMCMP2) == HRTIM_OUTPUTRESET_TIMCMP2)) { - /* OC mode: HRTIM_BASICOCMODE_INACTIVE */ + /* OC mode: HRTIM_BASICOCMODE_INACTIVE */ interrupt = HRTIM_TIM_IT_RST2; } else { - /* nothing to do */ + /* nothing to do */ } break; } - default: - break; + default: + break; } return interrupt; @@ -8473,7 +8484,7 @@ static uint32_t HRTIM_GetITFromOCMode(const HRTIM_HandleTypeDef * hhrtim, * @arg HRTIM_OUTPUT_TE2: Timer E - Output 2 * @retval DMA request to enable or disable */ -static uint32_t HRTIM_GetDMAFromOCMode(const HRTIM_HandleTypeDef * hhrtim, +static uint32_t HRTIM_GetDMAFromOCMode(const HRTIM_HandleTypeDef *hhrtim, uint32_t TimerIdx, uint32_t OCChannel) { @@ -8483,13 +8494,13 @@ static uint32_t HRTIM_GetDMAFromOCMode(const HRTIM_HandleTypeDef * hhrtim, switch (OCChannel) { - case HRTIM_OUTPUT_TA1: - case HRTIM_OUTPUT_TB1: - case HRTIM_OUTPUT_TC1: - case HRTIM_OUTPUT_TD1: - case HRTIM_OUTPUT_TE1: + case HRTIM_OUTPUT_TA1: + case HRTIM_OUTPUT_TB1: + case HRTIM_OUTPUT_TC1: + case HRTIM_OUTPUT_TD1: + case HRTIM_OUTPUT_TE1: { - /* Retreives actual OC mode and set dma_request accordingly */ + /* Retrieves actual OC mode and set dma_request accordingly */ hrtim_set = hhrtim->Instance->sTimerxRegs[TimerIdx].SETx1R; hrtim_reset = hhrtim->Instance->sTimerxRegs[TimerIdx].RSTx1R; @@ -8502,29 +8513,29 @@ static uint32_t HRTIM_GetDMAFromOCMode(const HRTIM_HandleTypeDef * hhrtim, else if (((hrtim_set & HRTIM_OUTPUTSET_TIMCMP1) == HRTIM_OUTPUTSET_TIMCMP1) && (hrtim_reset == 0U)) { - /* OC mode: HRTIM_BASICOCMODE_ACTIVE */ + /* OC mode: HRTIM_BASICOCMODE_ACTIVE */ dma_request = HRTIM_TIM_DMA_SET1; } else if ((hrtim_set == 0U) && ((hrtim_reset & HRTIM_OUTPUTRESET_TIMCMP1) == HRTIM_OUTPUTRESET_TIMCMP1)) { - /* OC mode: HRTIM_BASICOCMODE_INACTIVE */ + /* OC mode: HRTIM_BASICOCMODE_INACTIVE */ dma_request = HRTIM_TIM_DMA_RST1; } else { - /* nothing to do */ + /* nothing to do */ } break; } - case HRTIM_OUTPUT_TA2: - case HRTIM_OUTPUT_TB2: - case HRTIM_OUTPUT_TC2: - case HRTIM_OUTPUT_TD2: - case HRTIM_OUTPUT_TE2: + case HRTIM_OUTPUT_TA2: + case HRTIM_OUTPUT_TB2: + case HRTIM_OUTPUT_TC2: + case HRTIM_OUTPUT_TD2: + case HRTIM_OUTPUT_TE2: { - /* Retreives actual OC mode and set dma_request accordingly */ + /* Retrieves actual OC mode and set dma_request accordingly */ hrtim_set = hhrtim->Instance->sTimerxRegs[TimerIdx].SETx2R; hrtim_reset = hhrtim->Instance->sTimerxRegs[TimerIdx].RSTx2R; @@ -8537,81 +8548,81 @@ static uint32_t HRTIM_GetDMAFromOCMode(const HRTIM_HandleTypeDef * hhrtim, else if (((hrtim_set & HRTIM_OUTPUTSET_TIMCMP2) == HRTIM_OUTPUTSET_TIMCMP2) && (hrtim_reset == 0U)) { - /* OC mode: HRTIM_BASICOCMODE_ACTIVE */ + /* OC mode: HRTIM_BASICOCMODE_ACTIVE */ dma_request = HRTIM_TIM_DMA_SET2; } else if ((hrtim_set == 0U) && ((hrtim_reset & HRTIM_OUTPUTRESET_TIMCMP2) == HRTIM_OUTPUTRESET_TIMCMP2)) { - /* OC mode: HRTIM_BASICOCMODE_INACTIVE */ + /* OC mode: HRTIM_BASICOCMODE_INACTIVE */ dma_request = HRTIM_TIM_DMA_RST2; } else { - /* nothing to do */ + /* nothing to do */ } break; } - default: - break; + default: + break; } return dma_request; } -static DMA_HandleTypeDef * HRTIM_GetDMAHandleFromTimerIdx(const HRTIM_HandleTypeDef * hhrtim, - uint32_t TimerIdx) +static DMA_HandleTypeDef *HRTIM_GetDMAHandleFromTimerIdx(const HRTIM_HandleTypeDef *hhrtim, + uint32_t TimerIdx) { - DMA_HandleTypeDef * hdma = (DMA_HandleTypeDef *)NULL; + DMA_HandleTypeDef *hdma = (DMA_HandleTypeDef *)NULL; switch (TimerIdx) { - case HRTIM_TIMERINDEX_MASTER: + case HRTIM_TIMERINDEX_MASTER: { hdma = hhrtim->hdmaMaster; break; } - case HRTIM_TIMERINDEX_TIMER_A: + case HRTIM_TIMERINDEX_TIMER_A: { hdma = hhrtim->hdmaTimerA; break; } - case HRTIM_TIMERINDEX_TIMER_B: + case HRTIM_TIMERINDEX_TIMER_B: { hdma = hhrtim->hdmaTimerB; break; } - case HRTIM_TIMERINDEX_TIMER_C: + case HRTIM_TIMERINDEX_TIMER_C: { hdma = hhrtim->hdmaTimerC; break; } - case HRTIM_TIMERINDEX_TIMER_D: + case HRTIM_TIMERINDEX_TIMER_D: { hdma = hhrtim->hdmaTimerD; break; } - case HRTIM_TIMERINDEX_TIMER_E: + case HRTIM_TIMERINDEX_TIMER_E: { hdma = hhrtim->hdmaTimerE; break; } - default: - break; + default: + break; } return hdma; } -static uint32_t GetTimerIdxFromDMAHandle(const HRTIM_HandleTypeDef * hhrtim, - const DMA_HandleTypeDef * hdma) +static uint32_t GetTimerIdxFromDMAHandle(const HRTIM_HandleTypeDef *hhrtim, + const DMA_HandleTypeDef *hdma) { uint32_t timed_idx = 0xFFFFFFFFU; @@ -8653,49 +8664,49 @@ static uint32_t GetTimerIdxFromDMAHandle(const HRTIM_HandleTypeDef * hhrtim, * @param TimerIdx Timer index * @retval None */ -static void HRTIM_ForceRegistersUpdate(HRTIM_HandleTypeDef * hhrtim, +static void HRTIM_ForceRegistersUpdate(HRTIM_HandleTypeDef *hhrtim, uint32_t TimerIdx) { switch (TimerIdx) { - case HRTIM_TIMERINDEX_MASTER: + case HRTIM_TIMERINDEX_MASTER: { hhrtim->Instance->sCommonRegs.CR2 |= HRTIM_CR2_MSWU; break; } - case HRTIM_TIMERINDEX_TIMER_A: + case HRTIM_TIMERINDEX_TIMER_A: { hhrtim->Instance->sCommonRegs.CR2 |= HRTIM_CR2_TASWU; break; } - case HRTIM_TIMERINDEX_TIMER_B: + case HRTIM_TIMERINDEX_TIMER_B: { hhrtim->Instance->sCommonRegs.CR2 |= HRTIM_CR2_TBSWU; break; } - case HRTIM_TIMERINDEX_TIMER_C: + case HRTIM_TIMERINDEX_TIMER_C: { hhrtim->Instance->sCommonRegs.CR2 |= HRTIM_CR2_TCSWU; break; } - case HRTIM_TIMERINDEX_TIMER_D: + case HRTIM_TIMERINDEX_TIMER_D: { hhrtim->Instance->sCommonRegs.CR2 |= HRTIM_CR2_TDSWU; break; } - case HRTIM_TIMERINDEX_TIMER_E: + case HRTIM_TIMERINDEX_TIMER_E: { hhrtim->Instance->sCommonRegs.CR2 |= HRTIM_CR2_TESWU; break; } - default: - break; + default: + break; } } @@ -8705,15 +8716,15 @@ static void HRTIM_ForceRegistersUpdate(HRTIM_HandleTypeDef * hhrtim, * @param hhrtim pointer to HAL HRTIM handle * @retval None */ -static void HRTIM_HRTIM_ISR(HRTIM_HandleTypeDef * hhrtim) +static void HRTIM_HRTIM_ISR(HRTIM_HandleTypeDef *hhrtim) { uint32_t isrflags = READ_REG(hhrtim->Instance->sCommonRegs.ISR); uint32_t ierits = READ_REG(hhrtim->Instance->sCommonRegs.IER); /* Fault 1 event */ - if((uint32_t)(isrflags & HRTIM_FLAG_FLT1) != (uint32_t)RESET) + if ((uint32_t)(isrflags & HRTIM_FLAG_FLT1) != (uint32_t)RESET) { - if((uint32_t)(ierits & HRTIM_IT_FLT1) != (uint32_t)RESET) + if ((uint32_t)(ierits & HRTIM_IT_FLT1) != (uint32_t)RESET) { __HAL_HRTIM_CLEAR_IT(hhrtim, HRTIM_IT_FLT1); @@ -8727,9 +8738,9 @@ static void HRTIM_HRTIM_ISR(HRTIM_HandleTypeDef * hhrtim) } /* Fault 2 event */ - if((uint32_t)(isrflags & HRTIM_FLAG_FLT2) != (uint32_t)RESET) + if ((uint32_t)(isrflags & HRTIM_FLAG_FLT2) != (uint32_t)RESET) { - if((uint32_t)(ierits & HRTIM_IT_FLT2) != (uint32_t)RESET) + if ((uint32_t)(ierits & HRTIM_IT_FLT2) != (uint32_t)RESET) { __HAL_HRTIM_CLEAR_IT(hhrtim, HRTIM_IT_FLT2); @@ -8743,9 +8754,9 @@ static void HRTIM_HRTIM_ISR(HRTIM_HandleTypeDef * hhrtim) } /* Fault 3 event */ - if((uint32_t)(isrflags & HRTIM_FLAG_FLT3) != (uint32_t)RESET) + if ((uint32_t)(isrflags & HRTIM_FLAG_FLT3) != (uint32_t)RESET) { - if((uint32_t)(ierits & HRTIM_IT_FLT3) != (uint32_t)RESET) + if ((uint32_t)(ierits & HRTIM_IT_FLT3) != (uint32_t)RESET) { __HAL_HRTIM_CLEAR_IT(hhrtim, HRTIM_IT_FLT3); @@ -8759,9 +8770,9 @@ static void HRTIM_HRTIM_ISR(HRTIM_HandleTypeDef * hhrtim) } /* Fault 4 event */ - if((uint32_t)(isrflags & HRTIM_FLAG_FLT4) != (uint32_t)RESET) + if ((uint32_t)(isrflags & HRTIM_FLAG_FLT4) != (uint32_t)RESET) { - if((uint32_t)(ierits & HRTIM_IT_FLT4) != (uint32_t)RESET) + if ((uint32_t)(ierits & HRTIM_IT_FLT4) != (uint32_t)RESET) { __HAL_HRTIM_CLEAR_IT(hhrtim, HRTIM_IT_FLT4); @@ -8775,9 +8786,9 @@ static void HRTIM_HRTIM_ISR(HRTIM_HandleTypeDef * hhrtim) } /* Fault 5 event */ - if((uint32_t)(isrflags & HRTIM_FLAG_FLT5) != (uint32_t)RESET) + if ((uint32_t)(isrflags & HRTIM_FLAG_FLT5) != (uint32_t)RESET) { - if((uint32_t)(ierits & HRTIM_IT_FLT5) != (uint32_t)RESET) + if ((uint32_t)(ierits & HRTIM_IT_FLT5) != (uint32_t)RESET) { __HAL_HRTIM_CLEAR_IT(hhrtim, HRTIM_IT_FLT5); @@ -8791,9 +8802,9 @@ static void HRTIM_HRTIM_ISR(HRTIM_HandleTypeDef * hhrtim) } /* System fault event */ - if((uint32_t)(isrflags & HRTIM_FLAG_SYSFLT) != (uint32_t)RESET) + if ((uint32_t)(isrflags & HRTIM_FLAG_SYSFLT) != (uint32_t)RESET) { - if((uint32_t)(ierits & HRTIM_IT_SYSFLT) != (uint32_t)RESET) + if ((uint32_t)(ierits & HRTIM_IT_SYSFLT) != (uint32_t)RESET) { __HAL_HRTIM_CLEAR_IT(hhrtim, HRTIM_IT_SYSFLT); @@ -8808,11 +8819,11 @@ static void HRTIM_HRTIM_ISR(HRTIM_HandleTypeDef * hhrtim) } /** -* @brief Master timer interrupts service routine -* @param hhrtim pointer to HAL HRTIM handle -* @retval None -*/ -static void HRTIM_Master_ISR(HRTIM_HandleTypeDef * hhrtim) + * @brief Master timer interrupts service routine + * @param hhrtim pointer to HAL HRTIM handle + * @retval None + */ +static void HRTIM_Master_ISR(HRTIM_HandleTypeDef *hhrtim) { uint32_t isrflags = READ_REG(hhrtim->Instance->sCommonRegs.ISR); uint32_t ierits = READ_REG(hhrtim->Instance->sCommonRegs.IER); @@ -8820,9 +8831,9 @@ static void HRTIM_Master_ISR(HRTIM_HandleTypeDef * hhrtim) uint32_t mdierits = READ_REG(hhrtim->Instance->sMasterRegs.MDIER); /* DLL calibration ready event */ - if((uint32_t)(isrflags & HRTIM_FLAG_DLLRDY) != (uint32_t)RESET) + if ((uint32_t)(isrflags & HRTIM_FLAG_DLLRDY) != (uint32_t)RESET) { - if((uint32_t)(ierits & HRTIM_IT_DLLRDY) != (uint32_t)RESET) + if ((uint32_t)(ierits & HRTIM_IT_DLLRDY) != (uint32_t)RESET) { __HAL_HRTIM_CLEAR_IT(hhrtim, HRTIM_IT_DLLRDY); @@ -8842,9 +8853,9 @@ static void HRTIM_Master_ISR(HRTIM_HandleTypeDef * hhrtim) } /* Burst mode period event */ - if((uint32_t)(isrflags & HRTIM_FLAG_BMPER) != (uint32_t)RESET) + if ((uint32_t)(isrflags & HRTIM_FLAG_BMPER) != (uint32_t)RESET) { - if((uint32_t)(ierits & HRTIM_IT_BMPER) != (uint32_t)RESET) + if ((uint32_t)(ierits & HRTIM_IT_BMPER) != (uint32_t)RESET) { __HAL_HRTIM_CLEAR_IT(hhrtim, HRTIM_IT_BMPER); @@ -8858,9 +8869,9 @@ static void HRTIM_Master_ISR(HRTIM_HandleTypeDef * hhrtim) } /* Master timer compare 1 event */ - if((uint32_t)(misrflags & HRTIM_MASTER_FLAG_MCMP1) != (uint32_t)RESET) + if ((uint32_t)(misrflags & HRTIM_MASTER_FLAG_MCMP1) != (uint32_t)RESET) { - if((uint32_t)(mdierits & HRTIM_MASTER_IT_MCMP1) != (uint32_t)RESET) + if ((uint32_t)(mdierits & HRTIM_MASTER_IT_MCMP1) != (uint32_t)RESET) { __HAL_HRTIM_MASTER_CLEAR_IT(hhrtim, HRTIM_MASTER_IT_MCMP1); @@ -8874,9 +8885,9 @@ static void HRTIM_Master_ISR(HRTIM_HandleTypeDef * hhrtim) } /* Master timer compare 2 event */ - if((uint32_t)(misrflags & HRTIM_MASTER_FLAG_MCMP2) != (uint32_t)RESET) + if ((uint32_t)(misrflags & HRTIM_MASTER_FLAG_MCMP2) != (uint32_t)RESET) { - if((uint32_t)(mdierits & HRTIM_MASTER_IT_MCMP2) != (uint32_t)RESET) + if ((uint32_t)(mdierits & HRTIM_MASTER_IT_MCMP2) != (uint32_t)RESET) { __HAL_HRTIM_MASTER_CLEAR_IT(hhrtim, HRTIM_MASTER_IT_MCMP2); @@ -8890,9 +8901,9 @@ static void HRTIM_Master_ISR(HRTIM_HandleTypeDef * hhrtim) } /* Master timer compare 3 event */ - if((uint32_t)(misrflags & HRTIM_MASTER_FLAG_MCMP3) != (uint32_t)RESET) + if ((uint32_t)(misrflags & HRTIM_MASTER_FLAG_MCMP3) != (uint32_t)RESET) { - if((uint32_t)(mdierits & HRTIM_MASTER_IT_MCMP3) != (uint32_t)RESET) + if ((uint32_t)(mdierits & HRTIM_MASTER_IT_MCMP3) != (uint32_t)RESET) { __HAL_HRTIM_MASTER_CLEAR_IT(hhrtim, HRTIM_MASTER_IT_MCMP3); @@ -8906,9 +8917,9 @@ static void HRTIM_Master_ISR(HRTIM_HandleTypeDef * hhrtim) } /* Master timer compare 4 event */ - if((uint32_t)(misrflags & HRTIM_MASTER_FLAG_MCMP4) != (uint32_t)RESET) + if ((uint32_t)(misrflags & HRTIM_MASTER_FLAG_MCMP4) != (uint32_t)RESET) { - if((uint32_t)(mdierits & HRTIM_MASTER_IT_MCMP4) != (uint32_t)RESET) + if ((uint32_t)(mdierits & HRTIM_MASTER_IT_MCMP4) != (uint32_t)RESET) { __HAL_HRTIM_MASTER_CLEAR_IT(hhrtim, HRTIM_MASTER_IT_MCMP4); @@ -8922,9 +8933,9 @@ static void HRTIM_Master_ISR(HRTIM_HandleTypeDef * hhrtim) } /* Master timer repetition event */ - if((uint32_t)(misrflags & HRTIM_MASTER_FLAG_MREP) != (uint32_t)RESET) + if ((uint32_t)(misrflags & HRTIM_MASTER_FLAG_MREP) != (uint32_t)RESET) { - if((uint32_t)(mdierits & HRTIM_MASTER_IT_MREP) != (uint32_t)RESET) + if ((uint32_t)(mdierits & HRTIM_MASTER_IT_MREP) != (uint32_t)RESET) { __HAL_HRTIM_MASTER_CLEAR_IT(hhrtim, HRTIM_MASTER_IT_MREP); @@ -8938,9 +8949,9 @@ static void HRTIM_Master_ISR(HRTIM_HandleTypeDef * hhrtim) } /* Synchronization input event */ - if((uint32_t)(misrflags & HRTIM_MASTER_FLAG_SYNC) != (uint32_t)RESET) + if ((uint32_t)(misrflags & HRTIM_MASTER_FLAG_SYNC) != (uint32_t)RESET) { - if((uint32_t)(mdierits & HRTIM_MASTER_IT_SYNC) != (uint32_t)RESET) + if ((uint32_t)(mdierits & HRTIM_MASTER_IT_SYNC) != (uint32_t)RESET) { __HAL_HRTIM_MASTER_CLEAR_IT(hhrtim, HRTIM_MASTER_IT_SYNC); @@ -8954,9 +8965,9 @@ static void HRTIM_Master_ISR(HRTIM_HandleTypeDef * hhrtim) } /* Master timer registers update event */ - if((uint32_t)(misrflags & HRTIM_MASTER_FLAG_MUPD) != (uint32_t)RESET) + if ((uint32_t)(misrflags & HRTIM_MASTER_FLAG_MUPD) != (uint32_t)RESET) { - if((uint32_t)(mdierits & HRTIM_MASTER_IT_MUPD) != (uint32_t)RESET) + if ((uint32_t)(mdierits & HRTIM_MASTER_IT_MUPD) != (uint32_t)RESET) { __HAL_HRTIM_MASTER_CLEAR_IT(hhrtim, HRTIM_MASTER_IT_MUPD); @@ -8981,17 +8992,17 @@ static void HRTIM_Master_ISR(HRTIM_HandleTypeDef * hhrtim) * @arg HRTIM_TIMERINDEX_TIMER_D for timer D * @arg HRTIM_TIMERINDEX_TIMER_E for timer E * @retval None -*/ -static void HRTIM_Timer_ISR(HRTIM_HandleTypeDef * hhrtim, - uint32_t TimerIdx) + */ +static void HRTIM_Timer_ISR(HRTIM_HandleTypeDef *hhrtim, + uint32_t TimerIdx) { uint32_t tisrflags = READ_REG(hhrtim->Instance->sTimerxRegs[TimerIdx].TIMxISR); uint32_t tdierits = READ_REG(hhrtim->Instance->sTimerxRegs[TimerIdx].TIMxDIER); /* Timer compare 1 event */ - if((uint32_t)(tisrflags & HRTIM_TIM_FLAG_CMP1) != (uint32_t)RESET) + if ((uint32_t)(tisrflags & HRTIM_TIM_FLAG_CMP1) != (uint32_t)RESET) { - if((uint32_t)(tdierits & HRTIM_TIM_IT_CMP1) != (uint32_t)RESET) + if ((uint32_t)(tdierits & HRTIM_TIM_IT_CMP1) != (uint32_t)RESET) { __HAL_HRTIM_TIMER_CLEAR_IT(hhrtim, TimerIdx, HRTIM_TIM_IT_CMP1); @@ -9005,9 +9016,9 @@ static void HRTIM_Timer_ISR(HRTIM_HandleTypeDef * hhrtim, } /* Timer compare 2 event */ - if((uint32_t)(tisrflags & HRTIM_TIM_FLAG_CMP2) != (uint32_t)RESET) + if ((uint32_t)(tisrflags & HRTIM_TIM_FLAG_CMP2) != (uint32_t)RESET) { - if((uint32_t)(tdierits & HRTIM_TIM_IT_CMP2) != (uint32_t)RESET) + if ((uint32_t)(tdierits & HRTIM_TIM_IT_CMP2) != (uint32_t)RESET) { __HAL_HRTIM_TIMER_CLEAR_IT(hhrtim, TimerIdx, HRTIM_TIM_IT_CMP2); @@ -9021,9 +9032,9 @@ static void HRTIM_Timer_ISR(HRTIM_HandleTypeDef * hhrtim, } /* Timer compare 3 event */ - if((uint32_t)(tisrflags & HRTIM_TIM_FLAG_CMP3) != (uint32_t)RESET) + if ((uint32_t)(tisrflags & HRTIM_TIM_FLAG_CMP3) != (uint32_t)RESET) { - if((uint32_t)(tdierits & HRTIM_TIM_IT_CMP3) != (uint32_t)RESET) + if ((uint32_t)(tdierits & HRTIM_TIM_IT_CMP3) != (uint32_t)RESET) { __HAL_HRTIM_TIMER_CLEAR_IT(hhrtim, TimerIdx, HRTIM_TIM_IT_CMP3); @@ -9037,9 +9048,9 @@ static void HRTIM_Timer_ISR(HRTIM_HandleTypeDef * hhrtim, } /* Timer compare 4 event */ - if((uint32_t)(tisrflags & HRTIM_TIM_FLAG_CMP4) != (uint32_t)RESET) + if ((uint32_t)(tisrflags & HRTIM_TIM_FLAG_CMP4) != (uint32_t)RESET) { - if((uint32_t)(tdierits & HRTIM_TIM_IT_CMP4) != (uint32_t)RESET) + if ((uint32_t)(tdierits & HRTIM_TIM_IT_CMP4) != (uint32_t)RESET) { __HAL_HRTIM_TIMER_CLEAR_IT(hhrtim, TimerIdx, HRTIM_TIM_IT_CMP4); @@ -9053,9 +9064,9 @@ static void HRTIM_Timer_ISR(HRTIM_HandleTypeDef * hhrtim, } /* Timer repetition event */ - if((uint32_t)(tisrflags & HRTIM_TIM_FLAG_REP) != (uint32_t)RESET) + if ((uint32_t)(tisrflags & HRTIM_TIM_FLAG_REP) != (uint32_t)RESET) { - if((uint32_t)(tdierits & HRTIM_TIM_IT_REP) != (uint32_t)RESET) + if ((uint32_t)(tdierits & HRTIM_TIM_IT_REP) != (uint32_t)RESET) { __HAL_HRTIM_TIMER_CLEAR_IT(hhrtim, TimerIdx, HRTIM_TIM_IT_REP); @@ -9069,9 +9080,9 @@ static void HRTIM_Timer_ISR(HRTIM_HandleTypeDef * hhrtim, } /* Timer registers update event */ - if((uint32_t)(tisrflags & HRTIM_TIM_FLAG_UPD) != (uint32_t)RESET) + if ((uint32_t)(tisrflags & HRTIM_TIM_FLAG_UPD) != (uint32_t)RESET) { - if((uint32_t)(tdierits & HRTIM_TIM_IT_UPD) != (uint32_t)RESET) + if ((uint32_t)(tdierits & HRTIM_TIM_IT_UPD) != (uint32_t)RESET) { __HAL_HRTIM_TIMER_CLEAR_IT(hhrtim, TimerIdx, HRTIM_TIM_IT_UPD); @@ -9085,9 +9096,9 @@ static void HRTIM_Timer_ISR(HRTIM_HandleTypeDef * hhrtim, } /* Timer capture 1 event */ - if((uint32_t)(tisrflags & HRTIM_TIM_FLAG_CPT1) != (uint32_t)RESET) + if ((uint32_t)(tisrflags & HRTIM_TIM_FLAG_CPT1) != (uint32_t)RESET) { - if((uint32_t)(tdierits & HRTIM_TIM_IT_CPT1) != (uint32_t)RESET) + if ((uint32_t)(tdierits & HRTIM_TIM_IT_CPT1) != (uint32_t)RESET) { __HAL_HRTIM_TIMER_CLEAR_IT(hhrtim, TimerIdx, HRTIM_TIM_IT_CPT1); @@ -9101,9 +9112,9 @@ static void HRTIM_Timer_ISR(HRTIM_HandleTypeDef * hhrtim, } /* Timer capture 2 event */ - if((uint32_t)(tisrflags & HRTIM_TIM_FLAG_CPT2) != (uint32_t)RESET) + if ((uint32_t)(tisrflags & HRTIM_TIM_FLAG_CPT2) != (uint32_t)RESET) { - if((uint32_t)(tdierits & HRTIM_TIM_IT_CPT2) != (uint32_t)RESET) + if ((uint32_t)(tdierits & HRTIM_TIM_IT_CPT2) != (uint32_t)RESET) { __HAL_HRTIM_TIMER_CLEAR_IT(hhrtim, TimerIdx, HRTIM_TIM_IT_CPT2); @@ -9117,9 +9128,9 @@ static void HRTIM_Timer_ISR(HRTIM_HandleTypeDef * hhrtim, } /* Timer output 1 set event */ - if((uint32_t)(tisrflags & HRTIM_TIM_FLAG_SET1) != (uint32_t)RESET) + if ((uint32_t)(tisrflags & HRTIM_TIM_FLAG_SET1) != (uint32_t)RESET) { - if((uint32_t)(tdierits & HRTIM_TIM_IT_SET1) != (uint32_t)RESET) + if ((uint32_t)(tdierits & HRTIM_TIM_IT_SET1) != (uint32_t)RESET) { __HAL_HRTIM_TIMER_CLEAR_IT(hhrtim, TimerIdx, HRTIM_TIM_IT_SET1); @@ -9133,9 +9144,9 @@ static void HRTIM_Timer_ISR(HRTIM_HandleTypeDef * hhrtim, } /* Timer output 1 reset event */ - if((uint32_t)(tisrflags & HRTIM_TIM_FLAG_RST1) != (uint32_t)RESET) + if ((uint32_t)(tisrflags & HRTIM_TIM_FLAG_RST1) != (uint32_t)RESET) { - if((uint32_t)(tdierits & HRTIM_TIM_IT_RST1) != (uint32_t)RESET) + if ((uint32_t)(tdierits & HRTIM_TIM_IT_RST1) != (uint32_t)RESET) { __HAL_HRTIM_TIMER_CLEAR_IT(hhrtim, TimerIdx, HRTIM_TIM_IT_RST1); @@ -9149,9 +9160,9 @@ static void HRTIM_Timer_ISR(HRTIM_HandleTypeDef * hhrtim, } /* Timer output 2 set event */ - if((uint32_t)(tisrflags & HRTIM_TIM_FLAG_SET2) != (uint32_t)RESET) + if ((uint32_t)(tisrflags & HRTIM_TIM_FLAG_SET2) != (uint32_t)RESET) { - if((uint32_t)(tdierits & HRTIM_TIM_IT_SET2) != (uint32_t)RESET) + if ((uint32_t)(tdierits & HRTIM_TIM_IT_SET2) != (uint32_t)RESET) { __HAL_HRTIM_TIMER_CLEAR_IT(hhrtim, TimerIdx, HRTIM_TIM_IT_SET2); @@ -9165,9 +9176,9 @@ static void HRTIM_Timer_ISR(HRTIM_HandleTypeDef * hhrtim, } /* Timer output 2 reset event */ - if((uint32_t)(tisrflags & HRTIM_TIM_FLAG_RST2) != (uint32_t)RESET) + if ((uint32_t)(tisrflags & HRTIM_TIM_FLAG_RST2) != (uint32_t)RESET) { - if((uint32_t)(tdierits & HRTIM_TIM_IT_RST2) != (uint32_t)RESET) + if ((uint32_t)(tdierits & HRTIM_TIM_IT_RST2) != (uint32_t)RESET) { __HAL_HRTIM_TIMER_CLEAR_IT(hhrtim, TimerIdx, HRTIM_TIM_IT_RST2); @@ -9181,9 +9192,9 @@ static void HRTIM_Timer_ISR(HRTIM_HandleTypeDef * hhrtim, } /* Timer reset event */ - if((uint32_t)(tisrflags & HRTIM_TIM_FLAG_RST) != (uint32_t)RESET) + if ((uint32_t)(tisrflags & HRTIM_TIM_FLAG_RST) != (uint32_t)RESET) { - if((uint32_t)(tdierits & HRTIM_TIM_IT_RST) != (uint32_t)RESET) + if ((uint32_t)(tdierits & HRTIM_TIM_IT_RST) != (uint32_t)RESET) { __HAL_HRTIM_TIMER_CLEAR_IT(hhrtim, TimerIdx, HRTIM_TIM_IT_RST); @@ -9197,9 +9208,9 @@ static void HRTIM_Timer_ISR(HRTIM_HandleTypeDef * hhrtim, } /* Delayed protection event */ - if((uint32_t)(tisrflags & HRTIM_TIM_FLAG_DLYPRT) != (uint32_t)RESET) + if ((uint32_t)(tisrflags & HRTIM_TIM_FLAG_DLYPRT) != (uint32_t)RESET) { - if((uint32_t)(tdierits & HRTIM_TIM_IT_DLYPRT) != (uint32_t)RESET) + if ((uint32_t)(tdierits & HRTIM_TIM_IT_DLYPRT) != (uint32_t)RESET) { __HAL_HRTIM_TIMER_CLEAR_IT(hhrtim, TimerIdx, HRTIM_TIM_IT_DLYPRT); @@ -9220,7 +9231,7 @@ static void HRTIM_Timer_ISR(HRTIM_HandleTypeDef * hhrtim, */ static void HRTIM_DMAMasterCplt(DMA_HandleTypeDef *hdma) { - HRTIM_HandleTypeDef * hrtim = (HRTIM_HandleTypeDef *)((DMA_HandleTypeDef* )hdma)->Parent; + HRTIM_HandleTypeDef *hrtim = (HRTIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; if ((hrtim->Instance->sMasterRegs.MDIER & HRTIM_MASTER_DMA_MCMP1) != (uint32_t)RESET) { @@ -9293,11 +9304,11 @@ static void HRTIM_DMATimerxCplt(DMA_HandleTypeDef *hdma) { uint8_t timer_idx; - HRTIM_HandleTypeDef * hrtim = (HRTIM_HandleTypeDef *)((DMA_HandleTypeDef* )hdma)->Parent; + HRTIM_HandleTypeDef *hrtim = (HRTIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; timer_idx = (uint8_t)GetTimerIdxFromDMAHandle(hrtim, hdma); - if ( !IS_HRTIM_TIMING_UNIT(timer_idx) ) {return;} + if (!IS_HRTIM_TIMING_UNIT(timer_idx)) {return;} if ((hrtim->Instance->sTimerxRegs[timer_idx].TIMxDIER & HRTIM_TIM_DMA_CMP1) != (uint32_t)RESET) { @@ -9418,16 +9429,16 @@ static void HRTIM_DMATimerxCplt(DMA_HandleTypeDef *hdma) } /** -* @brief DMA error callback -* @param hdma pointer to DMA handle. -* @retval None -*/ + * @brief DMA error callback + * @param hdma pointer to DMA handle. + * @retval None + */ static void HRTIM_DMAError(DMA_HandleTypeDef *hdma) { - HRTIM_HandleTypeDef * hrtim = (HRTIM_HandleTypeDef *)((DMA_HandleTypeDef* )hdma)->Parent; + HRTIM_HandleTypeDef *hrtim = (HRTIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; #if (USE_HAL_HRTIM_REGISTER_CALLBACKS == 1) - hrtim->ErrorCallback(hrtim); + hrtim->ErrorCallback(hrtim); #else HAL_HRTIM_ErrorCallback(hrtim); #endif /* USE_HAL_HRTIM_REGISTER_CALLBACKS */ @@ -9440,10 +9451,10 @@ static void HRTIM_DMAError(DMA_HandleTypeDef *hdma) */ static void HRTIM_BurstDMACplt(DMA_HandleTypeDef *hdma) { - HRTIM_HandleTypeDef * hrtim = (HRTIM_HandleTypeDef *)((DMA_HandleTypeDef* )hdma)->Parent; + HRTIM_HandleTypeDef *hrtim = (HRTIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; #if (USE_HAL_HRTIM_REGISTER_CALLBACKS == 1) - hrtim->BurstDMATransferCallback(hrtim, GetTimerIdxFromDMAHandle(hrtim, hdma)); + hrtim->BurstDMATransferCallback(hrtim, GetTimerIdxFromDMAHandle(hrtim, hdma)); #else HAL_HRTIM_BurstDMATransferCallback(hrtim, GetTimerIdxFromDMAHandle(hrtim, hdma)); #endif /* USE_HAL_HRTIM_REGISTER_CALLBACKS */ diff --git a/system/Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c b/system/Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c index 7fdfa7389b..9d983bef1d 100644 --- a/system/Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c +++ b/system/Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c @@ -156,7 +156,8 @@ HAL_I2C_Master_Seq_Receive_IT() or using HAL_I2C_Master_Seq_Receive_DMA() (+++) At reception end of current frame transfer, HAL_I2C_MasterRxCpltCallback() is executed and users can add their own code by customization of function pointer HAL_I2C_MasterRxCpltCallback() - (++) Abort a master or memory IT or DMA I2C process communication with Interrupt using HAL_I2C_Master_Abort_IT() + (++) Abort a master or memory IT or DMA I2C process communication with Interrupt + using HAL_I2C_Master_Abort_IT() (+++) End of abort process, HAL_I2C_AbortCpltCallback() is executed and users can add their own code by customization of function pointer HAL_I2C_AbortCpltCallback() (++) Enable/disable the Address listen mode in slave I2C mode using HAL_I2C_EnableListen_IT() @@ -3324,33 +3325,46 @@ HAL_StatusTypeDef HAL_I2C_IsDeviceReady(I2C_HandleTypeDef *hi2c, uint16_t DevAdd /* Wait until STOPF flag is reset */ if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_STOPF, RESET, Timeout, tickstart) != HAL_OK) { - return HAL_ERROR; + /* A non acknowledge appear during STOP Flag waiting process, a new trial must be performed */ + if (hi2c->ErrorCode == HAL_I2C_ERROR_AF) + { + /* Clear STOP Flag */ + __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF); + + /* Reset the error code for next trial */ + hi2c->ErrorCode = HAL_I2C_ERROR_NONE; + } } + else + { + /* A acknowledge appear during STOP Flag waiting process, this mean that device respond to its address */ - /* Clear STOP Flag */ - __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF); + /* Clear STOP Flag */ + __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF); - /* Device is ready */ - hi2c->State = HAL_I2C_STATE_READY; + /* Device is ready */ + hi2c->State = HAL_I2C_STATE_READY; - /* Process Unlocked */ - __HAL_UNLOCK(hi2c); + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); - return HAL_OK; + return HAL_OK; + } } else { - /* Wait until STOPF flag is reset */ - if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_STOPF, RESET, Timeout, tickstart) != HAL_OK) - { - return HAL_ERROR; - } + /* A non acknowledge is detected, this mean that device not respond to its address, + a new trial must be performed */ /* Clear NACK Flag */ __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF); - /* Clear STOP Flag, auto generated with autoend*/ - __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF); + /* Wait until STOPF flag is reset */ + if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_STOPF, RESET, Timeout, tickstart) == HAL_OK) + { + /* Clear STOP Flag, auto generated with autoend*/ + __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF); + } } /* Increment Trials */ @@ -4577,9 +4591,6 @@ HAL_StatusTypeDef HAL_I2C_Master_Abort_IT(I2C_HandleTypeDef *hi2c, uint16_t DevA if ((tmp_mode == HAL_I2C_MODE_MASTER) || (tmp_mode == HAL_I2C_MODE_MEM)) { - /* Process Locked */ - __HAL_LOCK(hi2c); - /* Disable Interrupts and Store Previous state */ if (hi2c->State == HAL_I2C_STATE_BUSY_TX) { @@ -4603,9 +4614,6 @@ HAL_StatusTypeDef HAL_I2C_Master_Abort_IT(I2C_HandleTypeDef *hi2c, uint16_t DevA /* Set AUTOEND mode, this will generate a NACK then STOP condition to abort the current transfer */ I2C_TransferConfig(hi2c, DevAddress, 1, I2C_AUTOEND_MODE, I2C_GENERATE_STOP); - /* Process Unlocked */ - __HAL_UNLOCK(hi2c); - /* Note : The I2C interrupts must be enabled after unlocking current process to avoid the risk of I2C interrupt handle execution before current process unlock */ @@ -6052,16 +6060,20 @@ static void I2C_ITAddrCplt(I2C_HandleTypeDef *hi2c, uint32_t ITFlags) static void I2C_ITMasterSeqCplt(I2C_HandleTypeDef *hi2c) { /* Reset I2C handle mode */ - hi2c->Mode = HAL_I2C_MODE_NONE; - + if (I2C_GET_STOP_MODE(hi2c) == I2C_AUTOEND_MODE) + { + hi2c->Mode = HAL_I2C_MODE_NONE; + } /* No Generate Stop, to permit restart mode */ /* The stop will be done at the end of transfer, when I2C_AUTOEND_MODE enable */ if (hi2c->State == HAL_I2C_STATE_BUSY_TX) { hi2c->State = HAL_I2C_STATE_READY; hi2c->PreviousState = I2C_STATE_MASTER_BUSY_TX; - hi2c->XferISR = NULL; - + if (I2C_GET_STOP_MODE(hi2c) == I2C_AUTOEND_MODE) + { + hi2c->XferISR = NULL; + } /* Disable Interrupts */ I2C_Disable_IRQ(hi2c, I2C_XFER_TX_IT); @@ -6080,7 +6092,10 @@ static void I2C_ITMasterSeqCplt(I2C_HandleTypeDef *hi2c) { hi2c->State = HAL_I2C_STATE_READY; hi2c->PreviousState = I2C_STATE_MASTER_BUSY_RX; - hi2c->XferISR = NULL; + if (I2C_GET_STOP_MODE(hi2c) == I2C_AUTOEND_MODE) + { + hi2c->XferISR = NULL; + } /* Disable Interrupts */ I2C_Disable_IRQ(hi2c, I2C_XFER_RX_IT); @@ -6397,7 +6412,7 @@ static void I2C_ITSlaveCplt(I2C_HandleTypeDef *hi2c, uint32_t ITFlags) /* Increment Buffer pointer */ hi2c->pBuffPtr++; - if ((hi2c->XferSize > 0U)) + if (hi2c->XferSize > 0U) { hi2c->XferSize--; hi2c->XferCount--; @@ -6553,7 +6568,7 @@ static void I2C_ITListenCplt(I2C_HandleTypeDef *hi2c, uint32_t ITFlags) /* Increment Buffer pointer */ hi2c->pBuffPtr++; - if ((hi2c->XferSize > 0U)) + if (hi2c->XferSize > 0U) { hi2c->XferSize--; hi2c->XferCount--; @@ -7009,7 +7024,7 @@ static HAL_StatusTypeDef I2C_WaitOnFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uin { if (((HAL_GetTick() - Tickstart) > Timeout) || (Timeout == 0U)) { - if ((__HAL_I2C_GET_FLAG(hi2c, Flag) == Status)) + if (__HAL_I2C_GET_FLAG(hi2c, Flag) == Status) { hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT; hi2c->State = HAL_I2C_STATE_READY; @@ -7049,7 +7064,7 @@ static HAL_StatusTypeDef I2C_WaitOnTXISFlagUntilTimeout(I2C_HandleTypeDef *hi2c, { if (((HAL_GetTick() - Tickstart) > Timeout) || (Timeout == 0U)) { - if ((__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_TXIS) == RESET)) + if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_TXIS) == RESET) { hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT; hi2c->State = HAL_I2C_STATE_READY; @@ -7088,7 +7103,7 @@ static HAL_StatusTypeDef I2C_WaitOnSTOPFlagUntilTimeout(I2C_HandleTypeDef *hi2c, /* Check for the Timeout */ if (((HAL_GetTick() - Tickstart) > Timeout) || (Timeout == 0U)) { - if ((__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_STOPF) == RESET)) + if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_STOPF) == RESET) { hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT; hi2c->State = HAL_I2C_STATE_READY; @@ -7166,7 +7181,7 @@ static HAL_StatusTypeDef I2C_WaitOnRXNEFlagUntilTimeout(I2C_HandleTypeDef *hi2c, /* Check for the Timeout */ if ((((HAL_GetTick() - Tickstart) > Timeout) || (Timeout == 0U)) && (status == HAL_OK)) { - if ((__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_RXNE) == RESET)) + if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_RXNE) == RESET) { hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT; hi2c->State = HAL_I2C_STATE_READY; @@ -7333,15 +7348,17 @@ static HAL_StatusTypeDef I2C_IsErrorOccurred(I2C_HandleTypeDef *hi2c, uint32_t T static void I2C_TransferConfig(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t Size, uint32_t Mode, uint32_t Request) { + uint32_t tmp; + /* Check the parameters */ assert_param(IS_I2C_ALL_INSTANCE(hi2c->Instance)); assert_param(IS_TRANSFER_MODE(Mode)); assert_param(IS_TRANSFER_REQUEST(Request)); /* Declaration of tmp to prevent undefined behavior of volatile usage */ - uint32_t tmp = ((uint32_t)(((uint32_t)DevAddress & I2C_CR2_SADD) | \ - (((uint32_t)Size << I2C_CR2_NBYTES_Pos) & I2C_CR2_NBYTES) | \ - (uint32_t)Mode | (uint32_t)Request) & (~0x80000000U)); + tmp = ((uint32_t)(((uint32_t)DevAddress & I2C_CR2_SADD) | \ + (((uint32_t)Size << I2C_CR2_NBYTES_Pos) & I2C_CR2_NBYTES) | \ + (uint32_t)Mode | (uint32_t)Request) & (~0x80000000U)); /* update CR2 register */ MODIFY_REG(hi2c->Instance->CR2, \ diff --git a/system/Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2s.c b/system/Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2s.c index d754bbad9b..956c6079cd 100644 --- a/system/Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2s.c +++ b/system/Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2s.c @@ -1793,7 +1793,7 @@ __weak void HAL_I2S_ErrorCallback(I2S_HandleTypeDef *hi2s) * the configuration information for I2S module * @retval HAL state */ -HAL_I2S_StateTypeDef HAL_I2S_GetState(I2S_HandleTypeDef *hi2s) +HAL_I2S_StateTypeDef HAL_I2S_GetState(const I2S_HandleTypeDef *hi2s) { return hi2s->State; } @@ -1804,7 +1804,7 @@ HAL_I2S_StateTypeDef HAL_I2S_GetState(I2S_HandleTypeDef *hi2s) * the configuration information for I2S module * @retval I2S Error Code */ -uint32_t HAL_I2S_GetError(I2S_HandleTypeDef *hi2s) +uint32_t HAL_I2S_GetError(const I2S_HandleTypeDef *hi2s) { return hi2s->ErrorCode; } diff --git a/system/Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2s_ex.c b/system/Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2s_ex.c index 39f3767ac0..2643472ce4 100644 --- a/system/Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2s_ex.c +++ b/system/Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2s_ex.c @@ -197,7 +197,7 @@ static HAL_StatusTypeDef I2SEx_FullDuplexWaitFlagStateUntilTimeout(I2S_HandleTyp * @note When a 16-bit data frame or a 16-bit data frame extended is selected during the I2S * configuration phase, the Size parameter means the number of 16-bit data length * in the transaction and when a 24-bit data frame or a 32-bit data frame is selected - * the Size parameter means the number of 16-bit data length. + * the Size parameter means the number of 24-bit or 32-bit data length. * @param Timeout Timeout duration * @note The I2S is kept enabled at the end of transaction to avoid the clock de-synchronization * between Master and Slave(example: audio streaming). @@ -228,7 +228,7 @@ HAL_StatusTypeDef HAL_I2SEx_TransmitReceive(I2S_HandleTypeDef *hi2s, /* Check the Data format: When a 16-bit data frame or a 16-bit data frame extended is selected during the I2S configuration phase, the Size parameter means the number of 16-bit data length in the transaction and when a 24-bit data frame or a 32-bit data - frame is selected the Size parameter means the number of 16-bit data length. */ + frame is selected the Size parameter means the number of 24-bit or 32-bit data length. */ if ((tmp1 == I2S_DATAFORMAT_24B) || (tmp1 == I2S_DATAFORMAT_32B)) { hi2s->TxXferSize = (Size << 1U); @@ -431,7 +431,7 @@ HAL_StatusTypeDef HAL_I2SEx_TransmitReceive(I2S_HandleTypeDef *hi2s, * @note When a 16-bit data frame or a 16-bit data frame extended is selected during the I2S * configuration phase, the Size parameter means the number of 16-bit data length * in the transaction and when a 24-bit data frame or a 32-bit data frame is selected - * the Size parameter means the number of 16-bit data length. + * the Size parameter means the number of 24-bit or 32-bit data length. * @note The I2S is kept enabled at the end of transaction to avoid the clock de-synchronization * between Master and Slave(example: audio streaming). * @retval HAL status @@ -463,7 +463,7 @@ HAL_StatusTypeDef HAL_I2SEx_TransmitReceive_IT(I2S_HandleTypeDef *hi2s, /* Check the Data format: When a 16-bit data frame or a 16-bit data frame extended is selected during the I2S configuration phase, the Size parameter means the number of 16-bit data length in the transaction and when a 24-bit data frame or a 32-bit data - frame is selected the Size parameter means the number of 16-bit data length. */ + frame is selected the Size parameter means the number of 24-bit or 32-bit data length. */ if ((tmp1 == I2S_DATAFORMAT_24B) || (tmp1 == I2S_DATAFORMAT_32B)) { hi2s->TxXferSize = (Size << 1U); @@ -540,7 +540,7 @@ HAL_StatusTypeDef HAL_I2SEx_TransmitReceive_IT(I2S_HandleTypeDef *hi2s, * @note When a 16-bit data frame or a 16-bit data frame extended is selected during the I2S * configuration phase, the Size parameter means the number of 16-bit data length * in the transaction and when a 24-bit data frame or a 32-bit data frame is selected - * the Size parameter means the number of 16-bit data length. + * the Size parameter means the number of 24-bit or 32-bit data length. * @note The I2S is kept enabled at the end of transaction to avoid the clock de-synchronization * between Master and Slave(example: audio streaming). * @retval HAL status @@ -552,6 +552,7 @@ HAL_StatusTypeDef HAL_I2SEx_TransmitReceive_DMA(I2S_HandleTypeDef *hi2s, { uint32_t *tmp = NULL; uint32_t tmp1 = 0U; + HAL_StatusTypeDef status; if (hi2s->State != HAL_I2S_STATE_READY) { @@ -573,7 +574,7 @@ HAL_StatusTypeDef HAL_I2SEx_TransmitReceive_DMA(I2S_HandleTypeDef *hi2s, /* Check the Data format: When a 16-bit data frame or a 16-bit data frame extended is selected during the I2S configuration phase, the Size parameter means the number of 16-bit data length in the transaction and when a 24-bit data frame or a 32-bit data - frame is selected the Size parameter means the number of 16-bit data length. */ + frame is selected the Size parameter means the number of 24-bit or 32-bit data length. */ if ((tmp1 == I2S_DATAFORMAT_24B) || (tmp1 == I2S_DATAFORMAT_32B)) { hi2s->TxXferSize = (Size << 1U); @@ -616,14 +617,14 @@ HAL_StatusTypeDef HAL_I2SEx_TransmitReceive_DMA(I2S_HandleTypeDef *hi2s, { /* Enable the Rx DMA Stream */ tmp = (uint32_t *)&pRxData; - HAL_DMA_Start_IT(hi2s->hdmarx, (uint32_t)&I2SxEXT(hi2s->Instance)->DR, *(uint32_t *)tmp, hi2s->RxXferSize); + status = HAL_DMA_Start_IT(hi2s->hdmarx, (uint32_t)&I2SxEXT(hi2s->Instance)->DR, *(uint32_t *)tmp, hi2s->RxXferSize); /* Enable Rx DMA Request */ SET_BIT(I2SxEXT(hi2s->Instance)->CR2, SPI_CR2_RXDMAEN); /* Enable the Tx DMA Stream */ tmp = (uint32_t *)&pTxData; - HAL_DMA_Start_IT(hi2s->hdmatx, *(uint32_t *)tmp, (uint32_t)&hi2s->Instance->DR, hi2s->TxXferSize); + status = HAL_DMA_Start_IT(hi2s->hdmatx, *(uint32_t *)tmp, (uint32_t)&hi2s->Instance->DR, hi2s->TxXferSize); /* Enable Tx DMA Request */ SET_BIT(hi2s->Instance->CR2, SPI_CR2_TXDMAEN); @@ -639,14 +640,14 @@ HAL_StatusTypeDef HAL_I2SEx_TransmitReceive_DMA(I2S_HandleTypeDef *hi2s, } /* Enable the Tx DMA Stream */ tmp = (uint32_t *)&pTxData; - HAL_DMA_Start_IT(hi2s->hdmatx, *(uint32_t *)tmp, (uint32_t)&I2SxEXT(hi2s->Instance)->DR, hi2s->TxXferSize); + status = HAL_DMA_Start_IT(hi2s->hdmatx, *(uint32_t *)tmp, (uint32_t)&I2SxEXT(hi2s->Instance)->DR, hi2s->TxXferSize); /* Enable Tx DMA Request */ SET_BIT(I2SxEXT(hi2s->Instance)->CR2, SPI_CR2_TXDMAEN); /* Enable the Rx DMA Stream */ tmp = (uint32_t *)&pRxData; - HAL_DMA_Start_IT(hi2s->hdmarx, (uint32_t)&hi2s->Instance->DR, *(uint32_t *)tmp, hi2s->RxXferSize); + status = HAL_DMA_Start_IT(hi2s->hdmarx, (uint32_t)&hi2s->Instance->DR, *(uint32_t *)tmp, hi2s->RxXferSize); /* Enable Rx DMA Request */ SET_BIT(hi2s->Instance->CR2, SPI_CR2_RXDMAEN); @@ -662,7 +663,7 @@ HAL_StatusTypeDef HAL_I2SEx_TransmitReceive_DMA(I2S_HandleTypeDef *hi2s, __HAL_I2S_ENABLE(hi2s); } - return HAL_OK; + return status; } /** diff --git a/system/Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_nand.c b/system/Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_nand.c index f40f74f6fe..46c74c69e2 100644 --- a/system/Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_nand.c +++ b/system/Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_nand.c @@ -507,7 +507,7 @@ HAL_StatusTypeDef HAL_NAND_Reset(NAND_HandleTypeDef *hnand) * @param pDeviceConfig pointer to NAND_DeviceConfigTypeDef structure * @retval HAL status */ -HAL_StatusTypeDef HAL_NAND_ConfigDevice(NAND_HandleTypeDef *hnand, NAND_DeviceConfigTypeDef *pDeviceConfig) +HAL_StatusTypeDef HAL_NAND_ConfigDevice(NAND_HandleTypeDef *hnand, const NAND_DeviceConfigTypeDef *pDeviceConfig) { hnand->Config.PageSize = pDeviceConfig->PageSize; hnand->Config.SpareAreaSize = pDeviceConfig->SpareAreaSize; @@ -535,9 +535,9 @@ HAL_StatusTypeDef HAL_NAND_Read_Page_8b(NAND_HandleTypeDef *hnand, const NAND_Ad uint32_t index; uint32_t tickstart; uint32_t deviceaddress; - uint32_t numpagesread = 0U; uint32_t nandaddress; uint32_t nbpages = NumPageToRead; + uint32_t status; uint8_t *buff = pBuffer; /* Check the NAND controller state */ @@ -635,9 +635,11 @@ HAL_StatusTypeDef HAL_NAND_Read_Page_8b(NAND_HandleTypeDef *hnand, const NAND_Ad tickstart = HAL_GetTick(); /* Read status until NAND is ready */ - while (HAL_NAND_Read_Status(hnand) != NAND_READY) + do { - if ((HAL_GetTick() - tickstart) > NAND_WRITE_TIMEOUT) + status = HAL_NAND_Read_Status(hnand); + + if (status == NAND_ERROR) { /* Update the NAND controller state */ hnand->State = HAL_NAND_STATE_ERROR; @@ -645,9 +647,28 @@ HAL_StatusTypeDef HAL_NAND_Read_Page_8b(NAND_HandleTypeDef *hnand, const NAND_Ad /* Process unlocked */ __HAL_UNLOCK(hnand); - return HAL_TIMEOUT; + return HAL_ERROR; } - } + + if ((HAL_GetTick() - tickstart) > NAND_WRITE_TIMEOUT) + { + /* Perform a new read status to check if NAND is now ready */ + if (HAL_NAND_Read_Status(hnand) == NAND_READY) + { + break; + } + else + { + /* Update the NAND controller state */ + hnand->State = HAL_NAND_STATE_ERROR; + + /* Process unlocked */ + __HAL_UNLOCK(hnand); + + return HAL_TIMEOUT; + } + } + } while (status != NAND_READY); /* Go back to read mode */ *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = ((uint8_t)0x00); @@ -657,13 +678,10 @@ HAL_StatusTypeDef HAL_NAND_Read_Page_8b(NAND_HandleTypeDef *hnand, const NAND_Ad /* Get Data into Buffer */ for (index = 0U; index < hnand->Config.PageSize; index++) { - *buff = *(uint8_t *)deviceaddress; + *buff = *(__IO uint8_t *)deviceaddress; buff++; } - /* Increment read pages number */ - numpagesread++; - /* Decrement pages to read */ nbpages--; @@ -700,9 +718,9 @@ HAL_StatusTypeDef HAL_NAND_Read_Page_16b(NAND_HandleTypeDef *hnand, const NAND_A uint32_t index; uint32_t tickstart; uint32_t deviceaddress; - uint32_t numpagesread = 0U; uint32_t nandaddress; uint32_t nbpages = NumPageToRead; + uint32_t status; uint16_t *buff = pBuffer; /* Check the NAND controller state */ @@ -799,9 +817,11 @@ HAL_StatusTypeDef HAL_NAND_Read_Page_16b(NAND_HandleTypeDef *hnand, const NAND_A tickstart = HAL_GetTick(); /* Read status until NAND is ready */ - while (HAL_NAND_Read_Status(hnand) != NAND_READY) + do { - if ((HAL_GetTick() - tickstart) > NAND_WRITE_TIMEOUT) + status = HAL_NAND_Read_Status(hnand); + + if (status == NAND_ERROR) { /* Update the NAND controller state */ hnand->State = HAL_NAND_STATE_ERROR; @@ -809,9 +829,28 @@ HAL_StatusTypeDef HAL_NAND_Read_Page_16b(NAND_HandleTypeDef *hnand, const NAND_A /* Process unlocked */ __HAL_UNLOCK(hnand); - return HAL_TIMEOUT; + return HAL_ERROR; } - } + + if ((HAL_GetTick() - tickstart) > NAND_WRITE_TIMEOUT) + { + /* Perform a new read status to check if NAND is now ready */ + if (HAL_NAND_Read_Status(hnand) == NAND_READY) + { + break; + } + else + { + /* Update the NAND controller state */ + hnand->State = HAL_NAND_STATE_ERROR; + + /* Process unlocked */ + __HAL_UNLOCK(hnand); + + return HAL_TIMEOUT; + } + } + } while (status != NAND_READY); /* Go back to read mode */ *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = ((uint8_t)0x00); @@ -832,13 +871,10 @@ HAL_StatusTypeDef HAL_NAND_Read_Page_16b(NAND_HandleTypeDef *hnand, const NAND_A /* Get Data into Buffer */ for (index = 0U; index < hnand->Config.PageSize; index++) { - *buff = *(uint16_t *)deviceaddress; + *buff = *(__IO uint16_t *)deviceaddress; buff++; } - /* Increment read pages number */ - numpagesread++; - /* Decrement pages to read */ nbpages--; @@ -875,9 +911,9 @@ HAL_StatusTypeDef HAL_NAND_Write_Page_8b(NAND_HandleTypeDef *hnand, const NAND_A uint32_t index; uint32_t tickstart; uint32_t deviceaddress; - uint32_t numpageswritten = 0U; uint32_t nandaddress; uint32_t nbpages = NumPageToWrite; + uint32_t status; const uint8_t *buff = pBuffer; /* Check the NAND controller state */ @@ -982,9 +1018,11 @@ HAL_StatusTypeDef HAL_NAND_Write_Page_8b(NAND_HandleTypeDef *hnand, const NAND_A tickstart = HAL_GetTick(); /* Read status until NAND is ready */ - while (HAL_NAND_Read_Status(hnand) != NAND_READY) + do { - if ((HAL_GetTick() - tickstart) > NAND_WRITE_TIMEOUT) + status = HAL_NAND_Read_Status(hnand); + + if (status == NAND_ERROR) { /* Update the NAND controller state */ hnand->State = HAL_NAND_STATE_ERROR; @@ -992,12 +1030,28 @@ HAL_StatusTypeDef HAL_NAND_Write_Page_8b(NAND_HandleTypeDef *hnand, const NAND_A /* Process unlocked */ __HAL_UNLOCK(hnand); - return HAL_TIMEOUT; + return HAL_ERROR; } - } - /* Increment written pages number */ - numpageswritten++; + if ((HAL_GetTick() - tickstart) > NAND_WRITE_TIMEOUT) + { + /* Perform a new read status to check if NAND is now ready */ + if (HAL_NAND_Read_Status(hnand) == NAND_READY) + { + break; + } + else + { + /* Update the NAND controller state */ + hnand->State = HAL_NAND_STATE_ERROR; + + /* Process unlocked */ + __HAL_UNLOCK(hnand); + + return HAL_TIMEOUT; + } + } + } while (status != NAND_READY); /* Decrement pages to write */ nbpages--; @@ -1035,9 +1089,9 @@ HAL_StatusTypeDef HAL_NAND_Write_Page_16b(NAND_HandleTypeDef *hnand, const NAND_ uint32_t index; uint32_t tickstart; uint32_t deviceaddress; - uint32_t numpageswritten = 0U; uint32_t nandaddress; uint32_t nbpages = NumPageToWrite; + uint32_t status; const uint16_t *buff = pBuffer; /* Check the NAND controller state */ @@ -1153,9 +1207,11 @@ HAL_StatusTypeDef HAL_NAND_Write_Page_16b(NAND_HandleTypeDef *hnand, const NAND_ tickstart = HAL_GetTick(); /* Read status until NAND is ready */ - while (HAL_NAND_Read_Status(hnand) != NAND_READY) + do { - if ((HAL_GetTick() - tickstart) > NAND_WRITE_TIMEOUT) + status = HAL_NAND_Read_Status(hnand); + + if (status == NAND_ERROR) { /* Update the NAND controller state */ hnand->State = HAL_NAND_STATE_ERROR; @@ -1163,12 +1219,28 @@ HAL_StatusTypeDef HAL_NAND_Write_Page_16b(NAND_HandleTypeDef *hnand, const NAND_ /* Process unlocked */ __HAL_UNLOCK(hnand); - return HAL_TIMEOUT; + return HAL_ERROR; } - } - /* Increment written pages number */ - numpageswritten++; + if ((HAL_GetTick() - tickstart) > NAND_WRITE_TIMEOUT) + { + /* Perform a new read status to check if NAND is now ready */ + if (HAL_NAND_Read_Status(hnand) == NAND_READY) + { + break; + } + else + { + /* Update the NAND controller state */ + hnand->State = HAL_NAND_STATE_ERROR; + + /* Process unlocked */ + __HAL_UNLOCK(hnand); + + return HAL_TIMEOUT; + } + } + } while (status != NAND_READY); /* Decrement pages to write */ nbpages--; @@ -1206,10 +1278,10 @@ HAL_StatusTypeDef HAL_NAND_Read_SpareArea_8b(NAND_HandleTypeDef *hnand, const NA uint32_t index; uint32_t tickstart; uint32_t deviceaddress; - uint32_t numsparearearead = 0U; uint32_t nandaddress; uint32_t columnaddress; uint32_t nbspare = NumSpareAreaToRead; + uint32_t status; uint8_t *buff = pBuffer; /* Check the NAND controller state */ @@ -1313,9 +1385,11 @@ HAL_StatusTypeDef HAL_NAND_Read_SpareArea_8b(NAND_HandleTypeDef *hnand, const NA tickstart = HAL_GetTick(); /* Read status until NAND is ready */ - while (HAL_NAND_Read_Status(hnand) != NAND_READY) + do { - if ((HAL_GetTick() - tickstart) > NAND_WRITE_TIMEOUT) + status = HAL_NAND_Read_Status(hnand); + + if (status == NAND_ERROR) { /* Update the NAND controller state */ hnand->State = HAL_NAND_STATE_ERROR; @@ -1323,9 +1397,28 @@ HAL_StatusTypeDef HAL_NAND_Read_SpareArea_8b(NAND_HandleTypeDef *hnand, const NA /* Process unlocked */ __HAL_UNLOCK(hnand); - return HAL_TIMEOUT; + return HAL_ERROR; } - } + + if ((HAL_GetTick() - tickstart) > NAND_WRITE_TIMEOUT) + { + /* Perform a new read status to check if NAND is now ready */ + if (HAL_NAND_Read_Status(hnand) == NAND_READY) + { + break; + } + else + { + /* Update the NAND controller state */ + hnand->State = HAL_NAND_STATE_ERROR; + + /* Process unlocked */ + __HAL_UNLOCK(hnand); + + return HAL_TIMEOUT; + } + } + } while (status != NAND_READY); /* Go back to read mode */ *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = ((uint8_t)0x00); @@ -1335,13 +1428,10 @@ HAL_StatusTypeDef HAL_NAND_Read_SpareArea_8b(NAND_HandleTypeDef *hnand, const NA /* Get Data into Buffer */ for (index = 0U; index < hnand->Config.SpareAreaSize; index++) { - *buff = *(uint8_t *)deviceaddress; + *buff = *(__IO uint8_t *)deviceaddress; buff++; } - /* Increment read spare areas number */ - numsparearearead++; - /* Decrement spare areas to read */ nbspare--; @@ -1378,10 +1468,10 @@ HAL_StatusTypeDef HAL_NAND_Read_SpareArea_16b(NAND_HandleTypeDef *hnand, const N uint32_t index; uint32_t tickstart; uint32_t deviceaddress; - uint32_t numsparearearead = 0U; uint32_t nandaddress; uint32_t columnaddress; uint32_t nbspare = NumSpareAreaToRead; + uint32_t status; uint16_t *buff = pBuffer; /* Check the NAND controller state */ @@ -1485,9 +1575,11 @@ HAL_StatusTypeDef HAL_NAND_Read_SpareArea_16b(NAND_HandleTypeDef *hnand, const N tickstart = HAL_GetTick(); /* Read status until NAND is ready */ - while (HAL_NAND_Read_Status(hnand) != NAND_READY) + do { - if ((HAL_GetTick() - tickstart) > NAND_WRITE_TIMEOUT) + status = HAL_NAND_Read_Status(hnand); + + if (status == NAND_ERROR) { /* Update the NAND controller state */ hnand->State = HAL_NAND_STATE_ERROR; @@ -1495,9 +1587,28 @@ HAL_StatusTypeDef HAL_NAND_Read_SpareArea_16b(NAND_HandleTypeDef *hnand, const N /* Process unlocked */ __HAL_UNLOCK(hnand); - return HAL_TIMEOUT; + return HAL_ERROR; } - } + + if ((HAL_GetTick() - tickstart) > NAND_WRITE_TIMEOUT) + { + /* Perform a new read status to check if NAND is now ready */ + if (HAL_NAND_Read_Status(hnand) == NAND_READY) + { + break; + } + else + { + /* Update the NAND controller state */ + hnand->State = HAL_NAND_STATE_ERROR; + + /* Process unlocked */ + __HAL_UNLOCK(hnand); + + return HAL_TIMEOUT; + } + } + } while (status != NAND_READY); /* Go back to read mode */ *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = ((uint8_t)0x00); @@ -1507,13 +1618,10 @@ HAL_StatusTypeDef HAL_NAND_Read_SpareArea_16b(NAND_HandleTypeDef *hnand, const N /* Get Data into Buffer */ for (index = 0U; index < hnand->Config.SpareAreaSize; index++) { - *buff = *(uint16_t *)deviceaddress; + *buff = *(__IO uint16_t *)deviceaddress; buff++; } - /* Increment read spare areas number */ - numsparearearead++; - /* Decrement spare areas to read */ nbspare--; @@ -1550,10 +1658,10 @@ HAL_StatusTypeDef HAL_NAND_Write_SpareArea_8b(NAND_HandleTypeDef *hnand, const N uint32_t index; uint32_t tickstart; uint32_t deviceaddress; - uint32_t numspareareawritten = 0U; uint32_t nandaddress; uint32_t columnaddress; uint32_t nbspare = NumSpareAreaTowrite; + uint32_t status; const uint8_t *buff = pBuffer; /* Check the NAND controller state */ @@ -1667,9 +1775,11 @@ HAL_StatusTypeDef HAL_NAND_Write_SpareArea_8b(NAND_HandleTypeDef *hnand, const N tickstart = HAL_GetTick(); /* Read status until NAND is ready */ - while (HAL_NAND_Read_Status(hnand) != NAND_READY) + do { - if ((HAL_GetTick() - tickstart) > NAND_WRITE_TIMEOUT) + status = HAL_NAND_Read_Status(hnand); + + if (status == NAND_ERROR) { /* Update the NAND controller state */ hnand->State = HAL_NAND_STATE_ERROR; @@ -1677,12 +1787,28 @@ HAL_StatusTypeDef HAL_NAND_Write_SpareArea_8b(NAND_HandleTypeDef *hnand, const N /* Process unlocked */ __HAL_UNLOCK(hnand); - return HAL_TIMEOUT; + return HAL_ERROR; } - } - /* Increment written spare areas number */ - numspareareawritten++; + if ((HAL_GetTick() - tickstart) > NAND_WRITE_TIMEOUT) + { + /* Perform a new read status to check if NAND is now ready */ + if (HAL_NAND_Read_Status(hnand) == NAND_READY) + { + break; + } + else + { + /* Update the NAND controller state */ + hnand->State = HAL_NAND_STATE_ERROR; + + /* Process unlocked */ + __HAL_UNLOCK(hnand); + + return HAL_TIMEOUT; + } + } + } while (status != NAND_READY); /* Decrement spare areas to write */ nbspare--; @@ -1720,10 +1846,10 @@ HAL_StatusTypeDef HAL_NAND_Write_SpareArea_16b(NAND_HandleTypeDef *hnand, const uint32_t index; uint32_t tickstart; uint32_t deviceaddress; - uint32_t numspareareawritten = 0U; uint32_t nandaddress; uint32_t columnaddress; uint32_t nbspare = NumSpareAreaTowrite; + uint32_t status; const uint16_t *buff = pBuffer; /* Check the NAND controller state */ @@ -1837,9 +1963,11 @@ HAL_StatusTypeDef HAL_NAND_Write_SpareArea_16b(NAND_HandleTypeDef *hnand, const tickstart = HAL_GetTick(); /* Read status until NAND is ready */ - while (HAL_NAND_Read_Status(hnand) != NAND_READY) + do { - if ((HAL_GetTick() - tickstart) > NAND_WRITE_TIMEOUT) + status = HAL_NAND_Read_Status(hnand); + + if (status == NAND_ERROR) { /* Update the NAND controller state */ hnand->State = HAL_NAND_STATE_ERROR; @@ -1847,12 +1975,28 @@ HAL_StatusTypeDef HAL_NAND_Write_SpareArea_16b(NAND_HandleTypeDef *hnand, const /* Process unlocked */ __HAL_UNLOCK(hnand); - return HAL_TIMEOUT; + return HAL_ERROR; } - } - /* Increment written spare areas number */ - numspareareawritten++; + if ((HAL_GetTick() - tickstart) > NAND_WRITE_TIMEOUT) + { + /* Perform a new read status to check if NAND is now ready */ + if (HAL_NAND_Read_Status(hnand) == NAND_READY) + { + break; + } + else + { + /* Update the NAND controller state */ + hnand->State = HAL_NAND_STATE_ERROR; + + /* Process unlocked */ + __HAL_UNLOCK(hnand); + + return HAL_TIMEOUT; + } + } + } while (status != NAND_READY); /* Decrement spare areas to write */ nbspare--; diff --git a/system/Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_nor.c b/system/Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_nor.c index 87af606d24..2030b58beb 100644 --- a/system/Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_nor.c +++ b/system/Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_nor.c @@ -24,7 +24,7 @@ [..] This driver is a generic layered driver which contains a set of APIs used to control NOR flash memories. It uses the FMC layer functions to interface - with NOR devices. This driver is used as follows: + with NOR 16-bit devices. The NOR 8-bit support is deprecated. This driver is used as follows: (+) NOR flash memory configuration sequence using the function HAL_NOR_Init() with control and timing parameters for both normal and extended mode. @@ -127,11 +127,6 @@ */ /* Constants to define address to set to write a command */ -#define NOR_CMD_ADDRESS_FIRST_BYTE (uint16_t)0x0AAA -#define NOR_CMD_ADDRESS_FIRST_CFI_BYTE (uint16_t)0x00AA -#define NOR_CMD_ADDRESS_SECOND_BYTE (uint16_t)0x0555 -#define NOR_CMD_ADDRESS_THIRD_BYTE (uint16_t)0x0AAA - #define NOR_CMD_ADDRESS_FIRST (uint16_t)0x0555 #define NOR_CMD_ADDRESS_FIRST_CFI (uint16_t)0x0055 #define NOR_CMD_ADDRESS_SECOND (uint16_t)0x02AA @@ -196,8 +191,6 @@ * @{ */ -static uint32_t uwNORMemoryDataWidth = NOR_MEMORY_8B; - /** * @} */ @@ -243,6 +236,12 @@ HAL_StatusTypeDef HAL_NOR_Init(NOR_HandleTypeDef *hnor, FMC_NORSRAM_TimingTypeDe return HAL_ERROR; } + /* Check if deprecated 8-bit support is used */ + if (hnor->Init.MemoryDataWidth == FMC_NORSRAM_MEM_BUS_WIDTH_8) + { + return HAL_ERROR; + } + if (hnor->State == HAL_NOR_STATE_RESET) { /* Allocate lock resource and initialize it */ @@ -275,16 +274,6 @@ HAL_StatusTypeDef HAL_NOR_Init(NOR_HandleTypeDef *hnor, FMC_NORSRAM_TimingTypeDe /* Enable the NORSRAM device */ __FMC_NORSRAM_ENABLE(hnor->Instance, hnor->Init.NSBank); - /* Initialize NOR Memory Data Width*/ - if (hnor->Init.MemoryDataWidth == FMC_NORSRAM_MEM_BUS_WIDTH_8) - { - uwNORMemoryDataWidth = NOR_MEMORY_8B; - } - else - { - uwNORMemoryDataWidth = NOR_MEMORY_16B; - } - /* Initialize the NOR controller state */ hnor->State = HAL_NOR_STATE_READY; @@ -316,17 +305,9 @@ HAL_StatusTypeDef HAL_NOR_Init(NOR_HandleTypeDef *hnor, FMC_NORSRAM_TimingTypeDe else { /* Get the value of the command set */ - if (uwNORMemoryDataWidth == NOR_MEMORY_8B) - { - NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_FIRST_CFI_BYTE), - NOR_CMD_DATA_CFI); - } - else - { - NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_FIRST_CFI), NOR_CMD_DATA_CFI); - } + NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, NOR_MEMORY_16B, NOR_CMD_ADDRESS_FIRST_CFI), NOR_CMD_DATA_CFI); - hnor->CommandSet = *(__IO uint16_t *) NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_ADDRESS_COMMAND_SET); + hnor->CommandSet = *(__IO uint16_t *) NOR_ADDR_SHIFT(deviceaddress, NOR_MEMORY_16B, NOR_ADDRESS_COMMAND_SET); status = HAL_NOR_ReturnToReadMode(hnor); } @@ -487,22 +468,9 @@ HAL_StatusTypeDef HAL_NOR_Read_ID(NOR_HandleTypeDef *hnor, NOR_IDTypeDef *pNOR_I /* Send read ID command */ if (hnor->CommandSet == NOR_AMD_FUJITSU_COMMAND_SET) { - if (uwNORMemoryDataWidth == NOR_MEMORY_8B) - { - NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_FIRST_BYTE), - NOR_CMD_DATA_FIRST); - NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_SECOND_BYTE), - NOR_CMD_DATA_SECOND); - NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_THIRD_BYTE), - NOR_CMD_DATA_AUTO_SELECT); - } - else - { - NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_FIRST), NOR_CMD_DATA_FIRST); - NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_SECOND), NOR_CMD_DATA_SECOND); - NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_THIRD), - NOR_CMD_DATA_AUTO_SELECT); - } + NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, NOR_MEMORY_16B, NOR_CMD_ADDRESS_FIRST), NOR_CMD_DATA_FIRST); + NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, NOR_MEMORY_16B, NOR_CMD_ADDRESS_SECOND), NOR_CMD_DATA_SECOND); + NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, NOR_MEMORY_16B, NOR_CMD_ADDRESS_THIRD), NOR_CMD_DATA_AUTO_SELECT); } else if (hnor->CommandSet == NOR_INTEL_SHARP_EXT_COMMAND_SET) { @@ -517,13 +485,10 @@ HAL_StatusTypeDef HAL_NOR_Read_ID(NOR_HandleTypeDef *hnor, NOR_IDTypeDef *pNOR_I if (status != HAL_ERROR) { /* Read the NOR IDs */ - pNOR_ID->Manufacturer_Code = *(__IO uint16_t *) NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, MC_ADDRESS); - pNOR_ID->Device_Code1 = *(__IO uint16_t *) NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, - DEVICE_CODE1_ADDR); - pNOR_ID->Device_Code2 = *(__IO uint16_t *) NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, - DEVICE_CODE2_ADDR); - pNOR_ID->Device_Code3 = *(__IO uint16_t *) NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, - DEVICE_CODE3_ADDR); + pNOR_ID->Manufacturer_Code = *(__IO uint16_t *) NOR_ADDR_SHIFT(deviceaddress, NOR_MEMORY_16B, MC_ADDRESS); + pNOR_ID->Device_Code1 = *(__IO uint16_t *) NOR_ADDR_SHIFT(deviceaddress, NOR_MEMORY_16B, DEVICE_CODE1_ADDR); + pNOR_ID->Device_Code2 = *(__IO uint16_t *) NOR_ADDR_SHIFT(deviceaddress, NOR_MEMORY_16B, DEVICE_CODE2_ADDR); + pNOR_ID->Device_Code3 = *(__IO uint16_t *) NOR_ADDR_SHIFT(deviceaddress, NOR_MEMORY_16B, DEVICE_CODE3_ADDR); } /* Check the NOR controller state */ @@ -669,22 +634,9 @@ HAL_StatusTypeDef HAL_NOR_Read(NOR_HandleTypeDef *hnor, uint32_t *pAddress, uint /* Send read data command */ if (hnor->CommandSet == NOR_AMD_FUJITSU_COMMAND_SET) { - if (uwNORMemoryDataWidth == NOR_MEMORY_8B) - { - NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_FIRST_BYTE), - NOR_CMD_DATA_FIRST); - NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_SECOND_BYTE), - NOR_CMD_DATA_SECOND); - NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_THIRD_BYTE), - NOR_CMD_DATA_READ_RESET); - } - else - { - NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_FIRST), NOR_CMD_DATA_FIRST); - NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_SECOND), NOR_CMD_DATA_SECOND); - NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_THIRD), - NOR_CMD_DATA_READ_RESET); - } + NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, NOR_MEMORY_16B, NOR_CMD_ADDRESS_FIRST), NOR_CMD_DATA_FIRST); + NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, NOR_MEMORY_16B, NOR_CMD_ADDRESS_SECOND), NOR_CMD_DATA_SECOND); + NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, NOR_MEMORY_16B, NOR_CMD_ADDRESS_THIRD), NOR_CMD_DATA_READ_RESET); } else if (hnor->CommandSet == NOR_INTEL_SHARP_EXT_COMMAND_SET) { @@ -699,7 +651,7 @@ HAL_StatusTypeDef HAL_NOR_Read(NOR_HandleTypeDef *hnor, uint32_t *pAddress, uint if (status != HAL_ERROR) { /* Read the data */ - *pData = (uint16_t)(*(__IO uint32_t *)pAddress); + *pData = NOR_READ(pAddress); } /* Check the NOR controller state */ @@ -763,21 +715,9 @@ HAL_StatusTypeDef HAL_NOR_Program(NOR_HandleTypeDef *hnor, uint32_t *pAddress, u /* Send program data command */ if (hnor->CommandSet == NOR_AMD_FUJITSU_COMMAND_SET) { - if (uwNORMemoryDataWidth == NOR_MEMORY_8B) - { - NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_FIRST_BYTE), - NOR_CMD_DATA_FIRST); - NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_SECOND_BYTE), - NOR_CMD_DATA_SECOND); - NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_THIRD_BYTE), - NOR_CMD_DATA_PROGRAM); - } - else - { - NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_FIRST), NOR_CMD_DATA_FIRST); - NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_SECOND), NOR_CMD_DATA_SECOND); - NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_THIRD), NOR_CMD_DATA_PROGRAM); - } + NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, NOR_MEMORY_16B, NOR_CMD_ADDRESS_FIRST), NOR_CMD_DATA_FIRST); + NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, NOR_MEMORY_16B, NOR_CMD_ADDRESS_SECOND), NOR_CMD_DATA_SECOND); + NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, NOR_MEMORY_16B, NOR_CMD_ADDRESS_THIRD), NOR_CMD_DATA_PROGRAM); } else if (hnor->CommandSet == NOR_INTEL_SHARP_EXT_COMMAND_SET) { @@ -867,22 +807,9 @@ HAL_StatusTypeDef HAL_NOR_ReadBuffer(NOR_HandleTypeDef *hnor, uint32_t uwAddress /* Send read data command */ if (hnor->CommandSet == NOR_AMD_FUJITSU_COMMAND_SET) { - if (uwNORMemoryDataWidth == NOR_MEMORY_8B) - { - NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_FIRST_BYTE), - NOR_CMD_DATA_FIRST); - NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_SECOND_BYTE), - NOR_CMD_DATA_SECOND); - NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_THIRD_BYTE), - NOR_CMD_DATA_READ_RESET); - } - else - { - NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_FIRST), NOR_CMD_DATA_FIRST); - NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_SECOND), NOR_CMD_DATA_SECOND); - NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_THIRD), - NOR_CMD_DATA_READ_RESET); - } + NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, NOR_MEMORY_16B, NOR_CMD_ADDRESS_FIRST), NOR_CMD_DATA_FIRST); + NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, NOR_MEMORY_16B, NOR_CMD_ADDRESS_SECOND), NOR_CMD_DATA_SECOND); + NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, NOR_MEMORY_16B, NOR_CMD_ADDRESS_THIRD), NOR_CMD_DATA_READ_RESET); } else if (hnor->CommandSet == NOR_INTEL_SHARP_EXT_COMMAND_SET) { @@ -975,20 +902,10 @@ HAL_StatusTypeDef HAL_NOR_ProgramBuffer(NOR_HandleTypeDef *hnor, uint32_t uwAddr if (hnor->CommandSet == NOR_AMD_FUJITSU_COMMAND_SET) { - if (uwNORMemoryDataWidth == NOR_MEMORY_8B) - { - /* Issue unlock command sequence */ - NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_FIRST_BYTE), - NOR_CMD_DATA_FIRST); - NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_SECOND_BYTE), - NOR_CMD_DATA_SECOND); - } - else - { - /* Issue unlock command sequence */ - NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_FIRST), NOR_CMD_DATA_FIRST); - NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_SECOND), NOR_CMD_DATA_SECOND); - } + /* Issue unlock command sequence */ + NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, NOR_MEMORY_16B, NOR_CMD_ADDRESS_FIRST), NOR_CMD_DATA_FIRST); + NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, NOR_MEMORY_16B, NOR_CMD_ADDRESS_SECOND), NOR_CMD_DATA_SECOND); + /* Write Buffer Load Command */ NOR_WRITE((deviceaddress + uwAddress), NOR_CMD_DATA_BUFFER_AND_PROG); NOR_WRITE((deviceaddress + uwAddress), (uint16_t)(uwBufferSize - 1U)); @@ -1088,26 +1005,15 @@ HAL_StatusTypeDef HAL_NOR_Erase_Block(NOR_HandleTypeDef *hnor, uint32_t BlockAdd /* Send block erase command sequence */ if (hnor->CommandSet == NOR_AMD_FUJITSU_COMMAND_SET) { - if (uwNORMemoryDataWidth == NOR_MEMORY_8B) - { - NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_FIRST_BYTE), - NOR_CMD_DATA_FIRST); - NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_SECOND_BYTE), - NOR_CMD_DATA_SECOND); - NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_THIRD_BYTE), - NOR_CMD_DATA_CHIP_BLOCK_ERASE_THIRD); - } - else - { - NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_FIRST), NOR_CMD_DATA_FIRST); - NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_SECOND), NOR_CMD_DATA_SECOND); - NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_THIRD), - NOR_CMD_DATA_CHIP_BLOCK_ERASE_THIRD); - NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_FOURTH), - NOR_CMD_DATA_CHIP_BLOCK_ERASE_FOURTH); - NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_FIFTH), - NOR_CMD_DATA_CHIP_BLOCK_ERASE_FIFTH); - } + NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, NOR_MEMORY_16B, NOR_CMD_ADDRESS_FIRST), NOR_CMD_DATA_FIRST); + NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, NOR_MEMORY_16B, NOR_CMD_ADDRESS_SECOND), NOR_CMD_DATA_SECOND); + NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, NOR_MEMORY_16B, NOR_CMD_ADDRESS_THIRD), + NOR_CMD_DATA_CHIP_BLOCK_ERASE_THIRD); + NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, NOR_MEMORY_16B, NOR_CMD_ADDRESS_FOURTH), + NOR_CMD_DATA_CHIP_BLOCK_ERASE_FOURTH); + NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, NOR_MEMORY_16B, NOR_CMD_ADDRESS_FIFTH), + NOR_CMD_DATA_CHIP_BLOCK_ERASE_FIFTH); + NOR_WRITE((uint32_t)(BlockAddress + Address), NOR_CMD_DATA_BLOCK_ERASE); } else if (hnor->CommandSet == NOR_INTEL_SHARP_EXT_COMMAND_SET) @@ -1185,28 +1091,16 @@ HAL_StatusTypeDef HAL_NOR_Erase_Chip(NOR_HandleTypeDef *hnor, uint32_t Address) /* Send NOR chip erase command sequence */ if (hnor->CommandSet == NOR_AMD_FUJITSU_COMMAND_SET) { - if (uwNORMemoryDataWidth == NOR_MEMORY_8B) - { - NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_FIRST_BYTE), - NOR_CMD_DATA_FIRST); - NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_SECOND_BYTE), - NOR_CMD_DATA_SECOND); - NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_THIRD_BYTE), - NOR_CMD_DATA_CHIP_BLOCK_ERASE_THIRD); - } - else - { - NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_FIRST), NOR_CMD_DATA_FIRST); - NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_SECOND), NOR_CMD_DATA_SECOND); - NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_THIRD), - NOR_CMD_DATA_CHIP_BLOCK_ERASE_THIRD); - NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_FOURTH), - NOR_CMD_DATA_CHIP_BLOCK_ERASE_FOURTH); - NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_FIFTH), - NOR_CMD_DATA_CHIP_BLOCK_ERASE_FIFTH); - NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_SIXTH), - NOR_CMD_DATA_CHIP_ERASE); - } + NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, NOR_MEMORY_16B, NOR_CMD_ADDRESS_FIRST), NOR_CMD_DATA_FIRST); + NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, NOR_MEMORY_16B, NOR_CMD_ADDRESS_SECOND), NOR_CMD_DATA_SECOND); + NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, NOR_MEMORY_16B, NOR_CMD_ADDRESS_THIRD), + NOR_CMD_DATA_CHIP_BLOCK_ERASE_THIRD); + NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, NOR_MEMORY_16B, NOR_CMD_ADDRESS_FOURTH), + NOR_CMD_DATA_CHIP_BLOCK_ERASE_FOURTH); + NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, NOR_MEMORY_16B, NOR_CMD_ADDRESS_FIFTH), + NOR_CMD_DATA_CHIP_BLOCK_ERASE_FIFTH); + NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, NOR_MEMORY_16B, NOR_CMD_ADDRESS_SIXTH), + NOR_CMD_DATA_CHIP_ERASE); } else { @@ -1277,20 +1171,13 @@ HAL_StatusTypeDef HAL_NOR_Read_CFI(NOR_HandleTypeDef *hnor, NOR_CFITypeDef *pNOR } /* Send read CFI query command */ - if (uwNORMemoryDataWidth == NOR_MEMORY_8B) - { - NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_FIRST_CFI_BYTE), - NOR_CMD_DATA_CFI); - } - else - { - NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_FIRST_CFI), NOR_CMD_DATA_CFI); - } + NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, NOR_MEMORY_16B, NOR_CMD_ADDRESS_FIRST_CFI), NOR_CMD_DATA_CFI); + /* read the NOR CFI information */ - pNOR_CFI->CFI_1 = *(__IO uint16_t *) NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, CFI1_ADDRESS); - pNOR_CFI->CFI_2 = *(__IO uint16_t *) NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, CFI2_ADDRESS); - pNOR_CFI->CFI_3 = *(__IO uint16_t *) NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, CFI3_ADDRESS); - pNOR_CFI->CFI_4 = *(__IO uint16_t *) NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, CFI4_ADDRESS); + pNOR_CFI->CFI_1 = *(__IO uint16_t *) NOR_ADDR_SHIFT(deviceaddress, NOR_MEMORY_16B, CFI1_ADDRESS); + pNOR_CFI->CFI_2 = *(__IO uint16_t *) NOR_ADDR_SHIFT(deviceaddress, NOR_MEMORY_16B, CFI2_ADDRESS); + pNOR_CFI->CFI_3 = *(__IO uint16_t *) NOR_ADDR_SHIFT(deviceaddress, NOR_MEMORY_16B, CFI3_ADDRESS); + pNOR_CFI->CFI_4 = *(__IO uint16_t *) NOR_ADDR_SHIFT(deviceaddress, NOR_MEMORY_16B, CFI4_ADDRESS); /* Check the NOR controller state */ hnor->State = state; diff --git a/system/Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pccard.c b/system/Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pccard.c index c92ab54ebd..af6a88fadd 100644 --- a/system/Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pccard.c +++ b/system/Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pccard.c @@ -163,7 +163,8 @@ * @retval HAL status */ HAL_StatusTypeDef HAL_PCCARD_Init(PCCARD_HandleTypeDef *hpccard, FMC_NAND_PCC_TimingTypeDef *ComSpaceTiming, - FMC_NAND_PCC_TimingTypeDef *AttSpaceTiming, FMC_NAND_PCC_TimingTypeDef *IOSpaceTiming) + FMC_NAND_PCC_TimingTypeDef *AttSpaceTiming, + FMC_NAND_PCC_TimingTypeDef *IOSpaceTiming) { /* Check the PCCARD controller state */ if (hpccard == NULL) @@ -187,7 +188,7 @@ HAL_StatusTypeDef HAL_PCCARD_Init(PCCARD_HandleTypeDef *hpccard, FMC_NAND_PCC_Ti #else /* Initialize the low level hardware (MSP) */ HAL_PCCARD_MspInit(hpccard); -#endif +#endif /* USE_HAL_PCCARD_REGISTER_CALLBACKS */ } /* Initialize the PCCARD state */ @@ -234,7 +235,7 @@ HAL_StatusTypeDef HAL_PCCARD_DeInit(PCCARD_HandleTypeDef *hpccard) #else /* De-Initialize the low level hardware (MSP) */ HAL_PCCARD_MspDeInit(hpccard); -#endif +#endif /* USE_HAL_PCCARD_REGISTER_CALLBACKS */ /* Configure the PCCARD registers with their reset values */ FMC_PCCARD_DeInit(hpccard->Instance); @@ -307,8 +308,9 @@ __weak void HAL_PCCARD_MspDeInit(PCCARD_HandleTypeDef *hpccard) */ HAL_StatusTypeDef HAL_PCCARD_Read_ID(PCCARD_HandleTypeDef *hpccard, uint8_t CompactFlash_ID[], uint8_t *pStatus) { - uint32_t timeout = PCCARD_TIMEOUT_READ_ID, index = 0U; - uint8_t status = 0; + uint32_t timeout = 0U; + uint32_t index = 0U; + uint8_t status = 0U; /* Process Locked */ __HAL_LOCK(hpccard); @@ -319,6 +321,9 @@ HAL_StatusTypeDef HAL_PCCARD_Read_ID(PCCARD_HandleTypeDef *hpccard, uint8_t Comp return HAL_BUSY; } + /* Initialize timeout value */ + timeout = PCCARD_TIMEOUT_READ_ID; + /* Update the PCCARD controller state */ hpccard->State = HAL_PCCARD_STATE_BUSY; @@ -371,8 +376,9 @@ HAL_StatusTypeDef HAL_PCCARD_Read_ID(PCCARD_HandleTypeDef *hpccard, uint8_t Comp HAL_StatusTypeDef HAL_PCCARD_Read_Sector(PCCARD_HandleTypeDef *hpccard, uint16_t *pBuffer, uint16_t SectorAddress, uint8_t *pStatus) { - uint32_t timeout = PCCARD_TIMEOUT_READ_WRITE_SECTOR, index = 0U; - uint8_t status = 0; + uint32_t timeout = 0U; + uint32_t index = 0U; + uint8_t status = 0U; /* Process Locked */ __HAL_LOCK(hpccard); @@ -383,6 +389,9 @@ HAL_StatusTypeDef HAL_PCCARD_Read_Sector(PCCARD_HandleTypeDef *hpccard, uint16_t return HAL_BUSY; } + /* Initialize timeout value */ + timeout = PCCARD_TIMEOUT_READ_WRITE_SECTOR; + /* Update the PCCARD controller state */ hpccard->State = HAL_PCCARD_STATE_BUSY; @@ -448,8 +457,9 @@ HAL_StatusTypeDef HAL_PCCARD_Read_Sector(PCCARD_HandleTypeDef *hpccard, uint16_t HAL_StatusTypeDef HAL_PCCARD_Write_Sector(PCCARD_HandleTypeDef *hpccard, uint16_t *pBuffer, uint16_t SectorAddress, uint8_t *pStatus) { - uint32_t timeout = PCCARD_TIMEOUT_READ_WRITE_SECTOR, index = 0U; - uint8_t status = 0; + uint32_t timeout = 0U; + uint32_t index = 0U; + uint8_t status = 0U; /* Process Locked */ __HAL_LOCK(hpccard); @@ -460,6 +470,9 @@ HAL_StatusTypeDef HAL_PCCARD_Write_Sector(PCCARD_HandleTypeDef *hpccard, uint16_ return HAL_BUSY; } + /* Initialize timeout value */ + timeout = PCCARD_TIMEOUT_READ_WRITE_SECTOR; + /* Update the PCCARD controller state */ hpccard->State = HAL_PCCARD_STATE_BUSY; @@ -522,7 +535,7 @@ HAL_StatusTypeDef HAL_PCCARD_Write_Sector(PCCARD_HandleTypeDef *hpccard, uint16_ HAL_StatusTypeDef HAL_PCCARD_Erase_Sector(PCCARD_HandleTypeDef *hpccard, uint16_t SectorAddress, uint8_t *pStatus) { uint32_t timeout = PCCARD_TIMEOUT_ERASE_SECTOR; - uint8_t status = 0; + uint8_t status = 0U; /* Process Locked */ __HAL_LOCK(hpccard); @@ -624,7 +637,7 @@ void HAL_PCCARD_IRQHandler(PCCARD_HandleTypeDef *hpccard) hpccard->ItCallback(hpccard); #else HAL_PCCARD_ITCallback(hpccard); -#endif +#endif /* USE_HAL_PCCARD_REGISTER_CALLBACKS */ /* Clear PCCARD interrupt Rising edge pending bit */ __FMC_PCCARD_CLEAR_FLAG(hpccard->Instance, FMC_FLAG_RISING_EDGE); @@ -638,7 +651,7 @@ void HAL_PCCARD_IRQHandler(PCCARD_HandleTypeDef *hpccard) hpccard->ItCallback(hpccard); #else HAL_PCCARD_ITCallback(hpccard); -#endif +#endif /* USE_HAL_PCCARD_REGISTER_CALLBACKS */ /* Clear PCCARD interrupt Level pending bit */ __FMC_PCCARD_CLEAR_FLAG(hpccard->Instance, FMC_FLAG_LEVEL); @@ -652,7 +665,7 @@ void HAL_PCCARD_IRQHandler(PCCARD_HandleTypeDef *hpccard) hpccard->ItCallback(hpccard); #else HAL_PCCARD_ITCallback(hpccard); -#endif +#endif /* USE_HAL_PCCARD_REGISTER_CALLBACKS */ /* Clear PCCARD interrupt Falling edge pending bit */ __FMC_PCCARD_CLEAR_FLAG(hpccard->Instance, FMC_FLAG_FALLING_EDGE); @@ -666,7 +679,7 @@ void HAL_PCCARD_IRQHandler(PCCARD_HandleTypeDef *hpccard) hpccard->ItCallback(hpccard); #else HAL_PCCARD_ITCallback(hpccard); -#endif +#endif /* USE_HAL_PCCARD_REGISTER_CALLBACKS */ /* Clear PCCARD interrupt FIFO empty pending bit */ __FMC_PCCARD_CLEAR_FLAG(hpccard->Instance, FMC_FLAG_FEMPT); @@ -823,7 +836,7 @@ HAL_StatusTypeDef HAL_PCCARD_UnRegisterCallback(PCCARD_HandleTypeDef *hpccard, H __HAL_UNLOCK(hpccard); return status; } -#endif +#endif /* USE_HAL_PCCARD_REGISTER_CALLBACKS */ /** * @} @@ -866,7 +879,8 @@ HAL_PCCARD_StateTypeDef HAL_PCCARD_GetState(PCCARD_HandleTypeDef *hpccard) */ HAL_PCCARD_StatusTypeDef HAL_PCCARD_GetStatus(PCCARD_HandleTypeDef *hpccard) { - uint32_t timeout = PCCARD_TIMEOUT_STATUS, status_pccard = 0U; + uint32_t timeout = PCCARD_TIMEOUT_STATUS; + uint32_t status_pccard = 0U; /* Check the PCCARD controller state */ if (hpccard->State == HAL_PCCARD_STATE_BUSY) @@ -902,7 +916,8 @@ HAL_PCCARD_StatusTypeDef HAL_PCCARD_GetStatus(PCCARD_HandleTypeDef *hpccard) */ HAL_PCCARD_StatusTypeDef HAL_PCCARD_ReadStatus(PCCARD_HandleTypeDef *hpccard) { - uint8_t data = 0U, status_pccard = PCCARD_BUSY; + uint8_t data = 0U; + uint8_t status_pccard = PCCARD_BUSY; /* Check the PCCARD controller state */ if (hpccard->State == HAL_PCCARD_STATE_BUSY) diff --git a/system/Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pcd.c b/system/Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pcd.c index 427a38f018..d764468e9c 100644 --- a/system/Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pcd.c +++ b/system/Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pcd.c @@ -49,6 +49,9 @@ (#)Enable PCD transmission and reception: (##) HAL_PCD_Start(); + (#)NOTE: For applications not using double buffer mode, define the symbol + 'USE_USB_DOUBLE_BUFFER' as 0 to reduce the driver's memory footprint. + @endverbatim ****************************************************************************** */ @@ -302,8 +305,6 @@ HAL_StatusTypeDef HAL_PCD_RegisterCallback(PCD_HandleTypeDef *hpcd, hpcd->ErrorCode |= HAL_PCD_ERROR_INVALID_CALLBACK; return HAL_ERROR; } - /* Process locked */ - __HAL_LOCK(hpcd); if (hpcd->State == HAL_PCD_STATE_READY) { @@ -381,8 +382,6 @@ HAL_StatusTypeDef HAL_PCD_RegisterCallback(PCD_HandleTypeDef *hpcd, status = HAL_ERROR; } - /* Release Lock */ - __HAL_UNLOCK(hpcd); return status; } @@ -407,9 +406,6 @@ HAL_StatusTypeDef HAL_PCD_UnRegisterCallback(PCD_HandleTypeDef *hpcd, HAL_PCD_Ca { HAL_StatusTypeDef status = HAL_OK; - /* Process locked */ - __HAL_LOCK(hpcd); - /* Setup Legacy weak Callbacks */ if (hpcd->State == HAL_PCD_STATE_READY) { @@ -490,8 +486,6 @@ HAL_StatusTypeDef HAL_PCD_UnRegisterCallback(PCD_HandleTypeDef *hpcd, HAL_PCD_Ca status = HAL_ERROR; } - /* Release Lock */ - __HAL_UNLOCK(hpcd); return status; } @@ -515,9 +509,6 @@ HAL_StatusTypeDef HAL_PCD_RegisterDataOutStageCallback(PCD_HandleTypeDef *hpcd, return HAL_ERROR; } - /* Process locked */ - __HAL_LOCK(hpcd); - if (hpcd->State == HAL_PCD_STATE_READY) { hpcd->DataOutStageCallback = pCallback; @@ -531,9 +522,6 @@ HAL_StatusTypeDef HAL_PCD_RegisterDataOutStageCallback(PCD_HandleTypeDef *hpcd, status = HAL_ERROR; } - /* Release Lock */ - __HAL_UNLOCK(hpcd); - return status; } @@ -547,9 +535,6 @@ HAL_StatusTypeDef HAL_PCD_UnRegisterDataOutStageCallback(PCD_HandleTypeDef *hpcd { HAL_StatusTypeDef status = HAL_OK; - /* Process locked */ - __HAL_LOCK(hpcd); - if (hpcd->State == HAL_PCD_STATE_READY) { hpcd->DataOutStageCallback = HAL_PCD_DataOutStageCallback; /* Legacy weak DataOutStageCallback */ @@ -563,9 +548,6 @@ HAL_StatusTypeDef HAL_PCD_UnRegisterDataOutStageCallback(PCD_HandleTypeDef *hpcd status = HAL_ERROR; } - /* Release Lock */ - __HAL_UNLOCK(hpcd); - return status; } @@ -589,9 +571,6 @@ HAL_StatusTypeDef HAL_PCD_RegisterDataInStageCallback(PCD_HandleTypeDef *hpcd, return HAL_ERROR; } - /* Process locked */ - __HAL_LOCK(hpcd); - if (hpcd->State == HAL_PCD_STATE_READY) { hpcd->DataInStageCallback = pCallback; @@ -605,9 +584,6 @@ HAL_StatusTypeDef HAL_PCD_RegisterDataInStageCallback(PCD_HandleTypeDef *hpcd, status = HAL_ERROR; } - /* Release Lock */ - __HAL_UNLOCK(hpcd); - return status; } @@ -621,9 +597,6 @@ HAL_StatusTypeDef HAL_PCD_UnRegisterDataInStageCallback(PCD_HandleTypeDef *hpcd) { HAL_StatusTypeDef status = HAL_OK; - /* Process locked */ - __HAL_LOCK(hpcd); - if (hpcd->State == HAL_PCD_STATE_READY) { hpcd->DataInStageCallback = HAL_PCD_DataInStageCallback; /* Legacy weak DataInStageCallback */ @@ -637,9 +610,6 @@ HAL_StatusTypeDef HAL_PCD_UnRegisterDataInStageCallback(PCD_HandleTypeDef *hpcd) status = HAL_ERROR; } - /* Release Lock */ - __HAL_UNLOCK(hpcd); - return status; } @@ -663,9 +633,6 @@ HAL_StatusTypeDef HAL_PCD_RegisterIsoOutIncpltCallback(PCD_HandleTypeDef *hpcd, return HAL_ERROR; } - /* Process locked */ - __HAL_LOCK(hpcd); - if (hpcd->State == HAL_PCD_STATE_READY) { hpcd->ISOOUTIncompleteCallback = pCallback; @@ -679,9 +646,6 @@ HAL_StatusTypeDef HAL_PCD_RegisterIsoOutIncpltCallback(PCD_HandleTypeDef *hpcd, status = HAL_ERROR; } - /* Release Lock */ - __HAL_UNLOCK(hpcd); - return status; } @@ -696,9 +660,6 @@ HAL_StatusTypeDef HAL_PCD_UnRegisterIsoOutIncpltCallback(PCD_HandleTypeDef *hpcd { HAL_StatusTypeDef status = HAL_OK; - /* Process locked */ - __HAL_LOCK(hpcd); - if (hpcd->State == HAL_PCD_STATE_READY) { hpcd->ISOOUTIncompleteCallback = HAL_PCD_ISOOUTIncompleteCallback; /* Legacy weak ISOOUTIncompleteCallback */ @@ -712,9 +673,6 @@ HAL_StatusTypeDef HAL_PCD_UnRegisterIsoOutIncpltCallback(PCD_HandleTypeDef *hpcd status = HAL_ERROR; } - /* Release Lock */ - __HAL_UNLOCK(hpcd); - return status; } @@ -738,9 +696,6 @@ HAL_StatusTypeDef HAL_PCD_RegisterIsoInIncpltCallback(PCD_HandleTypeDef *hpcd, return HAL_ERROR; } - /* Process locked */ - __HAL_LOCK(hpcd); - if (hpcd->State == HAL_PCD_STATE_READY) { hpcd->ISOINIncompleteCallback = pCallback; @@ -754,9 +709,6 @@ HAL_StatusTypeDef HAL_PCD_RegisterIsoInIncpltCallback(PCD_HandleTypeDef *hpcd, status = HAL_ERROR; } - /* Release Lock */ - __HAL_UNLOCK(hpcd); - return status; } @@ -771,9 +723,6 @@ HAL_StatusTypeDef HAL_PCD_UnRegisterIsoInIncpltCallback(PCD_HandleTypeDef *hpcd) { HAL_StatusTypeDef status = HAL_OK; - /* Process locked */ - __HAL_LOCK(hpcd); - if (hpcd->State == HAL_PCD_STATE_READY) { hpcd->ISOINIncompleteCallback = HAL_PCD_ISOINIncompleteCallback; /* Legacy weak ISOINIncompleteCallback */ @@ -787,9 +736,6 @@ HAL_StatusTypeDef HAL_PCD_UnRegisterIsoInIncpltCallback(PCD_HandleTypeDef *hpcd) status = HAL_ERROR; } - /* Release Lock */ - __HAL_UNLOCK(hpcd); - return status; } @@ -937,6 +883,9 @@ void HAL_PCD_IRQHandler(PCD_HandleTypeDef *hpcd) { __HAL_PCD_CLEAR_FLAG(hpcd, USB_ISTR_SOF); + /* store current frame number */ + hpcd->FrameNumber = USB_GetCurrentFrame(hpcd->Instance); + #if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U) hpcd->SOFCallback(hpcd); #else @@ -1219,7 +1168,7 @@ HAL_StatusTypeDef HAL_PCD_SetAddress(PCD_HandleTypeDef *hpcd, uint8_t address) HAL_StatusTypeDef HAL_PCD_EP_Open(PCD_HandleTypeDef *hpcd, uint8_t ep_addr, uint16_t ep_mps, uint8_t ep_type) { - HAL_StatusTypeDef ret = HAL_OK; + HAL_StatusTypeDef ret = HAL_OK; PCD_EPTypeDef *ep; if ((ep_addr & 0x80U) == 0x80U) @@ -1234,7 +1183,7 @@ HAL_StatusTypeDef HAL_PCD_EP_Open(PCD_HandleTypeDef *hpcd, uint8_t ep_addr, } ep->num = ep_addr & EP_ADDR_MSK; - ep->maxpacket = ep_mps; + ep->maxpacket = (uint32_t)ep_mps & 0x7FFU; ep->type = ep_type; /* Set initial data PID. */ @@ -1365,7 +1314,7 @@ HAL_StatusTypeDef HAL_PCD_EP_SetStall(PCD_HandleTypeDef *hpcd, uint8_t ep_addr) } else { - ep = &hpcd->OUT_ep[ep_addr]; + ep = &hpcd->OUT_ep[ep_addr & EP_ADDR_MSK]; ep->is_in = 0U; } @@ -1391,7 +1340,7 @@ HAL_StatusTypeDef HAL_PCD_EP_ClrStall(PCD_HandleTypeDef *hpcd, uint8_t ep_addr) { PCD_EPTypeDef *ep; - if (((uint32_t)ep_addr & 0x0FU) > hpcd->Init.dev_endpoints) + if (((uint32_t)ep_addr & EP_ADDR_MSK) > hpcd->Init.dev_endpoints) { return HAL_ERROR; } @@ -1548,6 +1497,9 @@ static HAL_StatusTypeDef PCD_EP_ISR_Handler(PCD_HandleTypeDef *hpcd) count = 0U; #endif /* USE_USB_DOUBLE_BUFFER */ + /* store current frame number */ + hpcd->FrameNumber = USB_GetCurrentFrame(hpcd->Instance); + /* stay in loop while pending interrupts */ while ((hpcd->Instance->ISTR & USB_ISTR_CTR) != 0U) { @@ -1556,6 +1508,11 @@ static HAL_StatusTypeDef PCD_EP_ISR_Handler(PCD_HandleTypeDef *hpcd) /* extract highest priority endpoint number */ epindex = (uint8_t)(wIstr & USB_ISTR_EP_ID); + if (epindex >= 8U) + { + return HAL_ERROR; + } + if (epindex == 0U) { /* Decode and service control endpoint interrupt */ @@ -1600,6 +1557,18 @@ static HAL_StatusTypeDef PCD_EP_ISR_Handler(PCD_HandleTypeDef *hpcd) /* Get SETUP Packet */ ep->xfer_count = PCD_GET_EP_RX_CNT(hpcd->Instance, ep->num); + if (ep->xfer_count != 8U) + { + /* Set Stall condition for EP0 IN/OUT */ + PCD_SET_EP_RX_STATUS(hpcd->Instance, PCD_ENDP0, USB_EP_RX_STALL); + PCD_SET_EP_TX_STATUS(hpcd->Instance, PCD_ENDP0, USB_EP_TX_STALL); + + /* SETUP bit kept frozen while CTR_RX = 1 */ + PCD_CLEAR_RX_EP_CTR(hpcd->Instance, PCD_ENDP0); + + return HAL_OK; + } + USB_ReadPMA(hpcd->Instance, (uint8_t *)hpcd->Setup, ep->pmaadress, (uint16_t)ep->xfer_count); @@ -1620,27 +1589,27 @@ static HAL_StatusTypeDef PCD_EP_ISR_Handler(PCD_HandleTypeDef *hpcd) /* Get Control Data OUT Packet */ ep->xfer_count = PCD_GET_EP_RX_CNT(hpcd->Instance, ep->num); - if ((ep->xfer_count != 0U) && (ep->xfer_buff != 0U)) + if (ep->xfer_count == 0U) { - USB_ReadPMA(hpcd->Instance, ep->xfer_buff, - ep->pmaadress, (uint16_t)ep->xfer_count); + /* Status phase re-arm for next setup */ + PCD_SET_EP_RX_STATUS(hpcd->Instance, PCD_ENDP0, USB_EP_RX_VALID); + } + else + { + if (ep->xfer_buff != 0U) + { + USB_ReadPMA(hpcd->Instance, ep->xfer_buff, + ep->pmaadress, (uint16_t)ep->xfer_count); /* max 64bytes */ - ep->xfer_buff += ep->xfer_count; + ep->xfer_buff += ep->xfer_count; - /* Process Control Data OUT Packet */ + /* Process Control Data OUT Packet */ #if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U) - hpcd->DataOutStageCallback(hpcd, 0U); + hpcd->DataOutStageCallback(hpcd, 0U); #else - HAL_PCD_DataOutStageCallback(hpcd, 0U); + HAL_PCD_DataOutStageCallback(hpcd, 0U); #endif /* USE_HAL_PCD_REGISTER_CALLBACKS */ - } - - wEPVal = (uint16_t)PCD_GET_ENDPOINT(hpcd->Instance, PCD_ENDP0); - - if (((wEPVal & USB_EP_SETUP) == 0U) && ((wEPVal & USB_EP_RX_STRX) != USB_EP_RX_VALID)) - { - PCD_SET_EP_RX_CNT(hpcd->Instance, PCD_ENDP0, ep->maxpacket); - PCD_SET_EP_RX_STATUS(hpcd->Instance, PCD_ENDP0, USB_EP_RX_VALID); + } } } } @@ -1706,7 +1675,6 @@ static HAL_StatusTypeDef PCD_EP_ISR_Handler(PCD_HandleTypeDef *hpcd) /* multi-packet on the NON control OUT endpoint */ ep->xfer_count += count; - ep->xfer_buff += count; if ((ep->xfer_len == 0U) || (count < ep->maxpacket)) { @@ -1719,6 +1687,7 @@ static HAL_StatusTypeDef PCD_EP_ISR_Handler(PCD_HandleTypeDef *hpcd) } else { + ep->xfer_buff += count; (void)USB_EPStartXfer(hpcd->Instance, ep); } } @@ -1760,7 +1729,7 @@ static HAL_StatusTypeDef PCD_EP_ISR_Handler(PCD_HandleTypeDef *hpcd) /* Manage Single Buffer Transaction */ if ((wEPVal & USB_EP_KIND) == 0U) { - /* multi-packet on the NON control IN endpoint */ + /* Multi-packet on the NON control IN endpoint */ TxPctSize = (uint16_t)PCD_GET_EP_TX_CNT(hpcd->Instance, ep->num); if (ep->xfer_len > TxPctSize) @@ -1836,7 +1805,7 @@ static uint16_t HAL_PCD_EP_DB_Receive(PCD_HandleTypeDef *hpcd, if (ep->xfer_len == 0U) { - /* set NAK to OUT endpoint since double buffer is enabled */ + /* Set NAK to OUT endpoint since double buffer is enabled */ PCD_SET_EP_RX_STATUS(hpcd->Instance, ep->num, USB_EP_RX_NAK); } @@ -1868,11 +1837,11 @@ static uint16_t HAL_PCD_EP_DB_Receive(PCD_HandleTypeDef *hpcd, if (ep->xfer_len == 0U) { - /* set NAK on the current endpoint */ + /* Set NAK on the current endpoint */ PCD_SET_EP_RX_STATUS(hpcd->Instance, ep->num, USB_EP_RX_NAK); } - /*Need to FreeUser Buffer*/ + /* Need to FreeUser Buffer */ if ((wEPVal & USB_EP_DTOG_TX) == 0U) { PCD_FREE_USER_BUFFER(hpcd->Instance, ep->num, 0U); @@ -1922,6 +1891,12 @@ static HAL_StatusTypeDef HAL_PCD_EP_DB_Transmit(PCD_HandleTypeDef *hpcd, PCD_SET_EP_DBUF0_CNT(hpcd->Instance, ep->num, ep->is_in, 0U); PCD_SET_EP_DBUF1_CNT(hpcd->Instance, ep->num, ep->is_in, 0U); + if (ep->type == EP_TYPE_BULK) + { + /* Set Bulk endpoint in NAK state */ + PCD_SET_EP_TX_STATUS(hpcd->Instance, ep->num, USB_EP_TX_NAK); + } + /* TX COMPLETE */ #if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U) hpcd->DataInStageCallback(hpcd, ep->num); @@ -1933,10 +1908,12 @@ static HAL_StatusTypeDef HAL_PCD_EP_DB_Transmit(PCD_HandleTypeDef *hpcd, { PCD_FREE_USER_BUFFER(hpcd->Instance, ep->num, 1U); } + + return HAL_OK; } else /* Transfer is not yet Done */ { - /* need to Free USB Buff */ + /* Need to Free USB Buffer */ if ((wEPVal & USB_EP_DTOG_RX) != 0U) { PCD_FREE_USER_BUFFER(hpcd->Instance, ep->num, 1U); @@ -1967,7 +1944,7 @@ static HAL_StatusTypeDef HAL_PCD_EP_DB_Transmit(PCD_HandleTypeDef *hpcd, } /* Write remaining Data to Buffer */ - /* Set the Double buffer counter for pma buffer1 */ + /* Set the Double buffer counter for pma buffer0 */ PCD_SET_EP_DBUF0_CNT(hpcd->Instance, ep->num, ep->is_in, len); /* Copy user buffer to USB PMA */ @@ -1995,6 +1972,12 @@ static HAL_StatusTypeDef HAL_PCD_EP_DB_Transmit(PCD_HandleTypeDef *hpcd, PCD_SET_EP_DBUF0_CNT(hpcd->Instance, ep->num, ep->is_in, 0U); PCD_SET_EP_DBUF1_CNT(hpcd->Instance, ep->num, ep->is_in, 0U); + if (ep->type == EP_TYPE_BULK) + { + /* Set Bulk endpoint in NAK state */ + PCD_SET_EP_TX_STATUS(hpcd->Instance, ep->num, USB_EP_TX_NAK); + } + /* TX COMPLETE */ #if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U) hpcd->DataInStageCallback(hpcd, ep->num); @@ -2007,10 +1990,12 @@ static HAL_StatusTypeDef HAL_PCD_EP_DB_Transmit(PCD_HandleTypeDef *hpcd, { PCD_FREE_USER_BUFFER(hpcd->Instance, ep->num, 1U); } + + return HAL_OK; } else /* Transfer is not yet Done */ { - /* need to Free USB Buff */ + /* Need to Free USB Buffer */ if ((wEPVal & USB_EP_DTOG_RX) == 0U) { PCD_FREE_USER_BUFFER(hpcd->Instance, ep->num, 1U); @@ -2040,7 +2025,7 @@ static HAL_StatusTypeDef HAL_PCD_EP_DB_Transmit(PCD_HandleTypeDef *hpcd, ep->xfer_fill_db = 0; } - /* Set the Double buffer counter for pmabuffer1 */ + /* Set the Double buffer counter for pma buffer1 */ PCD_SET_EP_DBUF1_CNT(hpcd->Instance, ep->num, ep->is_in, len); /* Copy the user buffer to USB PMA */ @@ -2049,7 +2034,7 @@ static HAL_StatusTypeDef HAL_PCD_EP_DB_Transmit(PCD_HandleTypeDef *hpcd, } } - /*enable endpoint IN*/ + /* Enable endpoint IN */ PCD_SET_EP_TX_STATUS(hpcd->Instance, ep->num, USB_EP_TX_VALID); return HAL_OK; @@ -2057,13 +2042,11 @@ static HAL_StatusTypeDef HAL_PCD_EP_DB_Transmit(PCD_HandleTypeDef *hpcd, #endif /* (USE_USB_DOUBLE_BUFFER == 1U) */ - /** * @} */ #endif /* defined (USB) */ #endif /* HAL_PCD_MODULE_ENABLED */ - /** * @} */ diff --git a/system/Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pcd_ex.c b/system/Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pcd_ex.c index 944cc345d0..2980e07d84 100644 --- a/system/Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pcd_ex.c +++ b/system/Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pcd_ex.c @@ -82,14 +82,14 @@ HAL_StatusTypeDef HAL_PCDEx_PMAConfig(PCD_HandleTypeDef *hpcd, uint16_t ep_addr { PCD_EPTypeDef *ep; - /* initialize ep structure*/ + /* Initialize ep structure */ if ((0x80U & ep_addr) == 0x80U) { ep = &hpcd->IN_ep[ep_addr & EP_ADDR_MSK]; } else { - ep = &hpcd->OUT_ep[ep_addr]; + ep = &hpcd->OUT_ep[ep_addr & EP_ADDR_MSK]; } /* Here we check if the endpoint is single or double Buffer*/ @@ -97,6 +97,7 @@ HAL_StatusTypeDef HAL_PCDEx_PMAConfig(PCD_HandleTypeDef *hpcd, uint16_t ep_addr { /* Single Buffer */ ep->doublebuffer = 0U; + /* Configure the PMA */ ep->pmaadress = (uint16_t)pmaadress; } @@ -105,6 +106,7 @@ HAL_StatusTypeDef HAL_PCDEx_PMAConfig(PCD_HandleTypeDef *hpcd, uint16_t ep_addr { /* Double Buffer Endpoint */ ep->doublebuffer = 1U; + /* Configure the PMA */ ep->pmaaddr0 = (uint16_t)(pmaadress & 0xFFFFU); ep->pmaaddr1 = (uint16_t)((pmaadress & 0xFFFF0000U) >> 16); diff --git a/system/Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c b/system/Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c index c2731eaffe..29c4005186 100644 --- a/system/Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c +++ b/system/Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c @@ -311,7 +311,7 @@ HAL_StatusTypeDef HAL_RCC_DeInit(void) * first and then HSE On or HSE Bypass. * @retval HAL status */ -HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct) +HAL_StatusTypeDef HAL_RCC_OscConfig(const RCC_OscInitTypeDef *RCC_OscInitStruct) { uint32_t tickstart; uint32_t pll_config; @@ -691,7 +691,7 @@ HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct) * currently used as system clock source. * @retval HAL status */ -HAL_StatusTypeDef HAL_RCC_ClockConfig(RCC_ClkInitTypeDef *RCC_ClkInitStruct, uint32_t FLatency) +HAL_StatusTypeDef HAL_RCC_ClockConfig(const RCC_ClkInitTypeDef *RCC_ClkInitStruct, uint32_t FLatency) { uint32_t tickstart = 0U; diff --git a/system/Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rtc.c b/system/Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rtc.c index c63ed710c8..5c413bb21a 100644 --- a/system/Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rtc.c +++ b/system/Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rtc.c @@ -253,7 +253,7 @@ */ HAL_StatusTypeDef HAL_RTC_Init(RTC_HandleTypeDef *hrtc) { - HAL_StatusTypeDef status = HAL_ERROR; + HAL_StatusTypeDef status; /* Check RTC handler validity */ if (hrtc == NULL) @@ -368,7 +368,7 @@ HAL_StatusTypeDef HAL_RTC_Init(RTC_HandleTypeDef *hrtc) */ HAL_StatusTypeDef HAL_RTC_DeInit(RTC_HandleTypeDef *hrtc) { - HAL_StatusTypeDef status = HAL_ERROR; + HAL_StatusTypeDef status; /* Check the parameters */ assert_param(IS_RTC_ALL_INSTANCE(hrtc->Instance)); @@ -387,7 +387,7 @@ HAL_StatusTypeDef HAL_RTC_DeInit(RTC_HandleTypeDef *hrtc) /* Reset RTC registers */ hrtc->Instance->TR = 0x00000000U; hrtc->Instance->DR = (RTC_DR_WDU_0 | RTC_DR_MU_0 | RTC_DR_DU_0); - hrtc->Instance->CR &= 0x00000000U; + hrtc->Instance->CR = 0x00000000U; hrtc->Instance->WUTR = RTC_WUTR_WUT; hrtc->Instance->PRER = (uint32_t)(RTC_PRER_PREDIV_A | 0x000000FFU); hrtc->Instance->ALRMAR = 0x00000000U; @@ -1640,7 +1640,7 @@ HAL_StatusTypeDef HAL_RTC_PollForAlarmAEvent(RTC_HandleTypeDef *hrtc, uint32_t T { if (Timeout != HAL_MAX_DELAY) { - if ((Timeout == 0U) || ((HAL_GetTick() - tickstart) > Timeout)) + if (((HAL_GetTick() - tickstart) > Timeout) || (Timeout == 0U)) { hrtc->State = HAL_RTC_STATE_TIMEOUT; return HAL_TIMEOUT; @@ -1893,14 +1893,15 @@ HAL_StatusTypeDef RTC_ExitInitMode(RTC_HandleTypeDef *hrtc) uint8_t RTC_ByteToBcd2(uint8_t number) { uint32_t bcdhigh = 0U; + uint8_t bcdlow = number; - while (number >= 10U) + while (bcdlow >= 10U) { bcdhigh++; - number -= 10U; + bcdlow -= (uint8_t)10; } - return ((uint8_t)(bcdhigh << 4U) | number); + return ((uint8_t)(bcdhigh << 4U) | bcdlow); } /** diff --git a/system/Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rtc_ex.c b/system/Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rtc_ex.c index c192ead77a..777de9d24b 100644 --- a/system/Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rtc_ex.c +++ b/system/Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rtc_ex.c @@ -733,7 +733,7 @@ HAL_StatusTypeDef HAL_RTCEx_PollForTimeStampEvent(RTC_HandleTypeDef *hrtc, uint3 { if (Timeout != HAL_MAX_DELAY) { - if ((Timeout == 0U) || ((HAL_GetTick() - tickstart) > Timeout)) + if (((HAL_GetTick() - tickstart) > Timeout) || (Timeout == 0U)) { hrtc->State = HAL_RTC_STATE_TIMEOUT; return HAL_TIMEOUT; @@ -777,7 +777,7 @@ HAL_StatusTypeDef HAL_RTCEx_PollForTamper1Event(RTC_HandleTypeDef *hrtc, uint32_ { if (Timeout != HAL_MAX_DELAY) { - if ((Timeout == 0U) || ((HAL_GetTick() - tickstart) > Timeout)) + if (((HAL_GetTick() - tickstart) > Timeout) || (Timeout == 0U)) { hrtc->State = HAL_RTC_STATE_TIMEOUT; return HAL_TIMEOUT; @@ -813,7 +813,7 @@ HAL_StatusTypeDef HAL_RTCEx_PollForTamper2Event(RTC_HandleTypeDef *hrtc, uint32_ { if (Timeout != HAL_MAX_DELAY) { - if ((Timeout == 0U) || ((HAL_GetTick() - tickstart) > Timeout)) + if (((HAL_GetTick() - tickstart) > Timeout) || (Timeout == 0U)) { hrtc->State = HAL_RTC_STATE_TIMEOUT; return HAL_TIMEOUT; @@ -847,7 +847,7 @@ HAL_StatusTypeDef HAL_RTCEx_PollForTamper3Event(RTC_HandleTypeDef *hrtc, uint32_ { if (Timeout != HAL_MAX_DELAY) { - if ((Timeout == 0U) || ((HAL_GetTick() - tickstart) > Timeout)) + if (((HAL_GetTick() - tickstart) > Timeout) || (Timeout == 0U)) { hrtc->State = HAL_RTC_STATE_TIMEOUT; return HAL_TIMEOUT; @@ -1217,7 +1217,7 @@ HAL_StatusTypeDef HAL_RTCEx_PollForWakeUpTimerEvent(RTC_HandleTypeDef *hrtc, uin { if (Timeout != HAL_MAX_DELAY) { - if ((Timeout == 0U) || ((HAL_GetTick() - tickstart) > Timeout)) + if (((HAL_GetTick() - tickstart) > Timeout) || (Timeout == 0U)) { hrtc->State = HAL_RTC_STATE_TIMEOUT; return HAL_TIMEOUT; @@ -1672,7 +1672,7 @@ HAL_StatusTypeDef HAL_RTCEx_EnableBypassShadow(RTC_HandleTypeDef *hrtc) __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc); /* Set the BYPSHAD bit */ - hrtc->Instance->CR |= (uint8_t)RTC_CR_BYPSHAD; + hrtc->Instance->CR |= (uint32_t)RTC_CR_BYPSHAD; /* Enable the write protection for RTC registers */ __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc); @@ -1705,7 +1705,7 @@ HAL_StatusTypeDef HAL_RTCEx_DisableBypassShadow(RTC_HandleTypeDef *hrtc) __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc); /* Reset the BYPSHAD bit */ - hrtc->Instance->CR &= (uint8_t)~RTC_CR_BYPSHAD; + hrtc->Instance->CR &= (uint32_t)~RTC_CR_BYPSHAD; /* Enable the write protection for RTC registers */ __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc); @@ -1773,7 +1773,7 @@ HAL_StatusTypeDef HAL_RTCEx_PollForAlarmBEvent(RTC_HandleTypeDef *hrtc, uint32_t { if (Timeout != HAL_MAX_DELAY) { - if ((Timeout == 0U) || ((HAL_GetTick() - tickstart) > Timeout)) + if (((HAL_GetTick() - tickstart) > Timeout) || (Timeout == 0U)) { hrtc->State = HAL_RTC_STATE_TIMEOUT; return HAL_TIMEOUT; diff --git a/system/Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_smartcard.c b/system/Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_smartcard.c index cad7b7977c..cae25f7595 100644 --- a/system/Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_smartcard.c +++ b/system/Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_smartcard.c @@ -2250,14 +2250,6 @@ static HAL_StatusTypeDef SMARTCARD_SetConfig(SMARTCARD_HandleTypeDef *hsmartcard ((uint32_t)hsmartcard->Init.WordLength)); MODIFY_REG(hsmartcard->Instance->CR1, USART_CR1_FIELDS, tmpreg); - /*-------------------------- USART CR2 Configuration -----------------------*/ - tmpreg = hsmartcard->Init.StopBits; - /* Synchronous mode is activated by default */ - tmpreg |= (uint32_t) USART_CR2_CLKEN | hsmartcard->Init.CLKPolarity; - tmpreg |= (uint32_t) hsmartcard->Init.CLKPhase | hsmartcard->Init.CLKLastBit; - tmpreg |= (uint32_t) hsmartcard->Init.TimeOutEnable; - MODIFY_REG(hsmartcard->Instance->CR2, USART_CR2_FIELDS, tmpreg); - /*-------------------------- USART CR3 Configuration -----------------------*/ /* Configure * - one-bit sampling method versus three samples' majority rule @@ -2275,6 +2267,14 @@ static HAL_StatusTypeDef SMARTCARD_SetConfig(SMARTCARD_HandleTypeDef *hsmartcard tmpreg = (hsmartcard->Init.Prescaler | ((uint32_t)hsmartcard->Init.GuardTime << USART_GTPR_GT_Pos)); MODIFY_REG(hsmartcard->Instance->GTPR, (uint16_t)(USART_GTPR_GT | USART_GTPR_PSC), (uint16_t)tmpreg); + /*-------------------------- USART CR2 Configuration -----------------------*/ + tmpreg = hsmartcard->Init.StopBits; + /* Synchronous mode is activated by default */ + tmpreg |= (uint32_t) USART_CR2_CLKEN | hsmartcard->Init.CLKPolarity; + tmpreg |= (uint32_t) hsmartcard->Init.CLKPhase | hsmartcard->Init.CLKLastBit; + tmpreg |= (uint32_t) hsmartcard->Init.TimeOutEnable; + MODIFY_REG(hsmartcard->Instance->CR2, USART_CR2_FIELDS, tmpreg); + /*-------------------------- USART RTOR Configuration ----------------------*/ tmpreg = ((uint32_t)hsmartcard->Init.BlockLength << USART_RTOR_BLEN_Pos); if (hsmartcard->Init.TimeOutEnable == SMARTCARD_TIMEOUT_ENABLE) diff --git a/system/Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_smbus.c b/system/Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_smbus.c index 06df19027c..a2fd8c8718 100644 --- a/system/Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_smbus.c +++ b/system/Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_smbus.c @@ -1543,55 +1543,50 @@ HAL_StatusTypeDef HAL_SMBUS_IsDeviceReady(SMBUS_HandleTypeDef *hsmbus, uint16_t /* Wait until STOPF flag is reset */ if (SMBUS_WaitOnFlagUntilTimeout(hsmbus, SMBUS_FLAG_STOPF, RESET, Timeout) != HAL_OK) { - return HAL_ERROR; + /* A non acknowledge appear during STOP Flag waiting process, a new trial must be performed */ + /* Clear STOP Flag */ + __HAL_SMBUS_CLEAR_FLAG(hsmbus, SMBUS_FLAG_STOPF); + + /* Reset the error code for next trial */ + hsmbus->ErrorCode = HAL_SMBUS_ERROR_NONE; } + else + { + /* A acknowledge appear during STOP Flag waiting process, this mean that device respond to its address */ - /* Clear STOP Flag */ - __HAL_SMBUS_CLEAR_FLAG(hsmbus, SMBUS_FLAG_STOPF); + /* Clear STOP Flag */ + __HAL_SMBUS_CLEAR_FLAG(hsmbus, SMBUS_FLAG_STOPF); - /* Device is ready */ - hsmbus->State = HAL_SMBUS_STATE_READY; + /* Device is ready */ + hsmbus->State = HAL_SMBUS_STATE_READY; - /* Process Unlocked */ - __HAL_UNLOCK(hsmbus); + /* Process Unlocked */ + __HAL_UNLOCK(hsmbus); - return HAL_OK; + return HAL_OK; + } } else { - /* Wait until STOPF flag is reset */ - if (SMBUS_WaitOnFlagUntilTimeout(hsmbus, SMBUS_FLAG_STOPF, RESET, Timeout) != HAL_OK) - { - return HAL_ERROR; - } + /* A non acknowledge is detected, this mean that device not respond to its address, + a new trial must be performed */ /* Clear NACK Flag */ __HAL_SMBUS_CLEAR_FLAG(hsmbus, SMBUS_FLAG_AF); - /* Clear STOP Flag, auto generated with autoend*/ - __HAL_SMBUS_CLEAR_FLAG(hsmbus, SMBUS_FLAG_STOPF); - } - - /* Check if the maximum allowed number of trials has been reached */ - if (SMBUS_Trials == Trials) - { - /* Generate Stop */ - hsmbus->Instance->CR2 |= I2C_CR2_STOP; - /* Wait until STOPF flag is reset */ - if (SMBUS_WaitOnFlagUntilTimeout(hsmbus, SMBUS_FLAG_STOPF, RESET, Timeout) != HAL_OK) + if (SMBUS_WaitOnFlagUntilTimeout(hsmbus, SMBUS_FLAG_STOPF, RESET, Timeout) == HAL_OK) { - return HAL_ERROR; + /* Clear STOP Flag, auto generated with autoend*/ + __HAL_SMBUS_CLEAR_FLAG(hsmbus, SMBUS_FLAG_STOPF); } - - /* Clear STOP Flag */ - __HAL_SMBUS_CLEAR_FLAG(hsmbus, SMBUS_FLAG_STOPF); } /* Increment Trials */ SMBUS_Trials++; } while (SMBUS_Trials < Trials); + /* Update SMBUS state */ hsmbus->State = HAL_SMBUS_STATE_READY; /* Update SMBUS error code */ @@ -1959,7 +1954,7 @@ static HAL_StatusTypeDef SMBUS_Master_ISR(SMBUS_HandleTypeDef *hsmbus, uint32_t /* Increment Buffer pointer */ hsmbus->pBuffPtr++; - if ((hsmbus->XferSize > 0U)) + if (hsmbus->XferSize > 0U) { hsmbus->XferSize--; hsmbus->XferCount--; @@ -2387,7 +2382,7 @@ static HAL_StatusTypeDef SMBUS_Slave_ISR(SMBUS_HandleTypeDef *hsmbus, uint32_t S /* Increment Buffer pointer */ hsmbus->pBuffPtr++; - if ((hsmbus->XferSize > 0U)) + if (hsmbus->XferSize > 0U) { hsmbus->XferSize--; hsmbus->XferCount--; diff --git a/system/Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c b/system/Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c index 79d06fee67..ce143e9440 100644 --- a/system/Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c +++ b/system/Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c @@ -44,7 +44,8 @@ (+++) Configure the DMA handle parameters (+++) Configure the DMA Tx or Rx Stream/Channel (+++) Associate the initialized hdma_tx(or _rx) handle to the hspi DMA Tx or Rx handle - (+++) Configure the priority and enable the NVIC for the transfer complete interrupt on the DMA Tx or Rx Stream/Channel + (+++) Configure the priority and enable the NVIC for the transfer complete interrupt on the DMA Tx + or Rx Stream/Channel (#) Program the Mode, BidirectionalMode , Data size, Baudrate Prescaler, NSS management, Clock polarity and phase, FirstBit and CRC configuration in the hspi Init structure. @@ -190,7 +191,8 @@ @note The max SPI frequency depend on SPI data size (4bits, 5bits,..., 8bits,...15bits, 16bits), SPI mode(2 Lines fullduplex, 2 lines RxOnly, 1 line TX/RX) and Process mode (Polling, IT, DMA). @note - (#) TX/RX processes are HAL_SPI_TransmitReceive(), HAL_SPI_TransmitReceive_IT() and HAL_SPI_TransmitReceive_DMA() + (#) TX/RX processes are HAL_SPI_TransmitReceive(), HAL_SPI_TransmitReceive_IT() and + HAL_SPI_TransmitReceive_DMA() (#) RX processes are HAL_SPI_Receive(), HAL_SPI_Receive_IT() and HAL_SPI_Receive_DMA() (#) TX processes are HAL_SPI_Transmit(), HAL_SPI_Transmit_IT() and HAL_SPI_Transmit_DMA() @@ -813,43 +815,40 @@ HAL_StatusTypeDef HAL_SPI_UnRegisterCallback(SPI_HandleTypeDef *hspi, HAL_SPI_Ca * @brief Transmit an amount of data in blocking mode. * @param hspi pointer to a SPI_HandleTypeDef structure that contains * the configuration information for SPI module. - * @param pData pointer to data buffer - * @param Size amount of data to be sent - * @param Timeout Timeout duration + * @param pData pointer to data buffer (u8 or u16 data elements) + * @param Size amount of data elements (u8 or u16) to be sent + * @param Timeout Timeout duration in ms * @retval HAL status */ -HAL_StatusTypeDef HAL_SPI_Transmit(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size, uint32_t Timeout) +HAL_StatusTypeDef HAL_SPI_Transmit(SPI_HandleTypeDef *hspi, const uint8_t *pData, uint16_t Size, uint32_t Timeout) { uint32_t tickstart; - HAL_StatusTypeDef errorcode = HAL_OK; uint16_t initial_TxXferCount; /* Check Direction parameter */ assert_param(IS_SPI_DIRECTION_2LINES_OR_1LINE(hspi->Init.Direction)); - /* Process Locked */ - __HAL_LOCK(hspi); - /* Init tickstart for timeout management*/ tickstart = HAL_GetTick(); initial_TxXferCount = Size; if (hspi->State != HAL_SPI_STATE_READY) { - errorcode = HAL_BUSY; - goto error; + return HAL_BUSY; } if ((pData == NULL) || (Size == 0U)) { - errorcode = HAL_ERROR; - goto error; + return HAL_ERROR; } + /* Process Locked */ + __HAL_LOCK(hspi); + /* Set the transaction information */ hspi->State = HAL_SPI_STATE_BUSY_TX; hspi->ErrorCode = HAL_SPI_ERROR_NONE; - hspi->pTxBuffPtr = (uint8_t *)pData; + hspi->pTxBuffPtr = (const uint8_t *)pData; hspi->TxXferSize = Size; hspi->TxXferCount = Size; @@ -888,7 +887,7 @@ HAL_StatusTypeDef HAL_SPI_Transmit(SPI_HandleTypeDef *hspi, uint8_t *pData, uint { if ((hspi->Init.Mode == SPI_MODE_SLAVE) || (initial_TxXferCount == 0x01U)) { - hspi->Instance->DR = *((uint16_t *)hspi->pTxBuffPtr); + hspi->Instance->DR = *((const uint16_t *)hspi->pTxBuffPtr); hspi->pTxBuffPtr += sizeof(uint16_t); hspi->TxXferCount--; } @@ -898,7 +897,7 @@ HAL_StatusTypeDef HAL_SPI_Transmit(SPI_HandleTypeDef *hspi, uint8_t *pData, uint /* Wait until TXE flag is set to send data */ if (__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_TXE)) { - hspi->Instance->DR = *((uint16_t *)hspi->pTxBuffPtr); + hspi->Instance->DR = *((const uint16_t *)hspi->pTxBuffPtr); hspi->pTxBuffPtr += sizeof(uint16_t); hspi->TxXferCount--; } @@ -907,9 +906,9 @@ HAL_StatusTypeDef HAL_SPI_Transmit(SPI_HandleTypeDef *hspi, uint8_t *pData, uint /* Timeout management */ if ((((HAL_GetTick() - tickstart) >= Timeout) && (Timeout != HAL_MAX_DELAY)) || (Timeout == 0U)) { - errorcode = HAL_TIMEOUT; hspi->State = HAL_SPI_STATE_READY; - goto error; + __HAL_UNLOCK(hspi); + return HAL_TIMEOUT; } } } @@ -922,13 +921,13 @@ HAL_StatusTypeDef HAL_SPI_Transmit(SPI_HandleTypeDef *hspi, uint8_t *pData, uint if (hspi->TxXferCount > 1U) { /* write on the data register in packing mode */ - hspi->Instance->DR = *((uint16_t *)hspi->pTxBuffPtr); + hspi->Instance->DR = *((const uint16_t *)hspi->pTxBuffPtr); hspi->pTxBuffPtr += sizeof(uint16_t); hspi->TxXferCount -= 2U; } else { - *((__IO uint8_t *)&hspi->Instance->DR) = (*hspi->pTxBuffPtr); + *((__IO uint8_t *)&hspi->Instance->DR) = *((const uint8_t *)hspi->pTxBuffPtr); hspi->pTxBuffPtr ++; hspi->TxXferCount--; } @@ -941,13 +940,13 @@ HAL_StatusTypeDef HAL_SPI_Transmit(SPI_HandleTypeDef *hspi, uint8_t *pData, uint if (hspi->TxXferCount > 1U) { /* write on the data register in packing mode */ - hspi->Instance->DR = *((uint16_t *)hspi->pTxBuffPtr); + hspi->Instance->DR = *((const uint16_t *)hspi->pTxBuffPtr); hspi->pTxBuffPtr += sizeof(uint16_t); hspi->TxXferCount -= 2U; } else { - *((__IO uint8_t *)&hspi->Instance->DR) = (*hspi->pTxBuffPtr); + *((__IO uint8_t *)&hspi->Instance->DR) = *((const uint8_t *)hspi->pTxBuffPtr); hspi->pTxBuffPtr++; hspi->TxXferCount--; } @@ -957,9 +956,9 @@ HAL_StatusTypeDef HAL_SPI_Transmit(SPI_HandleTypeDef *hspi, uint8_t *pData, uint /* Timeout management */ if ((((HAL_GetTick() - tickstart) >= Timeout) && (Timeout != HAL_MAX_DELAY)) || (Timeout == 0U)) { - errorcode = HAL_TIMEOUT; hspi->State = HAL_SPI_STATE_READY; - goto error; + __HAL_UNLOCK(hspi); + return HAL_TIMEOUT; } } } @@ -984,29 +983,31 @@ HAL_StatusTypeDef HAL_SPI_Transmit(SPI_HandleTypeDef *hspi, uint8_t *pData, uint __HAL_SPI_CLEAR_OVRFLAG(hspi); } + hspi->State = HAL_SPI_STATE_READY; + /* Process Unlocked */ + __HAL_UNLOCK(hspi); + if (hspi->ErrorCode != HAL_SPI_ERROR_NONE) { - errorcode = HAL_ERROR; + return HAL_ERROR; } else { - hspi->State = HAL_SPI_STATE_READY; + return HAL_OK; } - -error: - /* Process Unlocked */ - __HAL_UNLOCK(hspi); - return errorcode; } /** * @brief Receive an amount of data in blocking mode. * @param hspi pointer to a SPI_HandleTypeDef structure that contains * the configuration information for SPI module. - * @param pData pointer to data buffer - * @param Size amount of data to be received - * @param Timeout Timeout duration + * @param pData pointer to data buffer (u8 or u16 data elements) + * @param Size amount of data elements (u8 or u16) to be received + * @param Timeout Timeout duration in ms * @retval HAL status + * @note In master mode, if the direction is set to SPI_DIRECTION_2LINES + * the receive buffer is written to data register (DR) to generate + * clock pulses and receive data */ HAL_StatusTypeDef HAL_SPI_Receive(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size, uint32_t Timeout) { @@ -1016,12 +1017,15 @@ HAL_StatusTypeDef HAL_SPI_Receive(SPI_HandleTypeDef *hspi, uint8_t *pData, uint1 __IO uint8_t tmpreg8 = 0; #endif /* USE_SPI_CRC */ uint32_t tickstart; - HAL_StatusTypeDef errorcode = HAL_OK; if (hspi->State != HAL_SPI_STATE_READY) { - errorcode = HAL_BUSY; - goto error; + return HAL_BUSY; + } + + if ((pData == NULL) || (Size == 0U)) + { + return HAL_ERROR; } if ((hspi->Init.Mode == SPI_MODE_MASTER) && (hspi->Init.Direction == SPI_DIRECTION_2LINES)) @@ -1031,17 +1035,11 @@ HAL_StatusTypeDef HAL_SPI_Receive(SPI_HandleTypeDef *hspi, uint8_t *pData, uint1 return HAL_SPI_TransmitReceive(hspi, pData, pData, Size, Timeout); } - /* Process Locked */ - __HAL_LOCK(hspi); - /* Init tickstart for timeout management*/ tickstart = HAL_GetTick(); - if ((pData == NULL) || (Size == 0U)) - { - errorcode = HAL_ERROR; - goto error; - } + /* Process Locked */ + __HAL_LOCK(hspi); /* Set the transaction information */ hspi->State = HAL_SPI_STATE_BUSY_RX; @@ -1113,9 +1111,9 @@ HAL_StatusTypeDef HAL_SPI_Receive(SPI_HandleTypeDef *hspi, uint8_t *pData, uint1 /* Timeout management */ if ((((HAL_GetTick() - tickstart) >= Timeout) && (Timeout != HAL_MAX_DELAY)) || (Timeout == 0U)) { - errorcode = HAL_TIMEOUT; hspi->State = HAL_SPI_STATE_READY; - goto error; + __HAL_UNLOCK(hspi); + return HAL_TIMEOUT; } } } @@ -1137,9 +1135,9 @@ HAL_StatusTypeDef HAL_SPI_Receive(SPI_HandleTypeDef *hspi, uint8_t *pData, uint1 /* Timeout management */ if ((((HAL_GetTick() - tickstart) >= Timeout) && (Timeout != HAL_MAX_DELAY)) || (Timeout == 0U)) { - errorcode = HAL_TIMEOUT; hspi->State = HAL_SPI_STATE_READY; - goto error; + __HAL_UNLOCK(hspi); + return HAL_TIMEOUT; } } } @@ -1156,8 +1154,8 @@ HAL_StatusTypeDef HAL_SPI_Receive(SPI_HandleTypeDef *hspi, uint8_t *pData, uint1 if (SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_RXNE, SET, Timeout, tickstart) != HAL_OK) { /* the latest data has not been received */ - errorcode = HAL_TIMEOUT; - goto error; + __HAL_UNLOCK(hspi); + return HAL_TIMEOUT; } /* Receive last data in 16 Bit mode */ @@ -1175,8 +1173,9 @@ HAL_StatusTypeDef HAL_SPI_Receive(SPI_HandleTypeDef *hspi, uint8_t *pData, uint1 if (SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_RXNE, SET, Timeout, tickstart) != HAL_OK) { SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_CRC); - errorcode = HAL_TIMEOUT; - goto error; + hspi->State = HAL_SPI_STATE_READY; + __HAL_UNLOCK(hspi); + return HAL_TIMEOUT; } /* Read CRC to Flush DR and RXNE flag */ @@ -1202,8 +1201,9 @@ HAL_StatusTypeDef HAL_SPI_Receive(SPI_HandleTypeDef *hspi, uint8_t *pData, uint1 { /* Error on the CRC reception */ SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_CRC); - errorcode = HAL_TIMEOUT; - goto error; + hspi->State = HAL_SPI_STATE_READY; + __HAL_UNLOCK(hspi); + return HAL_TIMEOUT; } /* Read 8bit CRC again in case of 16bit CRC in 8bit Data mode */ tmpreg8 = *ptmpreg8; @@ -1229,32 +1229,31 @@ HAL_StatusTypeDef HAL_SPI_Receive(SPI_HandleTypeDef *hspi, uint8_t *pData, uint1 } #endif /* USE_SPI_CRC */ + hspi->State = HAL_SPI_STATE_READY; + /* Unlock the process */ + __HAL_UNLOCK(hspi); if (hspi->ErrorCode != HAL_SPI_ERROR_NONE) { - errorcode = HAL_ERROR; + return HAL_ERROR; } else { - hspi->State = HAL_SPI_STATE_READY; + return HAL_OK; } - -error : - __HAL_UNLOCK(hspi); - return errorcode; } /** * @brief Transmit and Receive an amount of data in blocking mode. * @param hspi pointer to a SPI_HandleTypeDef structure that contains * the configuration information for SPI module. - * @param pTxData pointer to transmission data buffer - * @param pRxData pointer to reception data buffer - * @param Size amount of data to be sent and received - * @param Timeout Timeout duration + * @param pTxData pointer to transmission data buffer (u8 or u16 data elements) + * @param pRxData pointer to reception data buffer (u8 or u16 data elements) + * @param Size amount of data elements (u8 or u16) to be sent and received + * @param Timeout Timeout duration in ms * @retval HAL status */ -HAL_StatusTypeDef HAL_SPI_TransmitReceive(SPI_HandleTypeDef *hspi, uint8_t *pTxData, uint8_t *pRxData, uint16_t Size, - uint32_t Timeout) +HAL_StatusTypeDef HAL_SPI_TransmitReceive(SPI_HandleTypeDef *hspi, const uint8_t *pTxData, uint8_t *pRxData, + uint16_t Size, uint32_t Timeout) { uint16_t initial_TxXferCount; uint16_t initial_RxXferCount; @@ -1271,14 +1270,10 @@ HAL_StatusTypeDef HAL_SPI_TransmitReceive(SPI_HandleTypeDef *hspi, uint8_t *pTxD /* Variable used to alternate Rx and Tx during transfer */ uint32_t txallowed = 1U; - HAL_StatusTypeDef errorcode = HAL_OK; /* Check Direction parameter */ assert_param(IS_SPI_DIRECTION_2LINES(hspi->Init.Direction)); - /* Process Locked */ - __HAL_LOCK(hspi); - /* Init tickstart for timeout management*/ tickstart = HAL_GetTick(); @@ -1293,18 +1288,20 @@ HAL_StatusTypeDef HAL_SPI_TransmitReceive(SPI_HandleTypeDef *hspi, uint8_t *pTxD #endif /* USE_SPI_CRC */ if (!((tmp_state == HAL_SPI_STATE_READY) || \ - ((tmp_mode == SPI_MODE_MASTER) && (hspi->Init.Direction == SPI_DIRECTION_2LINES) && (tmp_state == HAL_SPI_STATE_BUSY_RX)))) + ((tmp_mode == SPI_MODE_MASTER) && (hspi->Init.Direction == SPI_DIRECTION_2LINES) && + (tmp_state == HAL_SPI_STATE_BUSY_RX)))) { - errorcode = HAL_BUSY; - goto error; + return HAL_BUSY; } if ((pTxData == NULL) || (pRxData == NULL) || (Size == 0U)) { - errorcode = HAL_ERROR; - goto error; + return HAL_ERROR; } + /* Process Locked */ + __HAL_LOCK(hspi); + /* Don't overwrite in case of HAL_SPI_STATE_BUSY_RX */ if (hspi->State != HAL_SPI_STATE_BUSY_RX) { @@ -1316,7 +1313,7 @@ HAL_StatusTypeDef HAL_SPI_TransmitReceive(SPI_HandleTypeDef *hspi, uint8_t *pTxD hspi->pRxBuffPtr = (uint8_t *)pRxData; hspi->RxXferCount = Size; hspi->RxXferSize = Size; - hspi->pTxBuffPtr = (uint8_t *)pTxData; + hspi->pTxBuffPtr = (const uint8_t *)pTxData; hspi->TxXferCount = Size; hspi->TxXferSize = Size; @@ -1356,7 +1353,7 @@ HAL_StatusTypeDef HAL_SPI_TransmitReceive(SPI_HandleTypeDef *hspi, uint8_t *pTxD { if ((hspi->Init.Mode == SPI_MODE_SLAVE) || (initial_TxXferCount == 0x01U)) { - hspi->Instance->DR = *((uint16_t *)hspi->pTxBuffPtr); + hspi->Instance->DR = *((const uint16_t *)hspi->pTxBuffPtr); hspi->pTxBuffPtr += sizeof(uint16_t); hspi->TxXferCount--; @@ -1379,7 +1376,7 @@ HAL_StatusTypeDef HAL_SPI_TransmitReceive(SPI_HandleTypeDef *hspi, uint8_t *pTxD /* Check TXE flag */ if ((__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_TXE)) && (hspi->TxXferCount > 0U) && (txallowed == 1U)) { - hspi->Instance->DR = *((uint16_t *)hspi->pTxBuffPtr); + hspi->Instance->DR = *((const uint16_t *)hspi->pTxBuffPtr); hspi->pTxBuffPtr += sizeof(uint16_t); hspi->TxXferCount--; /* Next Data is a reception (Rx). Tx not allowed */ @@ -1410,9 +1407,9 @@ HAL_StatusTypeDef HAL_SPI_TransmitReceive(SPI_HandleTypeDef *hspi, uint8_t *pTxD } if (((HAL_GetTick() - tickstart) >= Timeout) && (Timeout != HAL_MAX_DELAY)) { - errorcode = HAL_TIMEOUT; hspi->State = HAL_SPI_STATE_READY; - goto error; + __HAL_UNLOCK(hspi); + return HAL_TIMEOUT; } } } @@ -1423,13 +1420,13 @@ HAL_StatusTypeDef HAL_SPI_TransmitReceive(SPI_HandleTypeDef *hspi, uint8_t *pTxD { if (hspi->TxXferCount > 1U) { - hspi->Instance->DR = *((uint16_t *)hspi->pTxBuffPtr); + hspi->Instance->DR = *((const uint16_t *)hspi->pTxBuffPtr); hspi->pTxBuffPtr += sizeof(uint16_t); hspi->TxXferCount -= 2U; } else { - *(__IO uint8_t *)&hspi->Instance->DR = (*hspi->pTxBuffPtr); + *(__IO uint8_t *)&hspi->Instance->DR = *((const uint8_t *)hspi->pTxBuffPtr); hspi->pTxBuffPtr++; hspi->TxXferCount--; @@ -1454,13 +1451,13 @@ HAL_StatusTypeDef HAL_SPI_TransmitReceive(SPI_HandleTypeDef *hspi, uint8_t *pTxD { if (hspi->TxXferCount > 1U) { - hspi->Instance->DR = *((uint16_t *)hspi->pTxBuffPtr); + hspi->Instance->DR = *((const uint16_t *)hspi->pTxBuffPtr); hspi->pTxBuffPtr += sizeof(uint16_t); hspi->TxXferCount -= 2U; } else { - *(__IO uint8_t *)&hspi->Instance->DR = (*hspi->pTxBuffPtr); + *(__IO uint8_t *)&hspi->Instance->DR = *((const uint8_t *)hspi->pTxBuffPtr); hspi->pTxBuffPtr++; hspi->TxXferCount--; } @@ -1506,9 +1503,9 @@ HAL_StatusTypeDef HAL_SPI_TransmitReceive(SPI_HandleTypeDef *hspi, uint8_t *pTxD } if ((((HAL_GetTick() - tickstart) >= Timeout) && ((Timeout != HAL_MAX_DELAY))) || (Timeout == 0U)) { - errorcode = HAL_TIMEOUT; hspi->State = HAL_SPI_STATE_READY; - goto error; + __HAL_UNLOCK(hspi); + return HAL_TIMEOUT; } } } @@ -1522,8 +1519,9 @@ HAL_StatusTypeDef HAL_SPI_TransmitReceive(SPI_HandleTypeDef *hspi, uint8_t *pTxD { /* Error on the CRC reception */ SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_CRC); - errorcode = HAL_TIMEOUT; - goto error; + hspi->State = HAL_SPI_STATE_READY; + __HAL_UNLOCK(hspi); + return HAL_TIMEOUT; } /* Read CRC */ if (hspi->Init.DataSize == SPI_DATASIZE_16BIT) @@ -1548,8 +1546,9 @@ HAL_StatusTypeDef HAL_SPI_TransmitReceive(SPI_HandleTypeDef *hspi, uint8_t *pTxD { /* Error on the CRC reception */ SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_CRC); - errorcode = HAL_TIMEOUT; - goto error; + hspi->State = HAL_SPI_STATE_READY; + __HAL_UNLOCK(hspi); + return HAL_TIMEOUT; } /* Read 8bit CRC again in case of 16bit CRC in 8bit Data mode */ tmpreg8 = *ptmpreg8; @@ -1565,43 +1564,44 @@ HAL_StatusTypeDef HAL_SPI_TransmitReceive(SPI_HandleTypeDef *hspi, uint8_t *pTxD SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_CRC); /* Clear CRC Flag */ __HAL_SPI_CLEAR_CRCERRFLAG(hspi); - - errorcode = HAL_ERROR; + __HAL_UNLOCK(hspi); + return HAL_ERROR; } #endif /* USE_SPI_CRC */ /* Check the end of the transaction */ if (SPI_EndRxTxTransaction(hspi, Timeout, tickstart) != HAL_OK) { - errorcode = HAL_ERROR; hspi->ErrorCode = HAL_SPI_ERROR_FLAG; + __HAL_UNLOCK(hspi); + return HAL_ERROR; } + + hspi->State = HAL_SPI_STATE_READY; + /* Unlock the process */ + __HAL_UNLOCK(hspi); + if (hspi->ErrorCode != HAL_SPI_ERROR_NONE) { - errorcode = HAL_ERROR; + return HAL_ERROR; } else { - hspi->State = HAL_SPI_STATE_READY; + return HAL_OK; } - -error : - __HAL_UNLOCK(hspi); - return errorcode; } /** * @brief Transmit an amount of data in non-blocking mode with Interrupt. * @param hspi pointer to a SPI_HandleTypeDef structure that contains * the configuration information for SPI module. - * @param pData pointer to data buffer - * @param Size amount of data to be sent + * @param pData pointer to data buffer (u8 or u16 data elements) + * @param Size amount of data elements (u8 or u16) to be sent * @retval HAL status */ -HAL_StatusTypeDef HAL_SPI_Transmit_IT(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size) +HAL_StatusTypeDef HAL_SPI_Transmit_IT(SPI_HandleTypeDef *hspi, const uint8_t *pData, uint16_t Size) { - HAL_StatusTypeDef errorcode = HAL_OK; /* Check Direction parameter */ assert_param(IS_SPI_DIRECTION_2LINES_OR_1LINE(hspi->Init.Direction)); @@ -1609,14 +1609,12 @@ HAL_StatusTypeDef HAL_SPI_Transmit_IT(SPI_HandleTypeDef *hspi, uint8_t *pData, u if ((pData == NULL) || (Size == 0U)) { - errorcode = HAL_ERROR; - goto error; + return HAL_ERROR; } if (hspi->State != HAL_SPI_STATE_READY) { - errorcode = HAL_BUSY; - goto error; + return HAL_BUSY; } /* Process Locked */ @@ -1625,7 +1623,7 @@ HAL_StatusTypeDef HAL_SPI_Transmit_IT(SPI_HandleTypeDef *hspi, uint8_t *pData, u /* Set the transaction information */ hspi->State = HAL_SPI_STATE_BUSY_TX; hspi->ErrorCode = HAL_SPI_ERROR_NONE; - hspi->pTxBuffPtr = (uint8_t *)pData; + hspi->pTxBuffPtr = (const uint8_t *)pData; hspi->TxXferSize = Size; hspi->TxXferCount = Size; @@ -1673,27 +1671,28 @@ HAL_StatusTypeDef HAL_SPI_Transmit_IT(SPI_HandleTypeDef *hspi, uint8_t *pData, u /* Enable TXE and ERR interrupt */ __HAL_SPI_ENABLE_IT(hspi, (SPI_IT_TXE | SPI_IT_ERR)); -error : - return errorcode; + return HAL_OK; } /** * @brief Receive an amount of data in non-blocking mode with Interrupt. * @param hspi pointer to a SPI_HandleTypeDef structure that contains * the configuration information for SPI module. - * @param pData pointer to data buffer - * @param Size amount of data to be sent + * @param pData pointer to data buffer (u8 or u16 data elements) + * @param Size amount of data elements (u8 or u16) to be received * @retval HAL status */ HAL_StatusTypeDef HAL_SPI_Receive_IT(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size) { - HAL_StatusTypeDef errorcode = HAL_OK; - if (hspi->State != HAL_SPI_STATE_READY) { - errorcode = HAL_BUSY; - goto error; + return HAL_BUSY; + } + + if ((pData == NULL) || (Size == 0U)) + { + return HAL_ERROR; } if ((hspi->Init.Direction == SPI_DIRECTION_2LINES) && (hspi->Init.Mode == SPI_MODE_MASTER)) @@ -1704,12 +1703,6 @@ HAL_StatusTypeDef HAL_SPI_Receive_IT(SPI_HandleTypeDef *hspi, uint8_t *pData, ui } - if ((pData == NULL) || (Size == 0U)) - { - errorcode = HAL_ERROR; - goto error; - } - /* Process Locked */ __HAL_LOCK(hspi); @@ -1781,24 +1774,23 @@ HAL_StatusTypeDef HAL_SPI_Receive_IT(SPI_HandleTypeDef *hspi, uint8_t *pData, ui /* Enable RXNE and ERR interrupt */ __HAL_SPI_ENABLE_IT(hspi, (SPI_IT_RXNE | SPI_IT_ERR)); -error : - return errorcode; + return HAL_OK; } /** * @brief Transmit and Receive an amount of data in non-blocking mode with Interrupt. * @param hspi pointer to a SPI_HandleTypeDef structure that contains * the configuration information for SPI module. - * @param pTxData pointer to transmission data buffer - * @param pRxData pointer to reception data buffer - * @param Size amount of data to be sent and received + * @param pTxData pointer to transmission data buffer (u8 or u16 data elements) + * @param pRxData pointer to reception data buffer (u8 or u16 data elements) + * @param Size amount of data elements (u8 or u16) to be sent and received * @retval HAL status */ -HAL_StatusTypeDef HAL_SPI_TransmitReceive_IT(SPI_HandleTypeDef *hspi, uint8_t *pTxData, uint8_t *pRxData, uint16_t Size) +HAL_StatusTypeDef HAL_SPI_TransmitReceive_IT(SPI_HandleTypeDef *hspi, const uint8_t *pTxData, uint8_t *pRxData, + uint16_t Size) { uint32_t tmp_mode; HAL_SPI_StateTypeDef tmp_state; - HAL_StatusTypeDef errorcode = HAL_OK; /* Check Direction parameter */ assert_param(IS_SPI_DIRECTION_2LINES(hspi->Init.Direction)); @@ -1808,16 +1800,15 @@ HAL_StatusTypeDef HAL_SPI_TransmitReceive_IT(SPI_HandleTypeDef *hspi, uint8_t *p tmp_mode = hspi->Init.Mode; if (!((tmp_state == HAL_SPI_STATE_READY) || \ - ((tmp_mode == SPI_MODE_MASTER) && (hspi->Init.Direction == SPI_DIRECTION_2LINES) && (tmp_state == HAL_SPI_STATE_BUSY_RX)))) + ((tmp_mode == SPI_MODE_MASTER) && (hspi->Init.Direction == SPI_DIRECTION_2LINES) && + (tmp_state == HAL_SPI_STATE_BUSY_RX)))) { - errorcode = HAL_BUSY; - goto error; + return HAL_BUSY; } if ((pTxData == NULL) || (pRxData == NULL) || (Size == 0U)) { - errorcode = HAL_ERROR; - goto error; + return HAL_ERROR; } /* Process locked */ @@ -1831,7 +1822,7 @@ HAL_StatusTypeDef HAL_SPI_TransmitReceive_IT(SPI_HandleTypeDef *hspi, uint8_t *p /* Set the transaction information */ hspi->ErrorCode = HAL_SPI_ERROR_NONE; - hspi->pTxBuffPtr = (uint8_t *)pTxData; + hspi->pTxBuffPtr = (const uint8_t *)pTxData; hspi->TxXferSize = Size; hspi->TxXferCount = Size; hspi->pRxBuffPtr = (uint8_t *)pRxData; @@ -1892,21 +1883,19 @@ HAL_StatusTypeDef HAL_SPI_TransmitReceive_IT(SPI_HandleTypeDef *hspi, uint8_t *p /* Enable TXE, RXNE and ERR interrupt */ __HAL_SPI_ENABLE_IT(hspi, (SPI_IT_TXE | SPI_IT_RXNE | SPI_IT_ERR)); -error : - return errorcode; + return HAL_OK; } /** * @brief Transmit an amount of data in non-blocking mode with DMA. * @param hspi pointer to a SPI_HandleTypeDef structure that contains * the configuration information for SPI module. - * @param pData pointer to data buffer - * @param Size amount of data to be sent + * @param pData pointer to data buffer (u8 or u16 data elements) + * @param Size amount of data elements (u8 or u16) to be sent * @retval HAL status */ -HAL_StatusTypeDef HAL_SPI_Transmit_DMA(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size) +HAL_StatusTypeDef HAL_SPI_Transmit_DMA(SPI_HandleTypeDef *hspi, const uint8_t *pData, uint16_t Size) { - HAL_StatusTypeDef errorcode = HAL_OK; /* Check tx dma handle */ assert_param(IS_SPI_DMA_HANDLE(hspi->hdmatx)); @@ -1914,25 +1903,23 @@ HAL_StatusTypeDef HAL_SPI_Transmit_DMA(SPI_HandleTypeDef *hspi, uint8_t *pData, /* Check Direction parameter */ assert_param(IS_SPI_DIRECTION_2LINES_OR_1LINE(hspi->Init.Direction)); - /* Process Locked */ - __HAL_LOCK(hspi); - if (hspi->State != HAL_SPI_STATE_READY) { - errorcode = HAL_BUSY; - goto error; + return HAL_BUSY; } if ((pData == NULL) || (Size == 0U)) { - errorcode = HAL_ERROR; - goto error; + return HAL_ERROR; } + /* Process Locked */ + __HAL_LOCK(hspi); + /* Set the transaction information */ hspi->State = HAL_SPI_STATE_BUSY_TX; hspi->ErrorCode = HAL_SPI_ERROR_NONE; - hspi->pTxBuffPtr = (uint8_t *)pData; + hspi->pTxBuffPtr = (const uint8_t *)pData; hspi->TxXferSize = Size; hspi->TxXferCount = Size; @@ -1994,9 +1981,9 @@ HAL_StatusTypeDef HAL_SPI_Transmit_DMA(SPI_HandleTypeDef *hspi, uint8_t *pData, { /* Update SPI error code */ SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_DMA); - errorcode = HAL_ERROR; - - goto error; + /* Process Unlocked */ + __HAL_UNLOCK(hspi); + return HAL_ERROR; } /* Check if the SPI is already enabled */ @@ -2006,16 +1993,16 @@ HAL_StatusTypeDef HAL_SPI_Transmit_DMA(SPI_HandleTypeDef *hspi, uint8_t *pData, __HAL_SPI_ENABLE(hspi); } + /* Process Unlocked */ + __HAL_UNLOCK(hspi); + /* Enable the SPI Error Interrupt Bit */ __HAL_SPI_ENABLE_IT(hspi, (SPI_IT_ERR)); /* Enable Tx DMA Request */ SET_BIT(hspi->Instance->CR2, SPI_CR2_TXDMAEN); -error : - /* Process Unlocked */ - __HAL_UNLOCK(hspi); - return errorcode; + return HAL_OK; } /** @@ -2023,22 +2010,24 @@ error : * @note In case of MASTER mode and SPI_DIRECTION_2LINES direction, hdmatx shall be defined. * @param hspi pointer to a SPI_HandleTypeDef structure that contains * the configuration information for SPI module. - * @param pData pointer to data buffer + * @param pData pointer to data buffer (u8 or u16 data elements) * @note When the CRC feature is enabled the pData Length must be Size + 1. - * @param Size amount of data to be sent + * @param Size amount of data elements (u8 or u16) to be received * @retval HAL status */ HAL_StatusTypeDef HAL_SPI_Receive_DMA(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size) { - HAL_StatusTypeDef errorcode = HAL_OK; - /* Check rx dma handle */ assert_param(IS_SPI_DMA_HANDLE(hspi->hdmarx)); if (hspi->State != HAL_SPI_STATE_READY) { - errorcode = HAL_BUSY; - goto error; + return HAL_BUSY; + } + + if ((pData == NULL) || (Size == 0U)) + { + return HAL_ERROR; } if ((hspi->Init.Direction == SPI_DIRECTION_2LINES) && (hspi->Init.Mode == SPI_MODE_MASTER)) @@ -2055,12 +2044,6 @@ HAL_StatusTypeDef HAL_SPI_Receive_DMA(SPI_HandleTypeDef *hspi, uint8_t *pData, u /* Process Locked */ __HAL_LOCK(hspi); - if ((pData == NULL) || (Size == 0U)) - { - errorcode = HAL_ERROR; - goto error; - } - /* Set the transaction information */ hspi->State = HAL_SPI_STATE_BUSY_RX; hspi->ErrorCode = HAL_SPI_ERROR_NONE; @@ -2095,8 +2078,9 @@ HAL_StatusTypeDef HAL_SPI_Receive_DMA(SPI_HandleTypeDef *hspi, uint8_t *pData, u if ((hspi->Init.DataSize <= SPI_DATASIZE_8BIT) && (hspi->hdmarx->Init.MemDataAlignment == DMA_MDATAALIGN_HALFWORD)) { /* Restriction the DMA data received is not allowed in this mode */ - errorcode = HAL_ERROR; - goto error; + /* Process Unlocked */ + __HAL_UNLOCK(hspi); + return HAL_ERROR; } #endif /* STM32F302xC || STM32F303xC || STM32F373xC || STM32F358xx || STM32F378xx */ @@ -2147,9 +2131,9 @@ HAL_StatusTypeDef HAL_SPI_Receive_DMA(SPI_HandleTypeDef *hspi, uint8_t *pData, u { /* Update SPI error code */ SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_DMA); - errorcode = HAL_ERROR; - - goto error; + /* Process Unlocked */ + __HAL_UNLOCK(hspi); + return HAL_ERROR; } /* Check if the SPI is already enabled */ @@ -2159,34 +2143,33 @@ HAL_StatusTypeDef HAL_SPI_Receive_DMA(SPI_HandleTypeDef *hspi, uint8_t *pData, u __HAL_SPI_ENABLE(hspi); } + /* Process Unlocked */ + __HAL_UNLOCK(hspi); + /* Enable the SPI Error Interrupt Bit */ __HAL_SPI_ENABLE_IT(hspi, (SPI_IT_ERR)); /* Enable Rx DMA Request */ SET_BIT(hspi->Instance->CR2, SPI_CR2_RXDMAEN); -error: - /* Process Unlocked */ - __HAL_UNLOCK(hspi); - return errorcode; + return HAL_OK; } /** * @brief Transmit and Receive an amount of data in non-blocking mode with DMA. * @param hspi pointer to a SPI_HandleTypeDef structure that contains * the configuration information for SPI module. - * @param pTxData pointer to transmission data buffer - * @param pRxData pointer to reception data buffer + * @param pTxData pointer to transmission data buffer (u8 or u16 data elements) + * @param pRxData pointer to reception data buffer (u8 or u16 data elements) * @note When the CRC feature is enabled the pRxData Length must be Size + 1 - * @param Size amount of data to be sent + * @param Size amount of data elements (u8 or u16) to be sent and received * @retval HAL status */ -HAL_StatusTypeDef HAL_SPI_TransmitReceive_DMA(SPI_HandleTypeDef *hspi, uint8_t *pTxData, uint8_t *pRxData, +HAL_StatusTypeDef HAL_SPI_TransmitReceive_DMA(SPI_HandleTypeDef *hspi, const uint8_t *pTxData, uint8_t *pRxData, uint16_t Size) { uint32_t tmp_mode; HAL_SPI_StateTypeDef tmp_state; - HAL_StatusTypeDef errorcode = HAL_OK; /* Check rx & tx dma handles */ assert_param(IS_SPI_DMA_HANDLE(hspi->hdmarx)); @@ -2195,26 +2178,25 @@ HAL_StatusTypeDef HAL_SPI_TransmitReceive_DMA(SPI_HandleTypeDef *hspi, uint8_t * /* Check Direction parameter */ assert_param(IS_SPI_DIRECTION_2LINES(hspi->Init.Direction)); - /* Process locked */ - __HAL_LOCK(hspi); - /* Init temporary variables */ tmp_state = hspi->State; tmp_mode = hspi->Init.Mode; if (!((tmp_state == HAL_SPI_STATE_READY) || - ((tmp_mode == SPI_MODE_MASTER) && (hspi->Init.Direction == SPI_DIRECTION_2LINES) && (tmp_state == HAL_SPI_STATE_BUSY_RX)))) + ((tmp_mode == SPI_MODE_MASTER) && (hspi->Init.Direction == SPI_DIRECTION_2LINES) && + (tmp_state == HAL_SPI_STATE_BUSY_RX)))) { - errorcode = HAL_BUSY; - goto error; + return HAL_BUSY; } if ((pTxData == NULL) || (pRxData == NULL) || (Size == 0U)) { - errorcode = HAL_ERROR; - goto error; + return HAL_ERROR; } + /* Process locked */ + __HAL_LOCK(hspi); + /* Don't overwrite in case of HAL_SPI_STATE_BUSY_RX */ if (hspi->State != HAL_SPI_STATE_BUSY_RX) { @@ -2223,7 +2205,7 @@ HAL_StatusTypeDef HAL_SPI_TransmitReceive_DMA(SPI_HandleTypeDef *hspi, uint8_t * /* Set the transaction information */ hspi->ErrorCode = HAL_SPI_ERROR_NONE; - hspi->pTxBuffPtr = (uint8_t *)pTxData; + hspi->pTxBuffPtr = (const uint8_t *)pTxData; hspi->TxXferSize = Size; hspi->TxXferCount = Size; hspi->pRxBuffPtr = (uint8_t *)pRxData; @@ -2247,8 +2229,9 @@ HAL_StatusTypeDef HAL_SPI_TransmitReceive_DMA(SPI_HandleTypeDef *hspi, uint8_t * if ((hspi->Init.DataSize <= SPI_DATASIZE_8BIT) && (hspi->hdmarx->Init.MemDataAlignment == DMA_MDATAALIGN_HALFWORD)) { /* Restriction the DMA data received is not allowed in this mode */ - errorcode = HAL_ERROR; - goto error; + /* Process Unlocked */ + __HAL_UNLOCK(hspi); + return HAL_ERROR; } #endif /* STM32F302xC || STM32F303xC || STM32F373xC || STM32F358xx || STM32F378xx */ @@ -2324,9 +2307,9 @@ HAL_StatusTypeDef HAL_SPI_TransmitReceive_DMA(SPI_HandleTypeDef *hspi, uint8_t * { /* Update SPI error code */ SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_DMA); - errorcode = HAL_ERROR; - - goto error; + /* Process Unlocked */ + __HAL_UNLOCK(hspi); + return HAL_ERROR; } /* Enable Rx DMA Request */ @@ -2345,9 +2328,9 @@ HAL_StatusTypeDef HAL_SPI_TransmitReceive_DMA(SPI_HandleTypeDef *hspi, uint8_t * { /* Update SPI error code */ SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_DMA); - errorcode = HAL_ERROR; - - goto error; + /* Process Unlocked */ + __HAL_UNLOCK(hspi); + return HAL_ERROR; } /* Check if the SPI is already enabled */ @@ -2356,16 +2339,17 @@ HAL_StatusTypeDef HAL_SPI_TransmitReceive_DMA(SPI_HandleTypeDef *hspi, uint8_t * /* Enable SPI peripheral */ __HAL_SPI_ENABLE(hspi); } + + /* Process Unlocked */ + __HAL_UNLOCK(hspi); + /* Enable the SPI Error Interrupt Bit */ __HAL_SPI_ENABLE_IT(hspi, (SPI_IT_ERR)); /* Enable Tx DMA Request */ SET_BIT(hspi->Instance->CR2, SPI_CR2_TXDMAEN); -error : - /* Process Unlocked */ - __HAL_UNLOCK(hspi); - return errorcode; + return HAL_OK; } /** @@ -2458,7 +2442,8 @@ HAL_StatusTypeDef HAL_SPI_Abort(SPI_HandleTypeDef *hspi) __HAL_SPI_DISABLE(hspi); /* Empty the FRLVL fifo */ - if (SPI_WaitFifoStateUntilTimeout(hspi, SPI_FLAG_FRLVL, SPI_FRLVL_EMPTY, SPI_DEFAULT_TIMEOUT, HAL_GetTick()) != HAL_OK) + if (SPI_WaitFifoStateUntilTimeout(hspi, SPI_FLAG_FRLVL, SPI_FRLVL_EMPTY, SPI_DEFAULT_TIMEOUT, + HAL_GetTick()) != HAL_OK) { hspi->ErrorCode = HAL_SPI_ERROR_ABORT; } @@ -2491,7 +2476,8 @@ HAL_StatusTypeDef HAL_SPI_Abort(SPI_HandleTypeDef *hspi) } /* Empty the FRLVL fifo */ - if (SPI_WaitFifoStateUntilTimeout(hspi, SPI_FLAG_FRLVL, SPI_FRLVL_EMPTY, SPI_DEFAULT_TIMEOUT, HAL_GetTick()) != HAL_OK) + if (SPI_WaitFifoStateUntilTimeout(hspi, SPI_FLAG_FRLVL, SPI_FRLVL_EMPTY, SPI_DEFAULT_TIMEOUT, + HAL_GetTick()) != HAL_OK) { hspi->ErrorCode = HAL_SPI_ERROR_ABORT; } @@ -2746,9 +2732,11 @@ HAL_StatusTypeDef HAL_SPI_DMAStop(SPI_HandleTypeDef *hspi) { HAL_StatusTypeDef errorcode = HAL_OK; /* The Lock is not implemented on this API to allow the user application - to call the HAL SPI API under callbacks HAL_SPI_TxCpltCallback() or HAL_SPI_RxCpltCallback() or HAL_SPI_TxRxCpltCallback(): + to call the HAL SPI API under callbacks HAL_SPI_TxCpltCallback() or HAL_SPI_RxCpltCallback() or + HAL_SPI_TxRxCpltCallback(): when calling HAL_DMA_Abort() API the DMA TX/RX Transfer complete interrupt is generated - and the correspond call back is executed HAL_SPI_TxCpltCallback() or HAL_SPI_RxCpltCallback() or HAL_SPI_TxRxCpltCallback() + and the correspond call back is executed HAL_SPI_TxCpltCallback() or HAL_SPI_RxCpltCallback() or + HAL_SPI_TxRxCpltCallback() */ /* Abort the SPI DMA tx Stream/Channel */ @@ -3038,7 +3026,7 @@ __weak void HAL_SPI_AbortCpltCallback(SPI_HandleTypeDef *hspi) * the configuration information for SPI module. * @retval SPI state */ -HAL_SPI_StateTypeDef HAL_SPI_GetState(SPI_HandleTypeDef *hspi) +HAL_SPI_StateTypeDef HAL_SPI_GetState(const SPI_HandleTypeDef *hspi) { /* Return SPI handle state */ return hspi->State; @@ -3050,7 +3038,7 @@ HAL_SPI_StateTypeDef HAL_SPI_GetState(SPI_HandleTypeDef *hspi) * the configuration information for SPI module. * @retval SPI error code in bitmap format */ -uint32_t HAL_SPI_GetError(SPI_HandleTypeDef *hspi) +uint32_t HAL_SPI_GetError(const SPI_HandleTypeDef *hspi) { /* Return SPI ErrorCode */ return hspi->ErrorCode; @@ -3077,7 +3065,7 @@ uint32_t HAL_SPI_GetError(SPI_HandleTypeDef *hspi) */ static void SPI_DMATransmitCplt(DMA_HandleTypeDef *hdma) { - SPI_HandleTypeDef *hspi = (SPI_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent); /* Derogation MISRAC2012-Rule-11.5 */ + SPI_HandleTypeDef *hspi = (SPI_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent); uint32_t tickstart; /* Init tickstart for timeout management*/ @@ -3134,7 +3122,7 @@ static void SPI_DMATransmitCplt(DMA_HandleTypeDef *hdma) */ static void SPI_DMAReceiveCplt(DMA_HandleTypeDef *hdma) { - SPI_HandleTypeDef *hspi = (SPI_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent); /* Derogation MISRAC2012-Rule-11.5 */ + SPI_HandleTypeDef *hspi = (SPI_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent); uint32_t tickstart; #if (USE_SPI_CRC != 0U) __IO uint32_t tmpreg = 0U; @@ -3251,7 +3239,7 @@ static void SPI_DMAReceiveCplt(DMA_HandleTypeDef *hdma) */ static void SPI_DMATransmitReceiveCplt(DMA_HandleTypeDef *hdma) { - SPI_HandleTypeDef *hspi = (SPI_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent); /* Derogation MISRAC2012-Rule-11.5 */ + SPI_HandleTypeDef *hspi = (SPI_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent); uint32_t tickstart; #if (USE_SPI_CRC != 0U) __IO uint32_t tmpreg = 0U; @@ -3289,7 +3277,8 @@ static void SPI_DMATransmitReceiveCplt(DMA_HandleTypeDef *hdma) } else { - if (SPI_WaitFifoStateUntilTimeout(hspi, SPI_FLAG_FRLVL, SPI_FRLVL_HALF_FULL, SPI_DEFAULT_TIMEOUT, tickstart) != HAL_OK) + if (SPI_WaitFifoStateUntilTimeout(hspi, SPI_FLAG_FRLVL, SPI_FRLVL_HALF_FULL, SPI_DEFAULT_TIMEOUT, + tickstart) != HAL_OK) { /* Error on the CRC reception */ SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_CRC); @@ -3351,7 +3340,7 @@ static void SPI_DMATransmitReceiveCplt(DMA_HandleTypeDef *hdma) */ static void SPI_DMAHalfTransmitCplt(DMA_HandleTypeDef *hdma) { - SPI_HandleTypeDef *hspi = (SPI_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent); /* Derogation MISRAC2012-Rule-11.5 */ + SPI_HandleTypeDef *hspi = (SPI_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent); /* Call user Tx half complete callback */ #if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U) @@ -3369,7 +3358,7 @@ static void SPI_DMAHalfTransmitCplt(DMA_HandleTypeDef *hdma) */ static void SPI_DMAHalfReceiveCplt(DMA_HandleTypeDef *hdma) { - SPI_HandleTypeDef *hspi = (SPI_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent); /* Derogation MISRAC2012-Rule-11.5 */ + SPI_HandleTypeDef *hspi = (SPI_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent); /* Call user Rx half complete callback */ #if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U) @@ -3387,7 +3376,7 @@ static void SPI_DMAHalfReceiveCplt(DMA_HandleTypeDef *hdma) */ static void SPI_DMAHalfTransmitReceiveCplt(DMA_HandleTypeDef *hdma) { - SPI_HandleTypeDef *hspi = (SPI_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent); /* Derogation MISRAC2012-Rule-11.5 */ + SPI_HandleTypeDef *hspi = (SPI_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent); /* Call user TxRx half complete callback */ #if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U) @@ -3405,7 +3394,7 @@ static void SPI_DMAHalfTransmitReceiveCplt(DMA_HandleTypeDef *hdma) */ static void SPI_DMAError(DMA_HandleTypeDef *hdma) { - SPI_HandleTypeDef *hspi = (SPI_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent); /* Derogation MISRAC2012-Rule-11.5 */ + SPI_HandleTypeDef *hspi = (SPI_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent); /* Stop the disable DMA transfer on SPI side */ CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_TXDMAEN | SPI_CR2_RXDMAEN); @@ -3428,7 +3417,7 @@ static void SPI_DMAError(DMA_HandleTypeDef *hdma) */ static void SPI_DMAAbortOnError(DMA_HandleTypeDef *hdma) { - SPI_HandleTypeDef *hspi = (SPI_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent); /* Derogation MISRAC2012-Rule-11.5 */ + SPI_HandleTypeDef *hspi = (SPI_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent); hspi->RxXferCount = 0U; hspi->TxXferCount = 0U; @@ -3450,7 +3439,7 @@ static void SPI_DMAAbortOnError(DMA_HandleTypeDef *hdma) */ static void SPI_DMATxAbortCallback(DMA_HandleTypeDef *hdma) { - SPI_HandleTypeDef *hspi = (SPI_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent); /* Derogation MISRAC2012-Rule-11.5 */ + SPI_HandleTypeDef *hspi = (SPI_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent); hspi->hdmatx->XferAbortCallback = NULL; @@ -3466,7 +3455,8 @@ static void SPI_DMATxAbortCallback(DMA_HandleTypeDef *hdma) __HAL_SPI_DISABLE(hspi); /* Empty the FRLVL fifo */ - if (SPI_WaitFifoStateUntilTimeout(hspi, SPI_FLAG_FRLVL, SPI_FRLVL_EMPTY, SPI_DEFAULT_TIMEOUT, HAL_GetTick()) != HAL_OK) + if (SPI_WaitFifoStateUntilTimeout(hspi, SPI_FLAG_FRLVL, SPI_FRLVL_EMPTY, SPI_DEFAULT_TIMEOUT, + HAL_GetTick()) != HAL_OK) { hspi->ErrorCode = HAL_SPI_ERROR_ABORT; } @@ -3516,7 +3506,7 @@ static void SPI_DMATxAbortCallback(DMA_HandleTypeDef *hdma) */ static void SPI_DMARxAbortCallback(DMA_HandleTypeDef *hdma) { - SPI_HandleTypeDef *hspi = (SPI_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent); /* Derogation MISRAC2012-Rule-11.5 */ + SPI_HandleTypeDef *hspi = (SPI_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent); /* Disable SPI Peripheral */ __HAL_SPI_DISABLE(hspi); @@ -3533,7 +3523,8 @@ static void SPI_DMARxAbortCallback(DMA_HandleTypeDef *hdma) } /* Empty the FRLVL fifo */ - if (SPI_WaitFifoStateUntilTimeout(hspi, SPI_FLAG_FRLVL, SPI_FRLVL_EMPTY, SPI_DEFAULT_TIMEOUT, HAL_GetTick()) != HAL_OK) + if (SPI_WaitFifoStateUntilTimeout(hspi, SPI_FLAG_FRLVL, SPI_FRLVL_EMPTY, SPI_DEFAULT_TIMEOUT, + HAL_GetTick()) != HAL_OK) { hspi->ErrorCode = HAL_SPI_ERROR_ABORT; } @@ -3669,14 +3660,14 @@ static void SPI_2linesTxISR_8BIT(struct __SPI_HandleTypeDef *hspi) /* Transmit data in packing Bit mode */ if (hspi->TxXferCount >= 2U) { - hspi->Instance->DR = *((uint16_t *)hspi->pTxBuffPtr); + hspi->Instance->DR = *((const uint16_t *)hspi->pTxBuffPtr); hspi->pTxBuffPtr += sizeof(uint16_t); hspi->TxXferCount -= 2U; } /* Transmit data in 8 Bit mode */ else { - *(__IO uint8_t *)&hspi->Instance->DR = (*hspi->pTxBuffPtr); + *(__IO uint8_t *)&hspi->Instance->DR = *((const uint8_t *)hspi->pTxBuffPtr); hspi->pTxBuffPtr++; hspi->TxXferCount--; } @@ -3770,7 +3761,7 @@ static void SPI_2linesRxISR_16BITCRC(struct __SPI_HandleTypeDef *hspi) static void SPI_2linesTxISR_16BIT(struct __SPI_HandleTypeDef *hspi) { /* Transmit data in 16 Bit mode */ - hspi->Instance->DR = *((uint16_t *)hspi->pTxBuffPtr); + hspi->Instance->DR = *((const uint16_t *)hspi->pTxBuffPtr); hspi->pTxBuffPtr += sizeof(uint16_t); hspi->TxXferCount--; @@ -3923,7 +3914,7 @@ static void SPI_RxISR_16BIT(struct __SPI_HandleTypeDef *hspi) */ static void SPI_TxISR_8BIT(struct __SPI_HandleTypeDef *hspi) { - *(__IO uint8_t *)&hspi->Instance->DR = (*hspi->pTxBuffPtr); + *(__IO uint8_t *)&hspi->Instance->DR = *((const uint8_t *)hspi->pTxBuffPtr); hspi->pTxBuffPtr++; hspi->TxXferCount--; @@ -3949,7 +3940,7 @@ static void SPI_TxISR_8BIT(struct __SPI_HandleTypeDef *hspi) static void SPI_TxISR_16BIT(struct __SPI_HandleTypeDef *hspi) { /* Transmit data in 16 Bit mode */ - hspi->Instance->DR = *((uint16_t *)hspi->pTxBuffPtr); + hspi->Instance->DR = *((const uint16_t *)hspi->pTxBuffPtr); hspi->pTxBuffPtr += sizeof(uint16_t); hspi->TxXferCount--; @@ -4028,7 +4019,10 @@ static HAL_StatusTypeDef SPI_WaitFlagStateUntilTimeout(SPI_HandleTypeDef *hspi, { tmp_timeout = 0U; } - count--; + else + { + count--; + } } } @@ -4051,7 +4045,7 @@ static HAL_StatusTypeDef SPI_WaitFifoStateUntilTimeout(SPI_HandleTypeDef *hspi, __IO uint32_t count; uint32_t tmp_timeout; uint32_t tmp_tickstart; - __IO uint8_t *ptmpreg8; + __IO const uint8_t *ptmpreg8; __IO uint8_t tmpreg8 = 0; /* Adjust Timeout value in case of end of transfer */ @@ -4110,7 +4104,10 @@ static HAL_StatusTypeDef SPI_WaitFifoStateUntilTimeout(SPI_HandleTypeDef *hspi, { tmp_timeout = 0U; } - count--; + else + { + count--; + } } } @@ -4406,7 +4403,8 @@ static void SPI_AbortRx_ISR(SPI_HandleTypeDef *hspi) } /* Empty the FRLVL fifo */ - if (SPI_WaitFifoStateUntilTimeout(hspi, SPI_FLAG_FRLVL, SPI_FRLVL_EMPTY, SPI_DEFAULT_TIMEOUT, HAL_GetTick()) != HAL_OK) + if (SPI_WaitFifoStateUntilTimeout(hspi, SPI_FLAG_FRLVL, SPI_FRLVL_EMPTY, SPI_DEFAULT_TIMEOUT, + HAL_GetTick()) != HAL_OK) { hspi->ErrorCode = HAL_SPI_ERROR_ABORT; } @@ -4449,7 +4447,8 @@ static void SPI_AbortTx_ISR(SPI_HandleTypeDef *hspi) __HAL_SPI_DISABLE(hspi); /* Empty the FRLVL fifo */ - if (SPI_WaitFifoStateUntilTimeout(hspi, SPI_FLAG_FRLVL, SPI_FRLVL_EMPTY, SPI_DEFAULT_TIMEOUT, HAL_GetTick()) != HAL_OK) + if (SPI_WaitFifoStateUntilTimeout(hspi, SPI_FLAG_FRLVL, SPI_FRLVL_EMPTY, SPI_DEFAULT_TIMEOUT, + HAL_GetTick()) != HAL_OK) { hspi->ErrorCode = HAL_SPI_ERROR_ABORT; } @@ -4478,7 +4477,8 @@ static void SPI_AbortTx_ISR(SPI_HandleTypeDef *hspi) } /* Empty the FRLVL fifo */ - if (SPI_WaitFifoStateUntilTimeout(hspi, SPI_FLAG_FRLVL, SPI_FRLVL_EMPTY, SPI_DEFAULT_TIMEOUT, HAL_GetTick()) != HAL_OK) + if (SPI_WaitFifoStateUntilTimeout(hspi, SPI_FLAG_FRLVL, SPI_FRLVL_EMPTY, SPI_DEFAULT_TIMEOUT, + HAL_GetTick()) != HAL_OK) { hspi->ErrorCode = HAL_SPI_ERROR_ABORT; } diff --git a/system/Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_sram.c b/system/Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_sram.c index 0853ed354a..e16158be01 100644 --- a/system/Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_sram.c +++ b/system/Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_sram.c @@ -1038,6 +1038,7 @@ HAL_SRAM_StateTypeDef HAL_SRAM_GetState(const SRAM_HandleTypeDef *hsram) */ static void SRAM_DMACplt(DMA_HandleTypeDef *hdma) { + /* Derogation MISRAC2012-Rule-11.5 */ SRAM_HandleTypeDef *hsram = (SRAM_HandleTypeDef *)(hdma->Parent); /* Disable the DMA channel */ @@ -1060,6 +1061,7 @@ static void SRAM_DMACplt(DMA_HandleTypeDef *hdma) */ static void SRAM_DMACpltProt(DMA_HandleTypeDef *hdma) { + /* Derogation MISRAC2012-Rule-11.5 */ SRAM_HandleTypeDef *hsram = (SRAM_HandleTypeDef *)(hdma->Parent); /* Disable the DMA channel */ @@ -1082,6 +1084,7 @@ static void SRAM_DMACpltProt(DMA_HandleTypeDef *hdma) */ static void SRAM_DMAError(DMA_HandleTypeDef *hdma) { + /* Derogation MISRAC2012-Rule-11.5 */ SRAM_HandleTypeDef *hsram = (SRAM_HandleTypeDef *)(hdma->Parent); /* Disable the DMA channel */ diff --git a/system/Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c b/system/Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c index 41218d5eaa..9c2ad16306 100644 --- a/system/Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c +++ b/system/Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c @@ -4595,7 +4595,6 @@ HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStart(TIM_HandleTypeDef *htim, uint32_t ((BurstLength) >> 8U) + 1U); - return status; } @@ -5252,8 +5251,8 @@ HAL_StatusTypeDef HAL_TIM_DMABurst_ReadStop(TIM_HandleTypeDef *htim, uint32_t Bu * @arg TIM_EVENTSOURCE_BREAK2: Timer Break2 event source * @note Basic timers can only generate an update event. * @note TIM_EVENTSOURCE_COM is relevant only with advanced timer instances. - * @note TIM_EVENTSOURCE_BREAK are relevant only for timer instances - * supporting a break input. + * @note TIM_EVENTSOURCE_BREAK and TIM_EVENTSOURCE_BREAK2 are relevant + * only for timer instances supporting break input(s). * @retval HAL status */ @@ -6991,8 +6990,6 @@ void TIM_Base_SetConfig(TIM_TypeDef *TIMx, const TIM_Base_InitTypeDef *Structure /* Set the auto-reload preload */ MODIFY_REG(tmpcr1, TIM_CR1_ARPE, Structure->AutoReloadPreload); - TIMx->CR1 = tmpcr1; - /* Set the Autoreload value */ TIMx->ARR = (uint32_t)Structure->Period ; @@ -7005,16 +7002,18 @@ void TIM_Base_SetConfig(TIM_TypeDef *TIMx, const TIM_Base_InitTypeDef *Structure TIMx->RCR = Structure->RepetitionCounter; } + /* Disable Update Event (UEV) with Update Generation (UG) + by changing Update Request Source (URS) to avoid Update flag (UIF) */ + SET_BIT(TIMx->CR1, TIM_CR1_URS); + /* Generate an update event to reload the Prescaler and the repetition counter (only for advanced timer) value immediately */ TIMx->EGR = TIM_EGR_UG; - /* Check if the update flag is set after the Update Generation, if so clear the UIF flag */ - if (HAL_IS_BIT_SET(TIMx->SR, TIM_FLAG_UPDATE)) - { - /* Clear the update flag */ - CLEAR_BIT(TIMx->SR, TIM_FLAG_UPDATE); - } + /* Ensure that the update event is generated before writing back CR1 register with URS = 0 */ + __DSB(); + + TIMx->CR1 = tmpcr1; } /** @@ -7057,12 +7056,13 @@ static void TIM_OC1_SetConfig(TIM_TypeDef *TIMx, const TIM_OC_InitTypeDef *OC_Co /* Check parameters */ assert_param(IS_TIM_OCN_POLARITY(OC_Config->OCNPolarity)); + /* Disable the Channel 1N: Reset the CC1NE Bit */ + TIMx->CCER &= ~TIM_CCER_CC1NE; + /* Reset the Output N Polarity level */ tmpccer &= ~TIM_CCER_CC1NP; /* Set the Output N Polarity */ tmpccer |= OC_Config->OCNPolarity; - /* Reset the Output N State */ - tmpccer &= ~TIM_CCER_CC1NE; } if (IS_TIM_BREAK_INSTANCE(TIMx)) @@ -7133,12 +7133,13 @@ void TIM_OC2_SetConfig(TIM_TypeDef *TIMx, const TIM_OC_InitTypeDef *OC_Config) { assert_param(IS_TIM_OCN_POLARITY(OC_Config->OCNPolarity)); + /* Disable the Channel 2N: Reset the CC2NE Bit */ + TIMx->CCER &= ~TIM_CCER_CC2NE; + /* Reset the Output N Polarity level */ tmpccer &= ~TIM_CCER_CC2NP; /* Set the Output N Polarity */ tmpccer |= (OC_Config->OCNPolarity << 4U); - /* Reset the Output N State */ - tmpccer &= ~TIM_CCER_CC2NE; } if (IS_TIM_BREAK_INSTANCE(TIMx)) @@ -7210,12 +7211,13 @@ static void TIM_OC3_SetConfig(TIM_TypeDef *TIMx, const TIM_OC_InitTypeDef *OC_Co { assert_param(IS_TIM_OCN_POLARITY(OC_Config->OCNPolarity)); + /* Disable the Channel 3N: Reset the CC3NE Bit */ + TIMx->CCER &= ~TIM_CCER_CC3NE; + /* Reset the Output N Polarity level */ tmpccer &= ~TIM_CCER_CC3NP; /* Set the Output N Polarity */ tmpccer |= (OC_Config->OCNPolarity << 8U); - /* Reset the Output N State */ - tmpccer &= ~TIM_CCER_CC3NE; } #if defined(TIM_CR2_OIS3) @@ -7570,9 +7572,18 @@ void TIM_TI1_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ uint32_t tmpccmr1; uint32_t tmpccer; - /* Disable the Channel 1: Reset the CC1E Bit */ + /* Get the TIMx CCER register value */ tmpccer = TIMx->CCER; + + /* Disable the Channel 1: Reset the CC1E Bit */ TIMx->CCER &= ~TIM_CCER_CC1E; + /* Disable the Channel 1N: Reset the CC1NE Bit */ + if (IS_TIM_CCXN_INSTANCE(TIMx, TIM_CHANNEL_1)) + { + TIMx->CCER &= ~TIM_CCER_CC1NE; + } + + /* Get the TIMx CCMR1 register value */ tmpccmr1 = TIMx->CCMR1; /* Select the Input */ @@ -7616,9 +7627,18 @@ static void TIM_TI1_ConfigInputStage(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t tmpccmr1; uint32_t tmpccer; - /* Disable the Channel 1: Reset the CC1E Bit */ + /* Get the TIMx CCER register value */ tmpccer = TIMx->CCER; + + /* Disable the Channel 1: Reset the CC1E Bit */ TIMx->CCER &= ~TIM_CCER_CC1E; + /* Disable the Channel 1N: Reset the CC1NE Bit */ + if (IS_TIM_CCXN_INSTANCE(TIMx, TIM_CHANNEL_1)) + { + TIMx->CCER &= ~TIM_CCER_CC1NE; + } + + /* Get the TIMx CCMR1 register value */ tmpccmr1 = TIMx->CCMR1; /* Set the filter */ @@ -7660,9 +7680,18 @@ static void TIM_TI2_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32 uint32_t tmpccmr1; uint32_t tmpccer; - /* Disable the Channel 2: Reset the CC2E Bit */ + /* Get the TIMx CCER register value */ tmpccer = TIMx->CCER; + + /* Disable the Channel 2: Reset the CC2E Bit */ TIMx->CCER &= ~TIM_CCER_CC2E; + /* Disable the Channel 2N: Reset the CC2NE Bit */ + if (IS_TIM_CCXN_INSTANCE(TIMx, TIM_CHANNEL_2)) + { + TIMx->CCER &= ~TIM_CCER_CC2NE; + } + + /* Get the TIMx CCMR1 register value */ tmpccmr1 = TIMx->CCMR1; /* Select the Input */ @@ -7699,9 +7728,18 @@ static void TIM_TI2_ConfigInputStage(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t tmpccmr1; uint32_t tmpccer; - /* Disable the Channel 2: Reset the CC2E Bit */ + /* Get the TIMx CCER register value */ tmpccer = TIMx->CCER; + + /* Disable the Channel 2: Reset the CC2E Bit */ TIMx->CCER &= ~TIM_CCER_CC2E; + /* Disable the Channel 2N: Reset the CC2NE Bit */ + if (IS_TIM_CCXN_INSTANCE(TIMx, TIM_CHANNEL_2)) + { + TIMx->CCER &= ~TIM_CCER_CC2NE; + } + + /* Get the TIMx CCMR1 register value */ tmpccmr1 = TIMx->CCMR1; /* Set the filter */ @@ -7743,9 +7781,18 @@ static void TIM_TI3_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32 uint32_t tmpccmr2; uint32_t tmpccer; - /* Disable the Channel 3: Reset the CC3E Bit */ + /* Get the TIMx CCER register value */ tmpccer = TIMx->CCER; + + /* Disable the Channel 3: Reset the CC3E Bit */ TIMx->CCER &= ~TIM_CCER_CC3E; + /* Disable the Channel 3N: Reset the CC3NE Bit */ + if (IS_TIM_CCXN_INSTANCE(TIMx, TIM_CHANNEL_3)) + { + TIMx->CCER &= ~TIM_CCER_CC3NE; + } + + /* Get the TIMx CCMR2 register value */ tmpccmr2 = TIMx->CCMR2; /* Select the Input */ @@ -7791,9 +7838,13 @@ static void TIM_TI4_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32 uint32_t tmpccmr2; uint32_t tmpccer; - /* Disable the Channel 4: Reset the CC4E Bit */ + /* Get the TIMx CCER register value */ tmpccer = TIMx->CCER; + + /* Disable the Channel 4: Reset the CC4E Bit */ TIMx->CCER &= ~TIM_CCER_CC4E; + + /* Get the TIMx CCMR2 register value */ tmpccmr2 = TIMx->CCMR2; /* Select the Input */ @@ -7880,12 +7931,13 @@ void TIM_ETR_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ExtTRGPrescaler, * @param TIMx to select the TIM peripheral * @param Channel specifies the TIM Channel * This parameter can be one of the following values: - * @arg TIM_CHANNEL_1: TIM Channel 1 - * @arg TIM_CHANNEL_2: TIM Channel 2 - * @arg TIM_CHANNEL_3: TIM Channel 3 - * @arg TIM_CHANNEL_4: TIM Channel 4 - * @arg TIM_CHANNEL_5: TIM Channel 5 selected - * @arg TIM_CHANNEL_6: TIM Channel 6 selected + * @arg TIM_CHANNEL_1: TIM Channel 1 selected + * @arg TIM_CHANNEL_2: TIM Channel 2 selected + * @arg TIM_CHANNEL_3: TIM Channel 3 selected + * @arg TIM_CHANNEL_4: TIM Channel 4 selected + * @arg TIM_CHANNEL_5: TIM Channel 5 selected (*) + * @arg TIM_CHANNEL_6: TIM Channel 6 selected (*) + * (*) Value not defined for all devices * @param ChannelState specifies the TIM Channel CCxE bit new state. * This parameter can be: TIM_CCx_ENABLE or TIM_CCx_DISABLE. * @retval None diff --git a/system/Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c b/system/Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c index 2784849951..8b647d7a51 100644 --- a/system/Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c +++ b/system/Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c @@ -2342,9 +2342,9 @@ HAL_TIM_StateTypeDef HAL_TIMEx_HallSensor_GetState(const TIM_HandleTypeDef *htim * @param htim TIM handle * @param ChannelN TIM Complementary channel * This parameter can be one of the following values: - * @arg TIM_CHANNEL_1: TIM Channel 1 - * @arg TIM_CHANNEL_2: TIM Channel 2 - * @arg TIM_CHANNEL_3: TIM Channel 3 + * @arg TIM_CHANNEL_1: TIM Channel 1 selected + * @arg TIM_CHANNEL_2: TIM Channel 2 selected + * @arg TIM_CHANNEL_3: TIM Channel 3 selected * @retval TIM Complementary channel state */ HAL_TIM_ChannelStateTypeDef HAL_TIMEx_GetChannelNState(const TIM_HandleTypeDef *htim, uint32_t ChannelN) @@ -2503,9 +2503,9 @@ static void TIM_DMAErrorCCxN(DMA_HandleTypeDef *hdma) * @param TIMx to select the TIM peripheral * @param Channel specifies the TIM Channel * This parameter can be one of the following values: - * @arg TIM_CHANNEL_1: TIM Channel 1 - * @arg TIM_CHANNEL_2: TIM Channel 2 - * @arg TIM_CHANNEL_3: TIM Channel 3 + * @arg TIM_CHANNEL_1: TIM Channel 1 selected + * @arg TIM_CHANNEL_2: TIM Channel 2 selected + * @arg TIM_CHANNEL_3: TIM Channel 3 selected * @param ChannelNState specifies the TIM Channel CCxNE bit new state. * This parameter can be: TIM_CCxN_ENABLE or TIM_CCxN_Disable. * @retval None diff --git a/system/Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_timebase_tim_template.c b/system/Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_timebase_tim_template.c index 15d820f70c..9bb4fca86c 100644 --- a/system/Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_timebase_tim_template.c +++ b/system/Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_timebase_tim_template.c @@ -39,6 +39,9 @@ TIM_HandleTypeDef TimHandle; /* Private function prototypes -----------------------------------------------*/ void TIM6_DAC_IRQHandler(void); +#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1U) +void TimeBase_TIM_PeriodElapsedCallback(TIM_HandleTypeDef *htim); +#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ /* Private functions ---------------------------------------------------------*/ /** @@ -97,6 +100,11 @@ HAL_StatusTypeDef HAL_InitTick (uint32_t TickPriority) status = HAL_TIM_Base_Init(&TimHandle); if (status == HAL_OK) { +#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1U) + /* Register callback */ + HAL_TIM_RegisterCallback(&TimHandle, HAL_TIM_PERIOD_ELAPSED_CB_ID, TimeBase_TIM_PeriodElapsedCallback); +#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ + /* Start the TIM time Base generation in interrupt mode */ status = HAL_TIM_Base_Start_IT(&TimHandle); if (status == HAL_OK) @@ -152,8 +160,15 @@ void HAL_ResumeTick(void) * @param htim TIM handle * @retval None */ +#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1U) +void TimeBase_TIM_PeriodElapsedCallback(TIM_HandleTypeDef *htim) +#else void HAL_TIM_PeriodElapsedCallback(TIM_HandleTypeDef *htim) +#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ { + /* Prevent unused argument(s) compilation warning */ + UNUSED(htim); + HAL_IncTick(); } diff --git a/system/Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_uart.c b/system/Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_uart.c index a6b101f9fd..73e734429d 100644 --- a/system/Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_uart.c +++ b/system/Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_uart.c @@ -624,8 +624,6 @@ HAL_StatusTypeDef HAL_UART_DeInit(UART_HandleTypeDef *huart) huart->gState = HAL_UART_STATE_BUSY; - __HAL_UART_DISABLE(huart); - huart->Instance->CR1 = 0x0U; huart->Instance->CR2 = 0x0U; huart->Instance->CR3 = 0x0U; @@ -985,75 +983,79 @@ HAL_StatusTypeDef HAL_UART_UnRegisterRxEventCallback(UART_HandleTypeDef *huart) =============================================================================== ##### IO operation functions ##### =============================================================================== + [..] This subsection provides a set of functions allowing to manage the UART asynchronous and Half duplex data transfers. - (#) There are two mode of transfer: - (+) Blocking mode: The communication is performed in polling mode. - The HAL status of all data processing is returned by the same function - after finishing transfer. - (+) Non-Blocking mode: The communication is performed using Interrupts - or DMA, These API's return the HAL status. - The end of the data processing will be indicated through the - dedicated UART IRQ when using Interrupt mode or the DMA IRQ when - using DMA mode. - The HAL_UART_TxCpltCallback(), HAL_UART_RxCpltCallback() user callbacks - will be executed respectively at the end of the transmit or Receive process - The HAL_UART_ErrorCallback()user callback will be executed when a communication error is detected + (#) There are two modes of transfer: + (++) Blocking mode: The communication is performed in polling mode. + The HAL status of all data processing is returned by the same function + after finishing transfer. + (++) Non-Blocking mode: The communication is performed using Interrupts + or DMA, These API's return the HAL status. + The end of the data processing will be indicated through the + dedicated UART IRQ when using Interrupt mode or the DMA IRQ when + using DMA mode. + The HAL_UART_TxCpltCallback(), HAL_UART_RxCpltCallback() user callbacks + will be executed respectively at the end of the transmit or Receive process + The HAL_UART_ErrorCallback()user callback will be executed when a communication error is detected (#) Blocking mode API's are : - (+) HAL_UART_Transmit() - (+) HAL_UART_Receive() + (++) HAL_UART_Transmit() + (++) HAL_UART_Receive() (#) Non-Blocking mode API's with Interrupt are : - (+) HAL_UART_Transmit_IT() - (+) HAL_UART_Receive_IT() - (+) HAL_UART_IRQHandler() + (++) HAL_UART_Transmit_IT() + (++) HAL_UART_Receive_IT() + (++) HAL_UART_IRQHandler() (#) Non-Blocking mode API's with DMA are : - (+) HAL_UART_Transmit_DMA() - (+) HAL_UART_Receive_DMA() - (+) HAL_UART_DMAPause() - (+) HAL_UART_DMAResume() - (+) HAL_UART_DMAStop() + (++) HAL_UART_Transmit_DMA() + (++) HAL_UART_Receive_DMA() + (++) HAL_UART_DMAPause() + (++) HAL_UART_DMAResume() + (++) HAL_UART_DMAStop() (#) A set of Transfer Complete Callbacks are provided in Non_Blocking mode: - (+) HAL_UART_TxHalfCpltCallback() - (+) HAL_UART_TxCpltCallback() - (+) HAL_UART_RxHalfCpltCallback() - (+) HAL_UART_RxCpltCallback() - (+) HAL_UART_ErrorCallback() + (++) HAL_UART_TxHalfCpltCallback() + (++) HAL_UART_TxCpltCallback() + (++) HAL_UART_RxHalfCpltCallback() + (++) HAL_UART_RxCpltCallback() + (++) HAL_UART_ErrorCallback() (#) Non-Blocking mode transfers could be aborted using Abort API's : - (+) HAL_UART_Abort() - (+) HAL_UART_AbortTransmit() - (+) HAL_UART_AbortReceive() - (+) HAL_UART_Abort_IT() - (+) HAL_UART_AbortTransmit_IT() - (+) HAL_UART_AbortReceive_IT() + (++) HAL_UART_Abort() + (++) HAL_UART_AbortTransmit() + (++) HAL_UART_AbortReceive() + (++) HAL_UART_Abort_IT() + (++) HAL_UART_AbortTransmit_IT() + (++) HAL_UART_AbortReceive_IT() (#) For Abort services based on interrupts (HAL_UART_Abortxxx_IT), a set of Abort Complete Callbacks are provided: - (+) HAL_UART_AbortCpltCallback() - (+) HAL_UART_AbortTransmitCpltCallback() - (+) HAL_UART_AbortReceiveCpltCallback() + (++) HAL_UART_AbortCpltCallback() + (++) HAL_UART_AbortTransmitCpltCallback() + (++) HAL_UART_AbortReceiveCpltCallback() (#) A Rx Event Reception Callback (Rx event notification) is available for Non_Blocking modes of enhanced reception services: - (+) HAL_UARTEx_RxEventCallback() + (++) HAL_UARTEx_RxEventCallback() + + (#) Wakeup from Stop mode Callback: + (++) HAL_UARTEx_WakeupCallback() (#) In Non-Blocking mode transfers, possible errors are split into 2 categories. Errors are handled as follows : - (+) Error is considered as Recoverable and non blocking : Transfer could go till end, but error severity is - to be evaluated by user : this concerns Frame Error, Parity Error or Noise Error - in Interrupt mode reception . - Received character is then retrieved and stored in Rx buffer, Error code is set to allow user - to identify error type, and HAL_UART_ErrorCallback() user callback is executed. - Transfer is kept ongoing on UART side. - If user wants to abort it, Abort services should be called by user. - (+) Error is considered as Blocking : Transfer could not be completed properly and is aborted. - This concerns Overrun Error In Interrupt mode reception and all errors in DMA mode. - Error code is set to allow user to identify error type, and HAL_UART_ErrorCallback() - user callback is executed. + (++) Error is considered as Recoverable and non blocking : Transfer could go till end, but error severity is + to be evaluated by user : this concerns Frame Error, Parity Error or Noise Error + in Interrupt mode reception . + Received character is then retrieved and stored in Rx buffer, Error code is set to allow user + to identify error type, and HAL_UART_ErrorCallback() user callback is executed. + Transfer is kept ongoing on UART side. + If user wants to abort it, Abort services should be called by user. + (++) Error is considered as Blocking : Transfer could not be completed properly and is aborted. + This concerns Overrun Error In Interrupt mode reception and all errors in DMA mode. + Error code is set to allow user to identify error type, and HAL_UART_ErrorCallback() + user callback is executed. -@- In the Half duplex communication, it is forbidden to run the transmit and receive process in parallel, the UART state HAL_UART_STATE_BUSY_TX_RX can't be useful. @@ -1127,7 +1129,15 @@ HAL_StatusTypeDef HAL_UART_Transmit(UART_HandleTypeDef *huart, const uint8_t *pD huart->Instance->TDR = (uint8_t)(*pdata8bits & 0xFFU); pdata8bits++; } - huart->TxXferCount--; + if ((huart->gState & HAL_UART_STATE_BUSY_TX) == HAL_UART_STATE_BUSY_TX) + { + huart->TxXferCount--; + } + else + { + /* Process was aborted during the transmission */ + return HAL_ERROR; + } } if (UART_WaitOnFlagUntilTimeout(huart, UART_FLAG_TC, RESET, tickstart, Timeout) != HAL_OK) @@ -1219,7 +1229,15 @@ HAL_StatusTypeDef HAL_UART_Receive(UART_HandleTypeDef *huart, uint8_t *pData, ui *pdata8bits = (uint8_t)(huart->Instance->RDR & (uint8_t)uhMask); pdata8bits++; } - huart->RxXferCount--; + if (huart->RxState == HAL_UART_STATE_BUSY_RX) + { + huart->RxXferCount--; + } + else + { + /* Process was aborted during the reception */ + return HAL_ERROR; + } } /* At end of Rx process, restore huart->RxState to Ready */ @@ -1633,10 +1651,6 @@ HAL_StatusTypeDef HAL_UART_Abort(UART_HandleTypeDef *huart) } } - /* Reset Tx and Rx transfer counters */ - huart->TxXferCount = 0U; - huart->RxXferCount = 0U; - /* Clear the Error flags in the ICR register */ __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_OREF | UART_CLEAR_NEF | UART_CLEAR_PEF | UART_CLEAR_FEF); @@ -1697,9 +1711,6 @@ HAL_StatusTypeDef HAL_UART_AbortTransmit(UART_HandleTypeDef *huart) } } - /* Reset Tx transfer counter */ - huart->TxXferCount = 0U; - /* Restore huart->gState to Ready */ huart->gState = HAL_UART_STATE_READY; @@ -1757,9 +1768,6 @@ HAL_StatusTypeDef HAL_UART_AbortReceive(UART_HandleTypeDef *huart) } } - /* Reset Rx transfer counter */ - huart->RxXferCount = 0U; - /* Clear the Error flags in the ICR register */ __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_OREF | UART_CLEAR_NEF | UART_CLEAR_PEF | UART_CLEAR_FEF); @@ -1884,10 +1892,6 @@ HAL_StatusTypeDef HAL_UART_Abort_IT(UART_HandleTypeDef *huart) /* if no DMA abort complete callback execution is required => call user Abort Complete callback */ if (abortcplt == 1U) { - /* Reset Tx and Rx transfer counters */ - huart->TxXferCount = 0U; - huart->RxXferCount = 0U; - /* Clear ISR function pointers */ huart->RxISR = NULL; huart->TxISR = NULL; @@ -1961,8 +1965,6 @@ HAL_StatusTypeDef HAL_UART_AbortTransmit_IT(UART_HandleTypeDef *huart) } else { - /* Reset Tx transfer counter */ - huart->TxXferCount = 0U; /* Clear TxISR function pointers */ huart->TxISR = NULL; @@ -1982,9 +1984,6 @@ HAL_StatusTypeDef HAL_UART_AbortTransmit_IT(UART_HandleTypeDef *huart) } else { - /* Reset Tx transfer counter */ - huart->TxXferCount = 0U; - /* Clear TxISR function pointers */ huart->TxISR = NULL; @@ -2053,9 +2052,6 @@ HAL_StatusTypeDef HAL_UART_AbortReceive_IT(UART_HandleTypeDef *huart) } else { - /* Reset Rx transfer counter */ - huart->RxXferCount = 0U; - /* Clear RxISR function pointer */ huart->pRxBuffPtr = NULL; @@ -2081,9 +2077,6 @@ HAL_StatusTypeDef HAL_UART_AbortReceive_IT(UART_HandleTypeDef *huart) } else { - /* Reset Rx transfer counter */ - huart->RxXferCount = 0U; - /* Clear RxISR function pointer */ huart->pRxBuffPtr = NULL; @@ -2329,6 +2322,28 @@ void HAL_UART_IRQHandler(UART_HandleTypeDef *huart) HAL_UARTEx_RxEventCallback(huart, (huart->RxXferSize - huart->RxXferCount)); #endif /* (USE_HAL_UART_REGISTER_CALLBACKS) */ } + else + { + /* If DMA is in Circular mode, Idle event is to be reported to user + even if occurring after a Transfer Complete event from DMA */ + if (nb_remaining_rx_data == huart->RxXferSize) + { + if (huart->hdmarx->Init.Mode == DMA_CIRCULAR) + { + /* Initialize type of RxEvent that correspond to RxEvent callback execution; + In this case, Rx Event type is Idle Event */ + huart->RxEventType = HAL_UART_RXEVENT_IDLE; + +#if (USE_HAL_UART_REGISTER_CALLBACKS == 1) + /*Call registered Rx Event callback*/ + huart->RxEventCallback(huart, huart->RxXferSize); +#else + /*Call legacy weak Rx Event callback*/ + HAL_UARTEx_RxEventCallback(huart, huart->RxXferSize); +#endif /* (USE_HAL_UART_REGISTER_CALLBACKS) */ + } + } + } return; } else @@ -3449,12 +3464,24 @@ static void UART_DMAReceiveCplt(DMA_HandleTypeDef *hdma) If Reception till IDLE event has been selected : use Rx Event callback */ if (huart->ReceptionType == HAL_UART_RECEPTION_TOIDLE) { + huart->RxXferCount = 0; + + /* Check current nb of data still to be received on DMA side. + DMA Normal mode, remaining nb of data will be 0 + DMA Circular mode, remaining nb of data is reset to RxXferSize */ + uint16_t nb_remaining_rx_data = (uint16_t) __HAL_DMA_GET_COUNTER(hdma); + if (nb_remaining_rx_data < huart->RxXferSize) + { + /* Update nb of remaining data */ + huart->RxXferCount = nb_remaining_rx_data; + } + #if (USE_HAL_UART_REGISTER_CALLBACKS == 1) /*Call registered Rx Event callback*/ - huart->RxEventCallback(huart, huart->RxXferSize); + huart->RxEventCallback(huart, (huart->RxXferSize - huart->RxXferCount)); #else /*Call legacy weak Rx Event callback*/ - HAL_UARTEx_RxEventCallback(huart, huart->RxXferSize); + HAL_UARTEx_RxEventCallback(huart, (huart->RxXferSize - huart->RxXferCount)); #endif /* USE_HAL_UART_REGISTER_CALLBACKS */ } else @@ -3487,12 +3514,22 @@ static void UART_DMARxHalfCplt(DMA_HandleTypeDef *hdma) If Reception till IDLE event has been selected : use Rx Event callback */ if (huart->ReceptionType == HAL_UART_RECEPTION_TOIDLE) { + huart->RxXferCount = huart->RxXferSize / 2U; + + /* Check current nb of data still to be received on DMA side. */ + uint16_t nb_remaining_rx_data = (uint16_t) __HAL_DMA_GET_COUNTER(hdma); + if (nb_remaining_rx_data <= huart->RxXferSize) + { + /* Update nb of remaining data */ + huart->RxXferCount = nb_remaining_rx_data; + } + #if (USE_HAL_UART_REGISTER_CALLBACKS == 1) /*Call registered Rx Event callback*/ - huart->RxEventCallback(huart, huart->RxXferSize / 2U); + huart->RxEventCallback(huart, (huart->RxXferSize - huart->RxXferCount)); #else /*Call legacy weak Rx Event callback*/ - HAL_UARTEx_RxEventCallback(huart, huart->RxXferSize / 2U); + HAL_UARTEx_RxEventCallback(huart, (huart->RxXferSize - huart->RxXferCount)); #endif /* USE_HAL_UART_REGISTER_CALLBACKS */ } else @@ -3524,7 +3561,6 @@ static void UART_DMAError(DMA_HandleTypeDef *hdma) if ((HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAT)) && (gstate == HAL_UART_STATE_BUSY_TX)) { - huart->TxXferCount = 0U; UART_EndTxTransfer(huart); } @@ -3532,7 +3568,6 @@ static void UART_DMAError(DMA_HandleTypeDef *hdma) if ((HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR)) && (rxstate == HAL_UART_STATE_BUSY_RX)) { - huart->RxXferCount = 0U; UART_EndRxTransfer(huart); } @@ -3556,8 +3591,6 @@ static void UART_DMAError(DMA_HandleTypeDef *hdma) static void UART_DMAAbortOnError(DMA_HandleTypeDef *hdma) { UART_HandleTypeDef *huart = (UART_HandleTypeDef *)(hdma->Parent); - huart->RxXferCount = 0U; - huart->TxXferCount = 0U; #if (USE_HAL_UART_REGISTER_CALLBACKS == 1) /*Call registered error callback*/ @@ -3591,10 +3624,6 @@ static void UART_DMATxAbortCallback(DMA_HandleTypeDef *hdma) } } - /* No Abort process still ongoing : All DMA channels are aborted, call user Abort Complete callback */ - huart->TxXferCount = 0U; - huart->RxXferCount = 0U; - /* Reset errorCode */ huart->ErrorCode = HAL_UART_ERROR_NONE; @@ -3641,10 +3670,6 @@ static void UART_DMARxAbortCallback(DMA_HandleTypeDef *hdma) } } - /* No Abort process still ongoing : All DMA channels are aborted, call user Abort Complete callback */ - huart->TxXferCount = 0U; - huart->RxXferCount = 0U; - /* Reset errorCode */ huart->ErrorCode = HAL_UART_ERROR_NONE; @@ -3682,8 +3707,6 @@ static void UART_DMATxOnlyAbortCallback(DMA_HandleTypeDef *hdma) { UART_HandleTypeDef *huart = (UART_HandleTypeDef *)(hdma->Parent); - huart->TxXferCount = 0U; - /* Restore huart->gState to Ready */ huart->gState = HAL_UART_STATE_READY; @@ -3710,8 +3733,6 @@ static void UART_DMARxOnlyAbortCallback(DMA_HandleTypeDef *hdma) { UART_HandleTypeDef *huart = (UART_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; - huart->RxXferCount = 0U; - /* Clear the Error flags in the ICR register */ __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_OREF | UART_CLEAR_NEF | UART_CLEAR_PEF | UART_CLEAR_FEF); diff --git a/system/Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_uart_ex.c b/system/Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_uart_ex.c index c63133c4bd..ec7ca7722b 100644 --- a/system/Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_uart_ex.c +++ b/system/Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_uart_ex.c @@ -24,7 +24,7 @@ ============================================================================== ##### UART peripheral extended features ##### ============================================================================== - + [..] (#) Declare a UART_HandleTypeDef handle structure. (#) For the UART RS485 Driver Enable mode, initialize the UART registers @@ -235,11 +235,10 @@ HAL_StatusTypeDef HAL_RS485Ex_Init(UART_HandleTypeDef *huart, uint32_t Polarity, =============================================================================== ##### IO operation functions ##### =============================================================================== + [..] This subsection provides a set of Wakeup and FIFO mode related callback functions. - (#) Wakeup from Stop mode Callback: - (+) HAL_UARTEx_WakeupCallback() - + (++) HAL_UARTEx_WakeupCallback() @endverbatim * @{ */ @@ -286,19 +285,19 @@ __weak void HAL_UARTEx_WakeupCallback(UART_HandleTypeDef *huart) (#) Compared to standard reception services which only consider number of received data elements as reception completion criteria, these functions also consider additional events as triggers for updating reception status to caller : - (+) Detection of inactivity period (RX line has not been active for a given period). - (++) RX inactivity detected by IDLE event, i.e. RX line has been in idle state (normally high state) + (++) Detection of inactivity period (RX line has not been active for a given period). + (+++) RX inactivity detected by IDLE event, i.e. RX line has been in idle state (normally high state) for 1 frame time, after last received byte. - (++) RX inactivity detected by RTO, i.e. line has been in idle state + (+++) RX inactivity detected by RTO, i.e. line has been in idle state for a programmable time, after last received byte. - (+) Detection that a specific character has been received. + (++) Detection that a specific character has been received. - (#) There are two mode of transfer: - (+) Blocking mode: The reception is performed in polling mode, until either expected number of data is received, + (#) There are two modes of transfer: + (++) Blocking mode: The reception is performed in polling mode, until either expected number of data is received, or till IDLE event occurs. Reception is handled only during function execution. When function exits, no data reception could occur. HAL status and number of actually received data elements, are returned by function after finishing transfer. - (+) Non-Blocking mode: The reception is performed using Interrupts or DMA. + (++) Non-Blocking mode: The reception is performed using Interrupts or DMA. These API's return the HAL status. The end of the data processing will be indicated through the dedicated UART IRQ when using Interrupt mode or the DMA IRQ when using DMA mode. @@ -306,13 +305,13 @@ __weak void HAL_UARTEx_WakeupCallback(UART_HandleTypeDef *huart) The HAL_UART_ErrorCallback()user callback will be executed when a reception error is detected. (#) Blocking mode API: - (+) HAL_UARTEx_ReceiveToIdle() + (++) HAL_UARTEx_ReceiveToIdle() (#) Non-Blocking mode API with Interrupt: - (+) HAL_UARTEx_ReceiveToIdle_IT() + (++) HAL_UARTEx_ReceiveToIdle_IT() (#) Non-Blocking mode API with DMA: - (+) HAL_UARTEx_ReceiveToIdle_DMA() + (++) HAL_UARTEx_ReceiveToIdle_DMA() @endverbatim * @{ @@ -706,17 +705,15 @@ HAL_StatusTypeDef HAL_UARTEx_ReceiveToIdle_DMA(UART_HandleTypeDef *huart, uint8_ * Half Transfer, or Transfer Complete), this function allows to retrieve the Rx Event type that has lead * to Rx Event callback execution. * @note This function is expected to be called within the user implementation of Rx Event Callback, - * in order to provide the accurate value : - * In Interrupt Mode : - * - HAL_UART_RXEVENT_TC : when Reception has been completed (expected nb of data has been received) - * - HAL_UART_RXEVENT_IDLE : when Idle event occurred prior reception has been completed (nb of - * received data is lower than expected one) - * In DMA Mode : - * - HAL_UART_RXEVENT_TC : when Reception has been completed (expected nb of data has been received) - * - HAL_UART_RXEVENT_HT : when half of expected nb of data has been received - * - HAL_UART_RXEVENT_IDLE : when Idle event occurred prior reception has been completed (nb of - * received data is lower than expected one). - * In DMA mode, RxEvent callback could be called several times; + * in order to provide the accurate value. + * @note In Interrupt Mode: + * - HAL_UART_RXEVENT_TC : when Reception has been completed (expected nb of data has been received). + * - HAL_UART_RXEVENT_IDLE : when Idle event occurred prior reception has been completed. + * @note In DMA Mode: + * - HAL_UART_RXEVENT_TC : when Reception has been completed (expected nb of data has been received). + * - HAL_UART_RXEVENT_HT : when half of expected nb of data has been received. + * - HAL_UART_RXEVENT_IDLE : when Idle event occurred prior reception has been completed. + * @note In DMA mode, RxEvent callback could be called several times; * When DMA is configured in Normal Mode, HT event does not stop Reception process; * When DMA is configured in Circular Mode, HT, TC or IDLE events don't stop Reception process; * @param huart UART handle. diff --git a/system/Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_wwdg.c b/system/Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_wwdg.c index 6751a56d3c..88de43c647 100644 --- a/system/Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_wwdg.c +++ b/system/Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_wwdg.c @@ -95,7 +95,7 @@ and a pointer to the user callback function. (+) Use function HAL_WWDG_UnRegisterCallback() to reset a callback to - the default weak (surcharged) function. HAL_WWDG_UnRegisterCallback() + the default weak function. HAL_WWDG_UnRegisterCallback() takes as parameters the HAL peripheral handle and the Callback ID. This function allows to reset following callbacks: (++) EwiCallback : callback for Early WakeUp Interrupt. @@ -103,14 +103,14 @@ [..] When calling HAL_WWDG_Init function, callbacks are reset to the - corresponding legacy weak (surcharged) functions: + corresponding legacy weak functions: HAL_WWDG_EarlyWakeupCallback() and HAL_WWDG_MspInit() only if they have not been registered before. [..] When compilation define USE_HAL_WWDG_REGISTER_CALLBACKS is set to 0 or not defined, the callback registering feature is not available - and weak (surcharged) callbacks are used. + and weak (overridden) callbacks are used. *** WWDG HAL driver macros list *** =================================== @@ -240,7 +240,7 @@ __weak void HAL_WWDG_MspInit(WWDG_HandleTypeDef *hwwdg) #if (USE_HAL_WWDG_REGISTER_CALLBACKS == 1) /** * @brief Register a User WWDG Callback - * To be used instead of the weak (surcharged) predefined callback + * To be used instead of the weak (overridden) predefined callback * @param hwwdg WWDG handle * @param CallbackID ID of the callback to be registered * This parameter can be one of the following values: @@ -282,7 +282,7 @@ HAL_StatusTypeDef HAL_WWDG_RegisterCallback(WWDG_HandleTypeDef *hwwdg, HAL_WWDG_ /** * @brief Unregister a WWDG Callback - * WWDG Callback is redirected to the weak (surcharged) predefined callback + * WWDG Callback is redirected to the weak (overridden) predefined callback * @param hwwdg WWDG handle * @param CallbackID ID of the callback to be registered * This parameter can be one of the following values: diff --git a/system/Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_ll_exti.c b/system/Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_ll_exti.c index 80b85e387e..63d3fcf8a2 100644 --- a/system/Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_ll_exti.c +++ b/system/Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_ll_exti.c @@ -43,7 +43,12 @@ * @{ */ +#if defined(STM32F373xC) || defined(STM32F378xx) #define IS_LL_EXTI_LINE_0_31(__VALUE__) (((__VALUE__) & ~LL_EXTI_LINE_ALL_0_31) == 0x00000000U) +#else +#define IS_LL_EXTI_LINE_0_31(__VALUE__) ((__VALUE__) > 0x00000000U) +#endif /* STM32F373xC || STM32F378xx */ + #if defined(EXTI_32_63_SUPPORT) #define IS_LL_EXTI_LINE_32_63(__VALUE__) (((__VALUE__) & ~LL_EXTI_LINE_ALL_32_63) == 0x00000000U) #endif diff --git a/system/Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_ll_fmc.c b/system/Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_ll_fmc.c index 93a7ddbc18..be58cd7894 100644 --- a/system/Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_ll_fmc.c +++ b/system/Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_ll_fmc.c @@ -60,7 +60,7 @@ * @{ */ #if defined(HAL_NOR_MODULE_ENABLED) || defined(HAL_NAND_MODULE_ENABLED) || defined(HAL_PCCARD_MODULE_ENABLED) \ - || defined(HAL_SRAM_MODULE_ENABLED) + || defined(HAL_SRAM_MODULE_ENABLED) /** @defgroup FMC_LL FMC Low Layer * @brief FMC driver modules @@ -199,7 +199,7 @@ * @retval HAL status */ HAL_StatusTypeDef FMC_NORSRAM_Init(FMC_NORSRAM_TypeDef *Device, - FMC_NORSRAM_InitTypeDef *Init) + const FMC_NORSRAM_InitTypeDef *Init) { uint32_t flashaccess; uint32_t btcr_reg; @@ -324,7 +324,7 @@ HAL_StatusTypeDef FMC_NORSRAM_DeInit(FMC_NORSRAM_TypeDef *Device, * @retval HAL status */ HAL_StatusTypeDef FMC_NORSRAM_Timing_Init(FMC_NORSRAM_TypeDef *Device, - FMC_NORSRAM_TimingTypeDef *Timing, uint32_t Bank) + const FMC_NORSRAM_TimingTypeDef *Timing, uint32_t Bank) { uint32_t tmpr; @@ -352,7 +352,7 @@ HAL_StatusTypeDef FMC_NORSRAM_Timing_Init(FMC_NORSRAM_TypeDef *Device, /* Configure Clock division value (in NORSRAM bank 1) when continuous clock is enabled */ if (HAL_IS_BIT_SET(Device->BTCR[FMC_NORSRAM_BANK1], FMC_BCR1_CCLKEN)) { - tmpr = (uint32_t)(Device->BTCR[FMC_NORSRAM_BANK1 + 1U] & ~((0x0FU) << FMC_BTRx_CLKDIV_Pos)); + tmpr = (uint32_t)(Device->BTCR[FMC_NORSRAM_BANK1 + 1U] & ~((0x0FUL) << FMC_BTRx_CLKDIV_Pos)); tmpr |= (uint32_t)(((Timing->CLKDivision) - 1U) << FMC_BTRx_CLKDIV_Pos); MODIFY_REG(Device->BTCR[FMC_NORSRAM_BANK1 + 1U], FMC_BTRx_CLKDIV, tmpr); } @@ -373,7 +373,7 @@ HAL_StatusTypeDef FMC_NORSRAM_Timing_Init(FMC_NORSRAM_TypeDef *Device, * @retval HAL status */ HAL_StatusTypeDef FMC_NORSRAM_Extended_Timing_Init(FMC_NORSRAM_EXTENDED_TypeDef *Device, - FMC_NORSRAM_TimingTypeDef *Timing, uint32_t Bank, + const FMC_NORSRAM_TimingTypeDef *Timing, uint32_t Bank, uint32_t ExtendedMode) { /* Check the parameters */ @@ -466,7 +466,6 @@ HAL_StatusTypeDef FMC_NORSRAM_WriteOperation_Disable(FMC_NORSRAM_TypeDef *Device * @} */ #endif /* FMC_BANK1 */ - #if defined(FMC_BANK3) /** @defgroup FMC_LL_Exported_Functions_NAND FMC Low Layer NAND Exported Functions @@ -518,7 +517,7 @@ HAL_StatusTypeDef FMC_NORSRAM_WriteOperation_Disable(FMC_NORSRAM_TypeDef *Device * @param Init Pointer to NAND Initialization structure * @retval HAL status */ -HAL_StatusTypeDef FMC_NAND_Init(FMC_NAND_TypeDef *Device, FMC_NAND_InitTypeDef *Init) +HAL_StatusTypeDef FMC_NAND_Init(FMC_NAND_TypeDef *Device, const FMC_NAND_InitTypeDef *Init) { /* Check the parameters */ assert_param(IS_FMC_NAND_DEVICE(Device)); @@ -566,7 +565,7 @@ HAL_StatusTypeDef FMC_NAND_Init(FMC_NAND_TypeDef *Device, FMC_NAND_InitTypeDef * * @retval HAL status */ HAL_StatusTypeDef FMC_NAND_CommonSpace_Timing_Init(FMC_NAND_TypeDef *Device, - FMC_NAND_PCC_TimingTypeDef *Timing, uint32_t Bank) + const FMC_NAND_PCC_TimingTypeDef *Timing, uint32_t Bank) { /* Check the parameters */ assert_param(IS_FMC_NAND_DEVICE(Device)); @@ -580,18 +579,18 @@ HAL_StatusTypeDef FMC_NAND_CommonSpace_Timing_Init(FMC_NAND_TypeDef *Device, if (Bank == FMC_NAND_BANK2) { /* NAND bank 2 registers configuration */ - MODIFY_REG(Device->PMEM2, PMEM_CLEAR_MASK, (Timing->SetupTime | - ((Timing->WaitSetupTime) << FMC_PMEMx_MEMWAITx_Pos) | - ((Timing->HoldSetupTime) << FMC_PMEMx_MEMHOLDx_Pos) | - ((Timing->HiZSetupTime) << FMC_PMEMx_MEMHIZx_Pos))); + WRITE_REG(Device->PMEM2, (Timing->SetupTime | + ((Timing->WaitSetupTime) << FMC_PMEMx_MEMWAITx_Pos) | + ((Timing->HoldSetupTime) << FMC_PMEMx_MEMHOLDx_Pos) | + ((Timing->HiZSetupTime) << FMC_PMEMx_MEMHIZx_Pos))); } else { /* NAND bank 3 registers configuration */ - MODIFY_REG(Device->PMEM3, PMEM_CLEAR_MASK, (Timing->SetupTime | - ((Timing->WaitSetupTime) << FMC_PMEMx_MEMWAITx_Pos) | - ((Timing->HoldSetupTime) << FMC_PMEMx_MEMHOLDx_Pos) | - ((Timing->HiZSetupTime) << FMC_PMEMx_MEMHIZx_Pos))); + WRITE_REG(Device->PMEM3, (Timing->SetupTime | + ((Timing->WaitSetupTime) << FMC_PMEMx_MEMWAITx_Pos) | + ((Timing->HoldSetupTime) << FMC_PMEMx_MEMHOLDx_Pos) | + ((Timing->HiZSetupTime) << FMC_PMEMx_MEMHIZx_Pos))); } return HAL_OK; @@ -606,7 +605,7 @@ HAL_StatusTypeDef FMC_NAND_CommonSpace_Timing_Init(FMC_NAND_TypeDef *Device, * @retval HAL status */ HAL_StatusTypeDef FMC_NAND_AttributeSpace_Timing_Init(FMC_NAND_TypeDef *Device, - FMC_NAND_PCC_TimingTypeDef *Timing, uint32_t Bank) + const FMC_NAND_PCC_TimingTypeDef *Timing, uint32_t Bank) { /* Check the parameters */ assert_param(IS_FMC_NAND_DEVICE(Device)); @@ -620,18 +619,18 @@ HAL_StatusTypeDef FMC_NAND_AttributeSpace_Timing_Init(FMC_NAND_TypeDef *Device, if (Bank == FMC_NAND_BANK2) { /* NAND bank 2 registers configuration */ - MODIFY_REG(Device->PATT2, PATT_CLEAR_MASK, (Timing->SetupTime | - ((Timing->WaitSetupTime) << FMC_PATTx_ATTWAITx_Pos) | - ((Timing->HoldSetupTime) << FMC_PATTx_ATTHOLDx_Pos) | - ((Timing->HiZSetupTime) << FMC_PATTx_ATTHIZx_Pos))); + WRITE_REG(Device->PATT2, (Timing->SetupTime | + ((Timing->WaitSetupTime) << FMC_PATTx_ATTWAITx_Pos) | + ((Timing->HoldSetupTime) << FMC_PATTx_ATTHOLDx_Pos) | + ((Timing->HiZSetupTime) << FMC_PATTx_ATTHIZx_Pos))); } else { /* NAND bank 3 registers configuration */ - MODIFY_REG(Device->PATT3, PATT_CLEAR_MASK, (Timing->SetupTime | - ((Timing->WaitSetupTime) << FMC_PATTx_ATTWAITx_Pos) | - ((Timing->HoldSetupTime) << FMC_PATTx_ATTHOLDx_Pos) | - ((Timing->HiZSetupTime) << FMC_PATTx_ATTHIZx_Pos))); + WRITE_REG(Device->PATT3, (Timing->SetupTime | + ((Timing->WaitSetupTime) << FMC_PATTx_ATTWAITx_Pos) | + ((Timing->HoldSetupTime) << FMC_PATTx_ATTHOLDx_Pos) | + ((Timing->HiZSetupTime) << FMC_PATTx_ATTHIZx_Pos))); } return HAL_OK; @@ -753,7 +752,7 @@ HAL_StatusTypeDef FMC_NAND_ECC_Disable(FMC_NAND_TypeDef *Device, uint32_t Bank) * @param Timeout Timeout wait value * @retval HAL status */ -HAL_StatusTypeDef FMC_NAND_GetECC(FMC_NAND_TypeDef *Device, uint32_t *ECCval, uint32_t Bank, +HAL_StatusTypeDef FMC_NAND_GetECC(const FMC_NAND_TypeDef *Device, uint32_t *ECCval, uint32_t Bank, uint32_t Timeout) { uint32_t tickstart; @@ -796,7 +795,6 @@ HAL_StatusTypeDef FMC_NAND_GetECC(FMC_NAND_TypeDef *Device, uint32_t *ECCval, ui * @} */ #endif /* FMC_BANK3 */ - #if defined(FMC_BANK4) /** @addtogroup FMC_LL_PCCARD @@ -846,7 +844,7 @@ HAL_StatusTypeDef FMC_NAND_GetECC(FMC_NAND_TypeDef *Device, uint32_t *ECCval, ui * @param Init Pointer to PCCARD Initialization structure * @retval HAL status */ -HAL_StatusTypeDef FMC_PCCARD_Init(FMC_PCCARD_TypeDef *Device, FMC_PCCARD_InitTypeDef *Init) +HAL_StatusTypeDef FMC_PCCARD_Init(FMC_PCCARD_TypeDef *Device, const FMC_PCCARD_InitTypeDef *Init) { /* Check the parameters */ assert_param(IS_FMC_PCCARD_DEVICE(Device)); @@ -880,7 +878,7 @@ HAL_StatusTypeDef FMC_PCCARD_Init(FMC_PCCARD_TypeDef *Device, FMC_PCCARD_InitTyp * @retval HAL status */ HAL_StatusTypeDef FMC_PCCARD_CommonSpace_Timing_Init(FMC_PCCARD_TypeDef *Device, - FMC_NAND_PCC_TimingTypeDef *Timing) + const FMC_NAND_PCC_TimingTypeDef *Timing) { /* Check the parameters */ assert_param(IS_FMC_PCCARD_DEVICE(Device)); @@ -892,11 +890,10 @@ HAL_StatusTypeDef FMC_PCCARD_CommonSpace_Timing_Init(FMC_PCCARD_TypeDef *Device, #endif /* FMC_BANK3 */ /* Set PCCARD timing parameters */ - MODIFY_REG(Device->PMEM4, PMEM4_CLEAR_MASK, - (Timing->SetupTime | - ((Timing->WaitSetupTime) << FMC_PMEM4_MEMWAIT4_Pos) | - ((Timing->HoldSetupTime) << FMC_PMEM4_MEMHOLD4_Pos) | - ((Timing->HiZSetupTime) << FMC_PMEM4_MEMHIZ4_Pos))); + WRITE_REG(Device->PMEM4, (Timing->SetupTime | + ((Timing->WaitSetupTime) << FMC_PMEM4_MEMWAIT4_Pos) | + ((Timing->HoldSetupTime) << FMC_PMEM4_MEMHOLD4_Pos) | + ((Timing->HiZSetupTime) << FMC_PMEM4_MEMHIZ4_Pos))); return HAL_OK; } @@ -909,7 +906,7 @@ HAL_StatusTypeDef FMC_PCCARD_CommonSpace_Timing_Init(FMC_PCCARD_TypeDef *Device, * @retval HAL status */ HAL_StatusTypeDef FMC_PCCARD_AttributeSpace_Timing_Init(FMC_PCCARD_TypeDef *Device, - FMC_NAND_PCC_TimingTypeDef *Timing) + const FMC_NAND_PCC_TimingTypeDef *Timing) { /* Check the parameters */ assert_param(IS_FMC_PCCARD_DEVICE(Device)); @@ -921,11 +918,10 @@ HAL_StatusTypeDef FMC_PCCARD_AttributeSpace_Timing_Init(FMC_PCCARD_TypeDef *Devi #endif /* FMC_BANK3 */ /* Set PCCARD timing parameters */ - MODIFY_REG(Device->PATT4, PATT4_CLEAR_MASK, - (Timing->SetupTime | - ((Timing->WaitSetupTime) << FMC_PATT4_ATTWAIT4_Pos) | - ((Timing->HoldSetupTime) << FMC_PATT4_ATTHOLD4_Pos) | - ((Timing->HiZSetupTime) << FMC_PATT4_ATTHIZ4_Pos))); + WRITE_REG(Device->PATT4, (Timing->SetupTime | + ((Timing->WaitSetupTime) << FMC_PATT4_ATTWAIT4_Pos) | + ((Timing->HoldSetupTime) << FMC_PATT4_ATTHOLD4_Pos) | + ((Timing->HiZSetupTime) << FMC_PATT4_ATTHIZ4_Pos))); return HAL_OK; } @@ -938,7 +934,7 @@ HAL_StatusTypeDef FMC_PCCARD_AttributeSpace_Timing_Init(FMC_PCCARD_TypeDef *Devi * @retval HAL status */ HAL_StatusTypeDef FMC_PCCARD_IOSpace_Timing_Init(FMC_PCCARD_TypeDef *Device, - FMC_NAND_PCC_TimingTypeDef *Timing) + const FMC_NAND_PCC_TimingTypeDef *Timing) { /* Check the parameters */ assert_param(IS_FMC_PCCARD_DEVICE(Device)); @@ -950,11 +946,10 @@ HAL_StatusTypeDef FMC_PCCARD_IOSpace_Timing_Init(FMC_PCCARD_TypeDef *Device, #endif /* FMC_BANK3 */ /* Set FMC_PCCARD device timing parameters */ - MODIFY_REG(Device->PIO4, PIO4_CLEAR_MASK, - (Timing->SetupTime | - (Timing->WaitSetupTime << FMC_PIO4_IOWAIT4_Pos) | - (Timing->HoldSetupTime << FMC_PIO4_IOHOLD4_Pos) | - (Timing->HiZSetupTime << FMC_PIO4_IOHIZ4_Pos))); + WRITE_REG(Device->PIO4, (Timing->SetupTime | + (Timing->WaitSetupTime << FMC_PIO4_IOWAIT4_Pos) | + (Timing->HoldSetupTime << FMC_PIO4_IOHOLD4_Pos) | + (Timing->HiZSetupTime << FMC_PIO4_IOHIZ4_Pos))); return HAL_OK; } @@ -987,7 +982,6 @@ HAL_StatusTypeDef FMC_PCCARD_DeInit(FMC_PCCARD_TypeDef *Device) */ #endif /* FMC_BANK4 */ - /** * @} */ diff --git a/system/Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_ll_gpio.c b/system/Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_ll_gpio.c index 95c56a8762..51939c88ec 100644 --- a/system/Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_ll_gpio.c +++ b/system/Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_ll_gpio.c @@ -59,7 +59,7 @@ /** @addtogroup GPIO_LL_Private_Macros * @{ */ -#define IS_LL_GPIO_PIN(__VALUE__) (((0x00u) < (__VALUE__)) && ((__VALUE__) <= (LL_GPIO_PIN_ALL))) +#define IS_LL_GPIO_PIN(__VALUE__) (((0x00U) < (__VALUE__)) && ((__VALUE__) <= (LL_GPIO_PIN_ALL))) #define IS_LL_GPIO_MODE(__VALUE__) (((__VALUE__) == LL_GPIO_MODE_INPUT) ||\ ((__VALUE__) == LL_GPIO_MODE_OUTPUT) ||\ @@ -206,12 +206,12 @@ ErrorStatus LL_GPIO_Init(GPIO_TypeDef *GPIOx, LL_GPIO_InitTypeDef *GPIO_InitStru pinpos = POSITION_VAL(GPIO_InitStruct->Pin); /* Configure the port pins */ - while (((GPIO_InitStruct->Pin) >> pinpos) != 0x00u) + while (((GPIO_InitStruct->Pin) >> pinpos) != 0x00U) { /* Get current io position */ - currentpin = (GPIO_InitStruct->Pin) & (0x00000001uL << pinpos); + currentpin = (GPIO_InitStruct->Pin) & (0x00000001UL << pinpos); - if (currentpin != 0x00u) + if (currentpin != 0x00U) { if ((GPIO_InitStruct->Mode == LL_GPIO_MODE_OUTPUT) || (GPIO_InitStruct->Mode == LL_GPIO_MODE_ALTERNATE)) { diff --git a/system/Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_ll_hrtim.c b/system/Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_ll_hrtim.c index 795bc5d4ee..d793b11f3f 100644 --- a/system/Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_ll_hrtim.c +++ b/system/Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_ll_hrtim.c @@ -53,15 +53,27 @@ * - SUCCESS: HRTIMx registers are de-initialized * - ERROR: invalid HRTIMx instance */ -ErrorStatus LL_HRTIM_DeInit(HRTIM_TypeDef *HRTIMx) +ErrorStatus LL_HRTIM_DeInit(const HRTIM_TypeDef *HRTIMx) { - ErrorStatus result = SUCCESS; + ErrorStatus status = SUCCESS; /* Check the parameters */ assert_param(IS_HRTIM_ALL_INSTANCE(HRTIMx)); - LL_APB2_GRP1_ForceReset(LL_APB2_GRP1_PERIPH_HRTIM1); - LL_APB2_GRP1_ReleaseReset(LL_APB2_GRP1_PERIPH_HRTIM1); - return result; + + if (HRTIMx == HRTIM1) + { + /* Force HRTIM reset */ + LL_APB2_GRP1_ForceReset(LL_APB2_GRP1_PERIPH_HRTIM1); + + /* Release HRTIM reset */ + LL_APB2_GRP1_ReleaseReset(LL_APB2_GRP1_PERIPH_HRTIM1); + } + else + { + status = ERROR; + } + + return status; } /** * @} diff --git a/system/Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_ll_spi.c b/system/Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_ll_spi.c index 2312771a58..5dd6bb4a1b 100644 --- a/system/Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_ll_spi.c +++ b/system/Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_ll_spi.c @@ -130,7 +130,7 @@ * - SUCCESS: SPI registers are de-initialized * - ERROR: SPI registers are not de-initialized */ -ErrorStatus LL_SPI_DeInit(SPI_TypeDef *SPIx) +ErrorStatus LL_SPI_DeInit(const SPI_TypeDef *SPIx) { ErrorStatus status = ERROR; @@ -191,8 +191,9 @@ ErrorStatus LL_SPI_DeInit(SPI_TypeDef *SPIx) /** * @brief Initialize the SPI registers according to the specified parameters in SPI_InitStruct. - * @note As some bits in SPI configuration registers can only be written when the SPI is disabled (SPI_CR1_SPE bit =0), - * SPI peripheral should be in disabled state prior calling this function. Otherwise, ERROR result will be returned. + * @note As some bits in SPI configuration registers can only be written when the + * SPI is disabled (SPI_CR1_SPE bit = 0), SPI peripheral should be in disabled state prior + * calling this function. Otherwise, ERROR result will be returned. * @param SPIx SPI Instance * @param SPI_InitStruct pointer to a @ref LL_SPI_InitTypeDef structure * @retval An ErrorStatus enumeration value. (Return always SUCCESS) @@ -379,7 +380,7 @@ void LL_SPI_StructInit(LL_SPI_InitTypeDef *SPI_InitStruct) * - SUCCESS: SPI registers are de-initialized * - ERROR: SPI registers are not de-initialized */ -ErrorStatus LL_I2S_DeInit(SPI_TypeDef *SPIx) +ErrorStatus LL_I2S_DeInit(const SPI_TypeDef *SPIx) { return LL_SPI_DeInit(SPIx); } @@ -394,7 +395,7 @@ ErrorStatus LL_I2S_DeInit(SPI_TypeDef *SPIx) * - SUCCESS: SPI registers are Initialized * - ERROR: SPI registers are not Initialized */ -ErrorStatus LL_I2S_Init(SPI_TypeDef *SPIx, LL_I2S_InitTypeDef *I2S_InitStruct) +ErrorStatus LL_I2S_Init(SPI_TypeDef *SPIx,const LL_I2S_InitTypeDef *I2S_InitStruct) { uint32_t i2sdiv = 2U; uint32_t i2sodd = 0U; diff --git a/system/Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_ll_tim.c b/system/Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_ll_tim.c index 653ed07681..3485b85a4f 100644 --- a/system/Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_ll_tim.c +++ b/system/Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_ll_tim.c @@ -677,8 +677,6 @@ void LL_TIM_HALLSENSOR_StructInit(LL_TIM_HALLSENSOR_InitTypeDef *TIM_HallSensorI * @note Channel 2 is configured in output PWM 2 mode. * @note Compare value stored in TIMx_CCR2 corresponds to the commutation delay. * @note OC2REF is selected as trigger output on TRGO. - * @note LL_TIM_IC_POLARITY_BOTHEDGE must not be used for TI1 when it is used - * when TIMx operates in Hall sensor interface mode. * @param TIMx Timer Instance * @param TIM_HallSensorInitStruct pointer to a @ref LL_TIM_HALLSENSOR_InitTypeDef structure (TIMx HALL sensor * interface configuration data structure) @@ -738,7 +736,7 @@ ErrorStatus LL_TIM_HALLSENSOR_Init(TIM_TypeDef *TIMx, const LL_TIM_HALLSENSOR_In /* Set Channel 1 polarity and enable Channel 1 and Channel2 */ tmpccer &= (uint32_t)~(TIM_CCER_CC1P | TIM_CCER_CC1NP | TIM_CCER_CC2P | TIM_CCER_CC2NP); tmpccer |= (uint32_t)(TIM_HallSensorInitStruct->IC1Polarity); - tmpccer |= (uint32_t)(TIM_CCER_CC1E | TIM_CCER_CC2E); + tmpccer |= (uint32_t)(TIM_CCER_CC1E); /* Write to TIMx CR2 */ LL_TIM_WriteReg(TIMx, CR2, tmpcr2); diff --git a/system/Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_ll_usb.c b/system/Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_ll_usb.c index b31bd604e1..bc58e7bfa7 100644 --- a/system/Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_ll_usb.c +++ b/system/Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_ll_usb.c @@ -33,6 +33,9 @@ (#) The upper HAL HCD/PCD driver will call the right routines for its internal processes. + (#)NOTE: For applications not using double buffer mode, define the symbol + 'USE_USB_DOUBLE_BUFFER' as 0 to reduce the driver's memory footprint. + @endverbatim ****************************************************************************** @@ -61,7 +64,7 @@ * the configuration information for the specified USBx peripheral. * @retval HAL status */ -HAL_StatusTypeDef USB_CoreInit(USB_TypeDef *USBx, USB_CfgTypeDef cfg) +HAL_StatusTypeDef USB_CoreInit(USB_TypeDef const *USBx, USB_CfgTypeDef cfg) { /* Prevent unused argument(s) compilation warning */ UNUSED(USBx); @@ -130,7 +133,7 @@ HAL_StatusTypeDef USB_DisableGlobalInt(USB_TypeDef *USBx) * @arg USB_DEVICE_MODE Peripheral mode * @retval HAL status */ -HAL_StatusTypeDef USB_SetCurrentMode(USB_TypeDef *USBx, USB_ModeTypeDef mode) +HAL_StatusTypeDef USB_SetCurrentMode(USB_TypeDef const *USBx, USB_ModeTypeDef mode) { /* Prevent unused argument(s) compilation warning */ UNUSED(USBx); @@ -319,6 +322,10 @@ HAL_StatusTypeDef USB_ActivateEndpoint(USB_TypeDef *USBx, USB_EPTypeDef *ep) PCD_CLEAR_RX_DTOG(USBx, ep->num); PCD_CLEAR_TX_DTOG(USBx, ep->num); + /* Set endpoint RX count */ + PCD_SET_EP_DBUF_CNT(USBx, ep->num, ep->is_in, ep->maxpacket); + + /* Set endpoint RX to valid state */ PCD_SET_EP_RX_STATUS(USBx, ep->num, USB_EP_RX_VALID); PCD_SET_EP_TX_STATUS(USBx, ep->num, USB_EP_TX_DIS); } @@ -423,7 +430,7 @@ HAL_StatusTypeDef USB_EPStartXfer(USB_TypeDef *USBx, USB_EPTypeDef *ep) /* IN endpoint */ if (ep->is_in == 1U) { - /*Multi packet transfer*/ + /* Multi packet transfer */ if (ep->xfer_len > ep->maxpacket) { len = ep->maxpacket; @@ -525,9 +532,9 @@ HAL_StatusTypeDef USB_EPStartXfer(USB_TypeDef *USBx, USB_EPTypeDef *ep) USB_WritePMA(USBx, ep->xfer_buff, pmabuffer, (uint16_t)len); } } - else /* manage isochronous double buffer IN mode */ + else /* Manage isochronous double buffer IN mode */ { - /* each Time to write in PMA xfer_len_db will */ + /* Each Time to write in PMA xfer_len_db will */ ep->xfer_len_db -= len; /* Fill the data buffer */ @@ -559,19 +566,25 @@ HAL_StatusTypeDef USB_EPStartXfer(USB_TypeDef *USBx, USB_EPTypeDef *ep) { if (ep->doublebuffer == 0U) { + if ((ep->xfer_len == 0U) && (ep->type == EP_TYPE_CTRL)) + { + /* This is a status out stage set the OUT_STATUS */ + PCD_SET_OUT_STATUS(USBx, ep->num); + } + else + { + PCD_CLEAR_OUT_STATUS(USBx, ep->num); + } + /* Multi packet transfer */ if (ep->xfer_len > ep->maxpacket) { - len = ep->maxpacket; - ep->xfer_len -= len; + ep->xfer_len -= ep->maxpacket; } else { - len = ep->xfer_len; ep->xfer_len = 0U; } - /* configure and validate Rx endpoint */ - PCD_SET_EP_RX_CNT(USBx, ep->num, len); } #if (USE_USB_DOUBLE_BUFFER == 1U) else @@ -580,15 +593,13 @@ HAL_StatusTypeDef USB_EPStartXfer(USB_TypeDef *USBx, USB_EPTypeDef *ep) /* Set the Double buffer counter */ if (ep->type == EP_TYPE_BULK) { - PCD_SET_EP_DBUF_CNT(USBx, ep->num, ep->is_in, ep->maxpacket); - /* Coming from ISR */ if (ep->xfer_count != 0U) { - /* update last value to check if there is blocking state */ + /* Update last value to check if there is blocking state */ wEPVal = PCD_GET_ENDPOINT(USBx, ep->num); - /*Blocking State */ + /* Blocking State */ if ((((wEPVal & USB_EP_DTOG_RX) != 0U) && ((wEPVal & USB_EP_DTOG_TX) != 0U)) || (((wEPVal & USB_EP_DTOG_RX) == 0U) && ((wEPVal & USB_EP_DTOG_TX) == 0U))) { @@ -599,18 +610,8 @@ HAL_StatusTypeDef USB_EPStartXfer(USB_TypeDef *USBx, USB_EPTypeDef *ep) /* iso out double */ else if (ep->type == EP_TYPE_ISOC) { - /* Multi packet transfer */ - if (ep->xfer_len > ep->maxpacket) - { - len = ep->maxpacket; - ep->xfer_len -= len; - } - else - { - len = ep->xfer_len; - ep->xfer_len = 0U; - } - PCD_SET_EP_DBUF_CNT(USBx, ep->num, ep->is_in, len); + /* Only single packet transfer supported in FS */ + ep->xfer_len = 0U; } else { @@ -654,26 +655,23 @@ HAL_StatusTypeDef USB_EPSetStall(USB_TypeDef *USBx, USB_EPTypeDef *ep) */ HAL_StatusTypeDef USB_EPClearStall(USB_TypeDef *USBx, USB_EPTypeDef *ep) { - if (ep->doublebuffer == 0U) + if (ep->is_in != 0U) { - if (ep->is_in != 0U) - { - PCD_CLEAR_TX_DTOG(USBx, ep->num); + PCD_CLEAR_TX_DTOG(USBx, ep->num); - if (ep->type != EP_TYPE_ISOC) - { - /* Configure NAK status for the Endpoint */ - PCD_SET_EP_TX_STATUS(USBx, ep->num, USB_EP_TX_NAK); - } - } - else + if (ep->type != EP_TYPE_ISOC) { - PCD_CLEAR_RX_DTOG(USBx, ep->num); - - /* Configure VALID status for the Endpoint */ - PCD_SET_EP_RX_STATUS(USBx, ep->num, USB_EP_RX_VALID); + /* Configure NAK status for the Endpoint */ + PCD_SET_EP_TX_STATUS(USBx, ep->num, USB_EP_TX_NAK); } } + else + { + PCD_CLEAR_RX_DTOG(USBx, ep->num); + + /* Configure VALID status for the Endpoint */ + PCD_SET_EP_RX_STATUS(USBx, ep->num, USB_EP_RX_VALID); + } return HAL_OK; } @@ -909,6 +907,16 @@ void USB_ReadPMA(USB_TypeDef const *USBx, uint8_t *pbUsrBuf, uint16_t wPMABufAdd } } +/** + * @brief Return Current Frame number + * @param USBx Selected device + * @retval current frame number + */ +uint32_t USB_GetCurrentFrame(USB_TypeDef const *USBx) +{ + return (uint32_t)(USBx->FNR & 0x7FFU); +} + /** * @} diff --git a/system/Drivers/STM32YYxx_HAL_Driver_version.md b/system/Drivers/STM32YYxx_HAL_Driver_version.md index 05cd9b2113..1ce8686ff2 100644 --- a/system/Drivers/STM32YYxx_HAL_Driver_version.md +++ b/system/Drivers/STM32YYxx_HAL_Driver_version.md @@ -5,7 +5,7 @@ * STM32F0: 1.7.8 * STM32F1: 1.1.10 * STM32F2: 1.2.9 - * STM32F3: 1.5.8 + * STM32F3: 1.5.9 * STM32F4: 1.8.5 * STM32F7: 1.3.3 * STM32G0: 1.4.7 From d25ec07dcaf566f49a24d4724a8084516355f287 Mon Sep 17 00:00:00 2001 From: Frederic Pillon Date: Mon, 2 Nov 2026 16:07:47 +0100 Subject: [PATCH 2/2] system(f3): update STM32F3xx CMSIS Drivers to v2.3.9 Included in STM32CubeF3 FW v1.12.0 Signed-off-by: Frederic Pillon --- .../Device/ST/STM32F3xx/Include/stm32f301x8.h | 356 ++++++++++------- .../Device/ST/STM32F3xx/Include/stm32f302x8.h | 356 ++++++++++------- .../Device/ST/STM32F3xx/Include/stm32f302xc.h | 360 +++++++++++------- .../Device/ST/STM32F3xx/Include/stm32f302xe.h | 360 +++++++++++------- .../Device/ST/STM32F3xx/Include/stm32f303x8.h | 356 ++++++++++------- .../Device/ST/STM32F3xx/Include/stm32f303xc.h | 356 ++++++++++------- .../Device/ST/STM32F3xx/Include/stm32f303xe.h | 356 ++++++++++------- .../Device/ST/STM32F3xx/Include/stm32f318xx.h | 360 +++++++++++------- .../Device/ST/STM32F3xx/Include/stm32f328xx.h | 356 ++++++++++------- .../Device/ST/STM32F3xx/Include/stm32f334x8.h | 360 +++++++++++------- .../Device/ST/STM32F3xx/Include/stm32f358xx.h | 356 ++++++++++------- .../Device/ST/STM32F3xx/Include/stm32f373xc.h | 246 ++++++++---- .../Device/ST/STM32F3xx/Include/stm32f378xx.h | 246 ++++++++---- .../Device/ST/STM32F3xx/Include/stm32f398xx.h | 356 ++++++++++------- .../Device/ST/STM32F3xx/Include/stm32f3xx.h | 4 +- .../CMSIS/Device/ST/STM32F3xx/LICENSE.md | 2 +- .../CMSIS/Device/ST/STM32F3xx/README.md | 2 +- .../Device/ST/STM32F3xx/Release_Notes.html | 49 ++- .../Device/ST/STM32F3xx/Release_Notes.md | 352 +++++++++++++++++ .../Source/Templates/system_stm32f3xx.c | 18 +- .../Device/ST/STM32YYxx_CMSIS_version.md | 2 +- 21 files changed, 3364 insertions(+), 1845 deletions(-) create mode 100644 system/Drivers/CMSIS/Device/ST/STM32F3xx/Release_Notes.md diff --git a/system/Drivers/CMSIS/Device/ST/STM32F3xx/Include/stm32f301x8.h b/system/Drivers/CMSIS/Device/ST/STM32F3xx/Include/stm32f301x8.h index fffbc4cf67..ee3ecd3c56 100644 --- a/system/Drivers/CMSIS/Device/ST/STM32F3xx/Include/stm32f301x8.h +++ b/system/Drivers/CMSIS/Device/ST/STM32F3xx/Include/stm32f301x8.h @@ -1617,70 +1617,70 @@ typedef struct #define ADC_AWD2CR_AWD2CH_Pos (1U) #define ADC_AWD2CR_AWD2CH_Msk (0x3FFFFUL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x0003FFFF */ #define ADC_AWD2CR_AWD2CH ADC_AWD2CR_AWD2CH_Msk /*!< ADC analog watchdog 2 monitored channel selection */ -#define ADC_AWD2CR_AWD2CH_0 (0x00001UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000001 */ -#define ADC_AWD2CR_AWD2CH_1 (0x00002UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000002 */ -#define ADC_AWD2CR_AWD2CH_2 (0x00004UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000004 */ -#define ADC_AWD2CR_AWD2CH_3 (0x00008UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000008 */ -#define ADC_AWD2CR_AWD2CH_4 (0x00010UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000010 */ -#define ADC_AWD2CR_AWD2CH_5 (0x00020UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000020 */ -#define ADC_AWD2CR_AWD2CH_6 (0x00040UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000040 */ -#define ADC_AWD2CR_AWD2CH_7 (0x00080UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000080 */ -#define ADC_AWD2CR_AWD2CH_8 (0x00100UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000100 */ -#define ADC_AWD2CR_AWD2CH_9 (0x00200UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000200 */ -#define ADC_AWD2CR_AWD2CH_10 (0x00400UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000400 */ -#define ADC_AWD2CR_AWD2CH_11 (0x00800UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000800 */ -#define ADC_AWD2CR_AWD2CH_12 (0x01000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00001000 */ -#define ADC_AWD2CR_AWD2CH_13 (0x02000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00002000 */ -#define ADC_AWD2CR_AWD2CH_14 (0x04000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00004000 */ -#define ADC_AWD2CR_AWD2CH_15 (0x08000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00008000 */ -#define ADC_AWD2CR_AWD2CH_16 (0x10000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00010000 */ -#define ADC_AWD2CR_AWD2CH_17 (0x20000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00020000 */ +#define ADC_AWD2CR_AWD2CH_0 (0x00001UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000002 */ +#define ADC_AWD2CR_AWD2CH_1 (0x00002UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000004 */ +#define ADC_AWD2CR_AWD2CH_2 (0x00004UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000008 */ +#define ADC_AWD2CR_AWD2CH_3 (0x00008UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000010 */ +#define ADC_AWD2CR_AWD2CH_4 (0x00010UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000020 */ +#define ADC_AWD2CR_AWD2CH_5 (0x00020UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000040 */ +#define ADC_AWD2CR_AWD2CH_6 (0x00040UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000080 */ +#define ADC_AWD2CR_AWD2CH_7 (0x00080UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000100 */ +#define ADC_AWD2CR_AWD2CH_8 (0x00100UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000200 */ +#define ADC_AWD2CR_AWD2CH_9 (0x00200UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000400 */ +#define ADC_AWD2CR_AWD2CH_10 (0x00400UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000800 */ +#define ADC_AWD2CR_AWD2CH_11 (0x00800UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00001000 */ +#define ADC_AWD2CR_AWD2CH_12 (0x01000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00002000 */ +#define ADC_AWD2CR_AWD2CH_13 (0x02000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00004000 */ +#define ADC_AWD2CR_AWD2CH_14 (0x04000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00008000 */ +#define ADC_AWD2CR_AWD2CH_15 (0x08000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00010000 */ +#define ADC_AWD2CR_AWD2CH_16 (0x10000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00020000 */ +#define ADC_AWD2CR_AWD2CH_17 (0x20000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00040000 */ /******************** Bit definition for ADC_AWD3CR register ****************/ #define ADC_AWD3CR_AWD3CH_Pos (1U) #define ADC_AWD3CR_AWD3CH_Msk (0x3FFFFUL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x0003FFFF */ #define ADC_AWD3CR_AWD3CH ADC_AWD3CR_AWD3CH_Msk /*!< ADC analog watchdog 3 monitored channel selection */ -#define ADC_AWD3CR_AWD3CH_0 (0x00001UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000001 */ -#define ADC_AWD3CR_AWD3CH_1 (0x00002UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000002 */ -#define ADC_AWD3CR_AWD3CH_2 (0x00004UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000004 */ -#define ADC_AWD3CR_AWD3CH_3 (0x00008UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000008 */ -#define ADC_AWD3CR_AWD3CH_4 (0x00010UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000010 */ -#define ADC_AWD3CR_AWD3CH_5 (0x00020UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000020 */ -#define ADC_AWD3CR_AWD3CH_6 (0x00040UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000040 */ -#define ADC_AWD3CR_AWD3CH_7 (0x00080UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000080 */ -#define ADC_AWD3CR_AWD3CH_8 (0x00100UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000100 */ -#define ADC_AWD3CR_AWD3CH_9 (0x00200UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000200 */ -#define ADC_AWD3CR_AWD3CH_10 (0x00400UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000400 */ -#define ADC_AWD3CR_AWD3CH_11 (0x00800UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000800 */ -#define ADC_AWD3CR_AWD3CH_12 (0x01000UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00001000 */ -#define ADC_AWD3CR_AWD3CH_13 (0x02000UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00002000 */ -#define ADC_AWD3CR_AWD3CH_14 (0x04000UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00004000 */ -#define ADC_AWD3CR_AWD3CH_15 (0x08000UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00008000 */ -#define ADC_AWD3CR_AWD3CH_16 (0x10000UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00010000 */ -#define ADC_AWD3CR_AWD3CH_17 (0x20000UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00020000 */ +#define ADC_AWD3CR_AWD3CH_0 (0x00001UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000002 */ +#define ADC_AWD3CR_AWD3CH_1 (0x00002UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000004 */ +#define ADC_AWD3CR_AWD3CH_2 (0x00004UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000008 */ +#define ADC_AWD3CR_AWD3CH_3 (0x00008UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000010 */ +#define ADC_AWD3CR_AWD3CH_4 (0x00010UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000020 */ +#define ADC_AWD3CR_AWD3CH_5 (0x00020UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000040 */ +#define ADC_AWD3CR_AWD3CH_6 (0x00040UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000080 */ +#define ADC_AWD3CR_AWD3CH_7 (0x00080UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000100 */ +#define ADC_AWD3CR_AWD3CH_8 (0x00100UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000200 */ +#define ADC_AWD3CR_AWD3CH_9 (0x00200UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000400 */ +#define ADC_AWD3CR_AWD3CH_10 (0x00400UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000800 */ +#define ADC_AWD3CR_AWD3CH_11 (0x00800UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00001000 */ +#define ADC_AWD3CR_AWD3CH_12 (0x01000UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00002000 */ +#define ADC_AWD3CR_AWD3CH_13 (0x02000UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00004000 */ +#define ADC_AWD3CR_AWD3CH_14 (0x04000UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00008000 */ +#define ADC_AWD3CR_AWD3CH_15 (0x08000UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00010000 */ +#define ADC_AWD3CR_AWD3CH_16 (0x10000UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00020000 */ +#define ADC_AWD3CR_AWD3CH_17 (0x20000UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00040000 */ /******************** Bit definition for ADC_DIFSEL register ****************/ #define ADC_DIFSEL_DIFSEL_Pos (1U) #define ADC_DIFSEL_DIFSEL_Msk (0x3FFFFUL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x0003FFFF */ #define ADC_DIFSEL_DIFSEL ADC_DIFSEL_DIFSEL_Msk /*!< ADC channel differential or single-ended mode */ -#define ADC_DIFSEL_DIFSEL_0 (0x00001UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000001 */ -#define ADC_DIFSEL_DIFSEL_1 (0x00002UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000002 */ -#define ADC_DIFSEL_DIFSEL_2 (0x00004UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000004 */ -#define ADC_DIFSEL_DIFSEL_3 (0x00008UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000008 */ -#define ADC_DIFSEL_DIFSEL_4 (0x00010UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000010 */ -#define ADC_DIFSEL_DIFSEL_5 (0x00020UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000020 */ -#define ADC_DIFSEL_DIFSEL_6 (0x00040UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000040 */ -#define ADC_DIFSEL_DIFSEL_7 (0x00080UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000080 */ -#define ADC_DIFSEL_DIFSEL_8 (0x00100UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000100 */ -#define ADC_DIFSEL_DIFSEL_9 (0x00200UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000200 */ -#define ADC_DIFSEL_DIFSEL_10 (0x00400UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000400 */ -#define ADC_DIFSEL_DIFSEL_11 (0x00800UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000800 */ -#define ADC_DIFSEL_DIFSEL_12 (0x01000UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00001000 */ -#define ADC_DIFSEL_DIFSEL_13 (0x02000UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00002000 */ -#define ADC_DIFSEL_DIFSEL_14 (0x04000UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00004000 */ -#define ADC_DIFSEL_DIFSEL_15 (0x08000UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00008000 */ -#define ADC_DIFSEL_DIFSEL_16 (0x10000UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00010000 */ -#define ADC_DIFSEL_DIFSEL_17 (0x20000UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00020000 */ +#define ADC_DIFSEL_DIFSEL_0 (0x00001UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000002 */ +#define ADC_DIFSEL_DIFSEL_1 (0x00002UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000004 */ +#define ADC_DIFSEL_DIFSEL_2 (0x00004UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000008 */ +#define ADC_DIFSEL_DIFSEL_3 (0x00008UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000010 */ +#define ADC_DIFSEL_DIFSEL_4 (0x00010UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000020 */ +#define ADC_DIFSEL_DIFSEL_5 (0x00020UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000040 */ +#define ADC_DIFSEL_DIFSEL_6 (0x00040UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000080 */ +#define ADC_DIFSEL_DIFSEL_7 (0x00080UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000100 */ +#define ADC_DIFSEL_DIFSEL_8 (0x00100UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000200 */ +#define ADC_DIFSEL_DIFSEL_9 (0x00200UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000400 */ +#define ADC_DIFSEL_DIFSEL_10 (0x00400UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000800 */ +#define ADC_DIFSEL_DIFSEL_11 (0x00800UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00001000 */ +#define ADC_DIFSEL_DIFSEL_12 (0x01000UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00002000 */ +#define ADC_DIFSEL_DIFSEL_13 (0x02000UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00004000 */ +#define ADC_DIFSEL_DIFSEL_14 (0x04000UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00008000 */ +#define ADC_DIFSEL_DIFSEL_15 (0x08000UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00010000 */ +#define ADC_DIFSEL_DIFSEL_16 (0x10000UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00020000 */ +#define ADC_DIFSEL_DIFSEL_17 (0x20000UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00040000 */ /******************** Bit definition for ADC_CALFACT register ***************/ #define ADC_CALFACT_CALFACT_S_Pos (0U) @@ -3951,86 +3951,168 @@ typedef struct #define GPIO_OTYPER_OT_15 (0x00008000U) /**************** Bit definition for GPIO_OSPEEDR register ******************/ -#define GPIO_OSPEEDER_OSPEEDR0_Pos (0U) -#define GPIO_OSPEEDER_OSPEEDR0_Msk (0x3UL << GPIO_OSPEEDER_OSPEEDR0_Pos) /*!< 0x00000003 */ -#define GPIO_OSPEEDER_OSPEEDR0 GPIO_OSPEEDER_OSPEEDR0_Msk -#define GPIO_OSPEEDER_OSPEEDR0_0 (0x1UL << GPIO_OSPEEDER_OSPEEDR0_Pos) /*!< 0x00000001 */ -#define GPIO_OSPEEDER_OSPEEDR0_1 (0x2UL << GPIO_OSPEEDER_OSPEEDR0_Pos) /*!< 0x00000002 */ -#define GPIO_OSPEEDER_OSPEEDR1_Pos (2U) -#define GPIO_OSPEEDER_OSPEEDR1_Msk (0x3UL << GPIO_OSPEEDER_OSPEEDR1_Pos) /*!< 0x0000000C */ -#define GPIO_OSPEEDER_OSPEEDR1 GPIO_OSPEEDER_OSPEEDR1_Msk -#define GPIO_OSPEEDER_OSPEEDR1_0 (0x1UL << GPIO_OSPEEDER_OSPEEDR1_Pos) /*!< 0x00000004 */ -#define GPIO_OSPEEDER_OSPEEDR1_1 (0x2UL << GPIO_OSPEEDER_OSPEEDR1_Pos) /*!< 0x00000008 */ -#define GPIO_OSPEEDER_OSPEEDR2_Pos (4U) -#define GPIO_OSPEEDER_OSPEEDR2_Msk (0x3UL << GPIO_OSPEEDER_OSPEEDR2_Pos) /*!< 0x00000030 */ -#define GPIO_OSPEEDER_OSPEEDR2 GPIO_OSPEEDER_OSPEEDR2_Msk -#define GPIO_OSPEEDER_OSPEEDR2_0 (0x1UL << GPIO_OSPEEDER_OSPEEDR2_Pos) /*!< 0x00000010 */ -#define GPIO_OSPEEDER_OSPEEDR2_1 (0x2UL << GPIO_OSPEEDER_OSPEEDR2_Pos) /*!< 0x00000020 */ -#define GPIO_OSPEEDER_OSPEEDR3_Pos (6U) -#define GPIO_OSPEEDER_OSPEEDR3_Msk (0x3UL << GPIO_OSPEEDER_OSPEEDR3_Pos) /*!< 0x000000C0 */ -#define GPIO_OSPEEDER_OSPEEDR3 GPIO_OSPEEDER_OSPEEDR3_Msk -#define GPIO_OSPEEDER_OSPEEDR3_0 (0x1UL << GPIO_OSPEEDER_OSPEEDR3_Pos) /*!< 0x00000040 */ -#define GPIO_OSPEEDER_OSPEEDR3_1 (0x2UL << GPIO_OSPEEDER_OSPEEDR3_Pos) /*!< 0x00000080 */ -#define GPIO_OSPEEDER_OSPEEDR4_Pos (8U) -#define GPIO_OSPEEDER_OSPEEDR4_Msk (0x3UL << GPIO_OSPEEDER_OSPEEDR4_Pos) /*!< 0x00000300 */ -#define GPIO_OSPEEDER_OSPEEDR4 GPIO_OSPEEDER_OSPEEDR4_Msk -#define GPIO_OSPEEDER_OSPEEDR4_0 (0x1UL << GPIO_OSPEEDER_OSPEEDR4_Pos) /*!< 0x00000100 */ -#define GPIO_OSPEEDER_OSPEEDR4_1 (0x2UL << GPIO_OSPEEDER_OSPEEDR4_Pos) /*!< 0x00000200 */ -#define GPIO_OSPEEDER_OSPEEDR5_Pos (10U) -#define GPIO_OSPEEDER_OSPEEDR5_Msk (0x3UL << GPIO_OSPEEDER_OSPEEDR5_Pos) /*!< 0x00000C00 */ -#define GPIO_OSPEEDER_OSPEEDR5 GPIO_OSPEEDER_OSPEEDR5_Msk -#define GPIO_OSPEEDER_OSPEEDR5_0 (0x1UL << GPIO_OSPEEDER_OSPEEDR5_Pos) /*!< 0x00000400 */ -#define GPIO_OSPEEDER_OSPEEDR5_1 (0x2UL << GPIO_OSPEEDER_OSPEEDR5_Pos) /*!< 0x00000800 */ -#define GPIO_OSPEEDER_OSPEEDR6_Pos (12U) -#define GPIO_OSPEEDER_OSPEEDR6_Msk (0x3UL << GPIO_OSPEEDER_OSPEEDR6_Pos) /*!< 0x00003000 */ -#define GPIO_OSPEEDER_OSPEEDR6 GPIO_OSPEEDER_OSPEEDR6_Msk -#define GPIO_OSPEEDER_OSPEEDR6_0 (0x1UL << GPIO_OSPEEDER_OSPEEDR6_Pos) /*!< 0x00001000 */ -#define GPIO_OSPEEDER_OSPEEDR6_1 (0x2UL << GPIO_OSPEEDER_OSPEEDR6_Pos) /*!< 0x00002000 */ -#define GPIO_OSPEEDER_OSPEEDR7_Pos (14U) -#define GPIO_OSPEEDER_OSPEEDR7_Msk (0x3UL << GPIO_OSPEEDER_OSPEEDR7_Pos) /*!< 0x0000C000 */ -#define GPIO_OSPEEDER_OSPEEDR7 GPIO_OSPEEDER_OSPEEDR7_Msk -#define GPIO_OSPEEDER_OSPEEDR7_0 (0x1UL << GPIO_OSPEEDER_OSPEEDR7_Pos) /*!< 0x00004000 */ -#define GPIO_OSPEEDER_OSPEEDR7_1 (0x2UL << GPIO_OSPEEDER_OSPEEDR7_Pos) /*!< 0x00008000 */ -#define GPIO_OSPEEDER_OSPEEDR8_Pos (16U) -#define GPIO_OSPEEDER_OSPEEDR8_Msk (0x3UL << GPIO_OSPEEDER_OSPEEDR8_Pos) /*!< 0x00030000 */ -#define GPIO_OSPEEDER_OSPEEDR8 GPIO_OSPEEDER_OSPEEDR8_Msk -#define GPIO_OSPEEDER_OSPEEDR8_0 (0x1UL << GPIO_OSPEEDER_OSPEEDR8_Pos) /*!< 0x00010000 */ -#define GPIO_OSPEEDER_OSPEEDR8_1 (0x2UL << GPIO_OSPEEDER_OSPEEDR8_Pos) /*!< 0x00020000 */ -#define GPIO_OSPEEDER_OSPEEDR9_Pos (18U) -#define GPIO_OSPEEDER_OSPEEDR9_Msk (0x3UL << GPIO_OSPEEDER_OSPEEDR9_Pos) /*!< 0x000C0000 */ -#define GPIO_OSPEEDER_OSPEEDR9 GPIO_OSPEEDER_OSPEEDR9_Msk -#define GPIO_OSPEEDER_OSPEEDR9_0 (0x1UL << GPIO_OSPEEDER_OSPEEDR9_Pos) /*!< 0x00040000 */ -#define GPIO_OSPEEDER_OSPEEDR9_1 (0x2UL << GPIO_OSPEEDER_OSPEEDR9_Pos) /*!< 0x00080000 */ -#define GPIO_OSPEEDER_OSPEEDR10_Pos (20U) -#define GPIO_OSPEEDER_OSPEEDR10_Msk (0x3UL << GPIO_OSPEEDER_OSPEEDR10_Pos) /*!< 0x00300000 */ -#define GPIO_OSPEEDER_OSPEEDR10 GPIO_OSPEEDER_OSPEEDR10_Msk -#define GPIO_OSPEEDER_OSPEEDR10_0 (0x1UL << GPIO_OSPEEDER_OSPEEDR10_Pos) /*!< 0x00100000 */ -#define GPIO_OSPEEDER_OSPEEDR10_1 (0x2UL << GPIO_OSPEEDER_OSPEEDR10_Pos) /*!< 0x00200000 */ -#define GPIO_OSPEEDER_OSPEEDR11_Pos (22U) -#define GPIO_OSPEEDER_OSPEEDR11_Msk (0x3UL << GPIO_OSPEEDER_OSPEEDR11_Pos) /*!< 0x00C00000 */ -#define GPIO_OSPEEDER_OSPEEDR11 GPIO_OSPEEDER_OSPEEDR11_Msk -#define GPIO_OSPEEDER_OSPEEDR11_0 (0x1UL << GPIO_OSPEEDER_OSPEEDR11_Pos) /*!< 0x00400000 */ -#define GPIO_OSPEEDER_OSPEEDR11_1 (0x2UL << GPIO_OSPEEDER_OSPEEDR11_Pos) /*!< 0x00800000 */ -#define GPIO_OSPEEDER_OSPEEDR12_Pos (24U) -#define GPIO_OSPEEDER_OSPEEDR12_Msk (0x3UL << GPIO_OSPEEDER_OSPEEDR12_Pos) /*!< 0x03000000 */ -#define GPIO_OSPEEDER_OSPEEDR12 GPIO_OSPEEDER_OSPEEDR12_Msk -#define GPIO_OSPEEDER_OSPEEDR12_0 (0x1UL << GPIO_OSPEEDER_OSPEEDR12_Pos) /*!< 0x01000000 */ -#define GPIO_OSPEEDER_OSPEEDR12_1 (0x2UL << GPIO_OSPEEDER_OSPEEDR12_Pos) /*!< 0x02000000 */ -#define GPIO_OSPEEDER_OSPEEDR13_Pos (26U) -#define GPIO_OSPEEDER_OSPEEDR13_Msk (0x3UL << GPIO_OSPEEDER_OSPEEDR13_Pos) /*!< 0x0C000000 */ -#define GPIO_OSPEEDER_OSPEEDR13 GPIO_OSPEEDER_OSPEEDR13_Msk -#define GPIO_OSPEEDER_OSPEEDR13_0 (0x1UL << GPIO_OSPEEDER_OSPEEDR13_Pos) /*!< 0x04000000 */ -#define GPIO_OSPEEDER_OSPEEDR13_1 (0x2UL << GPIO_OSPEEDER_OSPEEDR13_Pos) /*!< 0x08000000 */ -#define GPIO_OSPEEDER_OSPEEDR14_Pos (28U) -#define GPIO_OSPEEDER_OSPEEDR14_Msk (0x3UL << GPIO_OSPEEDER_OSPEEDR14_Pos) /*!< 0x30000000 */ -#define GPIO_OSPEEDER_OSPEEDR14 GPIO_OSPEEDER_OSPEEDR14_Msk -#define GPIO_OSPEEDER_OSPEEDR14_0 (0x1UL << GPIO_OSPEEDER_OSPEEDR14_Pos) /*!< 0x10000000 */ -#define GPIO_OSPEEDER_OSPEEDR14_1 (0x2UL << GPIO_OSPEEDER_OSPEEDR14_Pos) /*!< 0x20000000 */ -#define GPIO_OSPEEDER_OSPEEDR15_Pos (30U) -#define GPIO_OSPEEDER_OSPEEDR15_Msk (0x3UL << GPIO_OSPEEDER_OSPEEDR15_Pos) /*!< 0xC0000000 */ -#define GPIO_OSPEEDER_OSPEEDR15 GPIO_OSPEEDER_OSPEEDR15_Msk -#define GPIO_OSPEEDER_OSPEEDR15_0 (0x1UL << GPIO_OSPEEDER_OSPEEDR15_Pos) /*!< 0x40000000 */ -#define GPIO_OSPEEDER_OSPEEDR15_1 (0x2UL << GPIO_OSPEEDER_OSPEEDR15_Pos) /*!< 0x80000000 */ +#define GPIO_OSPEEDR_OSPEEDR0_Pos (0U) +#define GPIO_OSPEEDR_OSPEEDR0_Msk (0x3UL << GPIO_OSPEEDR_OSPEEDR0_Pos) /*!< 0x00000003 */ +#define GPIO_OSPEEDR_OSPEEDR0 GPIO_OSPEEDR_OSPEEDR0_Msk +#define GPIO_OSPEEDR_OSPEEDR0_0 (0x1UL << GPIO_OSPEEDR_OSPEEDR0_Pos) /*!< 0x00000001 */ +#define GPIO_OSPEEDR_OSPEEDR0_1 (0x2UL << GPIO_OSPEEDR_OSPEEDR0_Pos) /*!< 0x00000002 */ +#define GPIO_OSPEEDR_OSPEEDR1_Pos (2U) +#define GPIO_OSPEEDR_OSPEEDR1_Msk (0x3UL << GPIO_OSPEEDR_OSPEEDR1_Pos) /*!< 0x0000000C */ +#define GPIO_OSPEEDR_OSPEEDR1 GPIO_OSPEEDR_OSPEEDR1_Msk +#define GPIO_OSPEEDR_OSPEEDR1_0 (0x1UL << GPIO_OSPEEDR_OSPEEDR1_Pos) /*!< 0x00000004 */ +#define GPIO_OSPEEDR_OSPEEDR1_1 (0x2UL << GPIO_OSPEEDR_OSPEEDR1_Pos) /*!< 0x00000008 */ +#define GPIO_OSPEEDR_OSPEEDR2_Pos (4U) +#define GPIO_OSPEEDR_OSPEEDR2_Msk (0x3UL << GPIO_OSPEEDR_OSPEEDR2_Pos) /*!< 0x00000030 */ +#define GPIO_OSPEEDR_OSPEEDR2 GPIO_OSPEEDR_OSPEEDR2_Msk +#define GPIO_OSPEEDR_OSPEEDR2_0 (0x1UL << GPIO_OSPEEDR_OSPEEDR2_Pos) /*!< 0x00000010 */ +#define GPIO_OSPEEDR_OSPEEDR2_1 (0x2UL << GPIO_OSPEEDR_OSPEEDR2_Pos) /*!< 0x00000020 */ +#define GPIO_OSPEEDR_OSPEEDR3_Pos (6U) +#define GPIO_OSPEEDR_OSPEEDR3_Msk (0x3UL << GPIO_OSPEEDR_OSPEEDR3_Pos) /*!< 0x000000C0 */ +#define GPIO_OSPEEDR_OSPEEDR3 GPIO_OSPEEDR_OSPEEDR3_Msk +#define GPIO_OSPEEDR_OSPEEDR3_0 (0x1UL << GPIO_OSPEEDR_OSPEEDR3_Pos) /*!< 0x00000040 */ +#define GPIO_OSPEEDR_OSPEEDR3_1 (0x2UL << GPIO_OSPEEDR_OSPEEDR3_Pos) /*!< 0x00000080 */ +#define GPIO_OSPEEDR_OSPEEDR4_Pos (8U) +#define GPIO_OSPEEDR_OSPEEDR4_Msk (0x3UL << GPIO_OSPEEDR_OSPEEDR4_Pos) /*!< 0x00000300 */ +#define GPIO_OSPEEDR_OSPEEDR4 GPIO_OSPEEDR_OSPEEDR4_Msk +#define GPIO_OSPEEDR_OSPEEDR4_0 (0x1UL << GPIO_OSPEEDR_OSPEEDR4_Pos) /*!< 0x00000100 */ +#define GPIO_OSPEEDR_OSPEEDR4_1 (0x2UL << GPIO_OSPEEDR_OSPEEDR4_Pos) /*!< 0x00000200 */ +#define GPIO_OSPEEDR_OSPEEDR5_Pos (10U) +#define GPIO_OSPEEDR_OSPEEDR5_Msk (0x3UL << GPIO_OSPEEDR_OSPEEDR5_Pos) /*!< 0x00000C00 */ +#define GPIO_OSPEEDR_OSPEEDR5 GPIO_OSPEEDR_OSPEEDR5_Msk +#define GPIO_OSPEEDR_OSPEEDR5_0 (0x1UL << GPIO_OSPEEDR_OSPEEDR5_Pos) /*!< 0x00000400 */ +#define GPIO_OSPEEDR_OSPEEDR5_1 (0x2UL << GPIO_OSPEEDR_OSPEEDR5_Pos) /*!< 0x00000800 */ +#define GPIO_OSPEEDR_OSPEEDR6_Pos (12U) +#define GPIO_OSPEEDR_OSPEEDR6_Msk (0x3UL << GPIO_OSPEEDR_OSPEEDR6_Pos) /*!< 0x00003000 */ +#define GPIO_OSPEEDR_OSPEEDR6 GPIO_OSPEEDR_OSPEEDR6_Msk +#define GPIO_OSPEEDR_OSPEEDR6_0 (0x1UL << GPIO_OSPEEDR_OSPEEDR6_Pos) /*!< 0x00001000 */ +#define GPIO_OSPEEDR_OSPEEDR6_1 (0x2UL << GPIO_OSPEEDR_OSPEEDR6_Pos) /*!< 0x00002000 */ +#define GPIO_OSPEEDR_OSPEEDR7_Pos (14U) +#define GPIO_OSPEEDR_OSPEEDR7_Msk (0x3UL << GPIO_OSPEEDR_OSPEEDR7_Pos) /*!< 0x0000C000 */ +#define GPIO_OSPEEDR_OSPEEDR7 GPIO_OSPEEDR_OSPEEDR7_Msk +#define GPIO_OSPEEDR_OSPEEDR7_0 (0x1UL << GPIO_OSPEEDR_OSPEEDR7_Pos) /*!< 0x00004000 */ +#define GPIO_OSPEEDR_OSPEEDR7_1 (0x2UL << GPIO_OSPEEDR_OSPEEDR7_Pos) /*!< 0x00008000 */ +#define GPIO_OSPEEDR_OSPEEDR8_Pos (16U) +#define GPIO_OSPEEDR_OSPEEDR8_Msk (0x3UL << GPIO_OSPEEDR_OSPEEDR8_Pos) /*!< 0x00030000 */ +#define GPIO_OSPEEDR_OSPEEDR8 GPIO_OSPEEDR_OSPEEDR8_Msk +#define GPIO_OSPEEDR_OSPEEDR8_0 (0x1UL << GPIO_OSPEEDR_OSPEEDR8_Pos) /*!< 0x00010000 */ +#define GPIO_OSPEEDR_OSPEEDR8_1 (0x2UL << GPIO_OSPEEDR_OSPEEDR8_Pos) /*!< 0x00020000 */ +#define GPIO_OSPEEDR_OSPEEDR9_Pos (18U) +#define GPIO_OSPEEDR_OSPEEDR9_Msk (0x3UL << GPIO_OSPEEDR_OSPEEDR9_Pos) /*!< 0x000C0000 */ +#define GPIO_OSPEEDR_OSPEEDR9 GPIO_OSPEEDR_OSPEEDR9_Msk +#define GPIO_OSPEEDR_OSPEEDR9_0 (0x1UL << GPIO_OSPEEDR_OSPEEDR9_Pos) /*!< 0x00040000 */ +#define GPIO_OSPEEDR_OSPEEDR9_1 (0x2UL << GPIO_OSPEEDR_OSPEEDR9_Pos) /*!< 0x00080000 */ +#define GPIO_OSPEEDR_OSPEEDR10_Pos (20U) +#define GPIO_OSPEEDR_OSPEEDR10_Msk (0x3UL << GPIO_OSPEEDR_OSPEEDR10_Pos) /*!< 0x00300000 */ +#define GPIO_OSPEEDR_OSPEEDR10 GPIO_OSPEEDR_OSPEEDR10_Msk +#define GPIO_OSPEEDR_OSPEEDR10_0 (0x1UL << GPIO_OSPEEDR_OSPEEDR10_Pos) /*!< 0x00100000 */ +#define GPIO_OSPEEDR_OSPEEDR10_1 (0x2UL << GPIO_OSPEEDR_OSPEEDR10_Pos) /*!< 0x00200000 */ +#define GPIO_OSPEEDR_OSPEEDR11_Pos (22U) +#define GPIO_OSPEEDR_OSPEEDR11_Msk (0x3UL << GPIO_OSPEEDR_OSPEEDR11_Pos) /*!< 0x00C00000 */ +#define GPIO_OSPEEDR_OSPEEDR11 GPIO_OSPEEDR_OSPEEDR11_Msk +#define GPIO_OSPEEDR_OSPEEDR11_0 (0x1UL << GPIO_OSPEEDR_OSPEEDR11_Pos) /*!< 0x00400000 */ +#define GPIO_OSPEEDR_OSPEEDR11_1 (0x2UL << GPIO_OSPEEDR_OSPEEDR11_Pos) /*!< 0x00800000 */ +#define GPIO_OSPEEDR_OSPEEDR12_Pos (24U) +#define GPIO_OSPEEDR_OSPEEDR12_Msk (0x3UL << GPIO_OSPEEDR_OSPEEDR12_Pos) /*!< 0x03000000 */ +#define GPIO_OSPEEDR_OSPEEDR12 GPIO_OSPEEDR_OSPEEDR12_Msk +#define GPIO_OSPEEDR_OSPEEDR12_0 (0x1UL << GPIO_OSPEEDR_OSPEEDR12_Pos) /*!< 0x01000000 */ +#define GPIO_OSPEEDR_OSPEEDR12_1 (0x2UL << GPIO_OSPEEDR_OSPEEDR12_Pos) /*!< 0x02000000 */ +#define GPIO_OSPEEDR_OSPEEDR13_Pos (26U) +#define GPIO_OSPEEDR_OSPEEDR13_Msk (0x3UL << GPIO_OSPEEDR_OSPEEDR13_Pos) /*!< 0x0C000000 */ +#define GPIO_OSPEEDR_OSPEEDR13 GPIO_OSPEEDR_OSPEEDR13_Msk +#define GPIO_OSPEEDR_OSPEEDR13_0 (0x1UL << GPIO_OSPEEDR_OSPEEDR13_Pos) /*!< 0x04000000 */ +#define GPIO_OSPEEDR_OSPEEDR13_1 (0x2UL << GPIO_OSPEEDR_OSPEEDR13_Pos) /*!< 0x08000000 */ +#define GPIO_OSPEEDR_OSPEEDR14_Pos (28U) +#define GPIO_OSPEEDR_OSPEEDR14_Msk (0x3UL << GPIO_OSPEEDR_OSPEEDR14_Pos) /*!< 0x30000000 */ +#define GPIO_OSPEEDR_OSPEEDR14 GPIO_OSPEEDR_OSPEEDR14_Msk +#define GPIO_OSPEEDR_OSPEEDR14_0 (0x1UL << GPIO_OSPEEDR_OSPEEDR14_Pos) /*!< 0x10000000 */ +#define GPIO_OSPEEDR_OSPEEDR14_1 (0x2UL << GPIO_OSPEEDR_OSPEEDR14_Pos) /*!< 0x20000000 */ +#define GPIO_OSPEEDR_OSPEEDR15_Pos (30U) +#define GPIO_OSPEEDR_OSPEEDR15_Msk (0x3UL << GPIO_OSPEEDR_OSPEEDR15_Pos) /*!< 0xC0000000 */ +#define GPIO_OSPEEDR_OSPEEDR15 GPIO_OSPEEDR_OSPEEDR15_Msk +#define GPIO_OSPEEDR_OSPEEDR15_0 (0x1UL << GPIO_OSPEEDR_OSPEEDR15_Pos) /*!< 0x40000000 */ +#define GPIO_OSPEEDR_OSPEEDR15_1 (0x2UL << GPIO_OSPEEDR_OSPEEDR15_Pos) /*!< 0x80000000 */ + +/* Legacy defines */ +#define GPIO_OSPEEDER_OSPEEDR0_Pos GPIO_OSPEEDR_OSPEEDR0_Pos +#define GPIO_OSPEEDER_OSPEEDR0_Msk GPIO_OSPEEDR_OSPEEDR0_Msk +#define GPIO_OSPEEDER_OSPEEDR0 GPIO_OSPEEDR_OSPEEDR0 +#define GPIO_OSPEEDER_OSPEEDR0_0 GPIO_OSPEEDR_OSPEEDR0_0 +#define GPIO_OSPEEDER_OSPEEDR0_1 GPIO_OSPEEDR_OSPEEDR0_1 +#define GPIO_OSPEEDER_OSPEEDR1_Pos GPIO_OSPEEDR_OSPEEDR1_Pos +#define GPIO_OSPEEDER_OSPEEDR1_Msk GPIO_OSPEEDR_OSPEEDR1_Msk +#define GPIO_OSPEEDER_OSPEEDR1 GPIO_OSPEEDR_OSPEEDR1 +#define GPIO_OSPEEDER_OSPEEDR1_0 GPIO_OSPEEDR_OSPEEDR1_0 +#define GPIO_OSPEEDER_OSPEEDR1_1 GPIO_OSPEEDR_OSPEEDR1_1 +#define GPIO_OSPEEDER_OSPEEDR2_Pos GPIO_OSPEEDR_OSPEEDR2_Pos +#define GPIO_OSPEEDER_OSPEEDR2_Msk GPIO_OSPEEDR_OSPEEDR2_Msk +#define GPIO_OSPEEDER_OSPEEDR2 GPIO_OSPEEDR_OSPEEDR2 +#define GPIO_OSPEEDER_OSPEEDR2_0 GPIO_OSPEEDR_OSPEEDR2_0 +#define GPIO_OSPEEDER_OSPEEDR2_1 GPIO_OSPEEDR_OSPEEDR2_1 +#define GPIO_OSPEEDER_OSPEEDR3_Pos GPIO_OSPEEDR_OSPEEDR3_Pos +#define GPIO_OSPEEDER_OSPEEDR3_Msk GPIO_OSPEEDR_OSPEEDR3_Msk +#define GPIO_OSPEEDER_OSPEEDR3 GPIO_OSPEEDR_OSPEEDR3 +#define GPIO_OSPEEDER_OSPEEDR3_0 GPIO_OSPEEDR_OSPEEDR3_0 +#define GPIO_OSPEEDER_OSPEEDR3_1 GPIO_OSPEEDR_OSPEEDR3_1 +#define GPIO_OSPEEDER_OSPEEDR4_Pos GPIO_OSPEEDR_OSPEEDR4_Pos +#define GPIO_OSPEEDER_OSPEEDR4_Msk GPIO_OSPEEDR_OSPEEDR4_Msk +#define GPIO_OSPEEDER_OSPEEDR4 GPIO_OSPEEDR_OSPEEDR4 +#define GPIO_OSPEEDER_OSPEEDR4_0 GPIO_OSPEEDR_OSPEEDR4_0 +#define GPIO_OSPEEDER_OSPEEDR4_1 GPIO_OSPEEDR_OSPEEDR4_1 +#define GPIO_OSPEEDER_OSPEEDR5_Pos GPIO_OSPEEDR_OSPEEDR5_Pos +#define GPIO_OSPEEDER_OSPEEDR5_Msk GPIO_OSPEEDR_OSPEEDR5_Msk +#define GPIO_OSPEEDER_OSPEEDR5 GPIO_OSPEEDR_OSPEEDR5 +#define GPIO_OSPEEDER_OSPEEDR5_0 GPIO_OSPEEDR_OSPEEDR5_0 +#define GPIO_OSPEEDER_OSPEEDR5_1 GPIO_OSPEEDR_OSPEEDR5_1 +#define GPIO_OSPEEDER_OSPEEDR6_Pos GPIO_OSPEEDR_OSPEEDR6_Pos +#define GPIO_OSPEEDER_OSPEEDR6_Msk GPIO_OSPEEDR_OSPEEDR6_Msk +#define GPIO_OSPEEDER_OSPEEDR6 GPIO_OSPEEDR_OSPEEDR6 +#define GPIO_OSPEEDER_OSPEEDR6_0 GPIO_OSPEEDR_OSPEEDR6_0 +#define GPIO_OSPEEDER_OSPEEDR6_1 GPIO_OSPEEDR_OSPEEDR6_1 +#define GPIO_OSPEEDER_OSPEEDR7_Pos GPIO_OSPEEDR_OSPEEDR7_Pos +#define GPIO_OSPEEDER_OSPEEDR7_Msk GPIO_OSPEEDR_OSPEEDR7_Msk +#define GPIO_OSPEEDER_OSPEEDR7 GPIO_OSPEEDR_OSPEEDR7 +#define GPIO_OSPEEDER_OSPEEDR7_0 GPIO_OSPEEDR_OSPEEDR7_0 +#define GPIO_OSPEEDER_OSPEEDR7_1 GPIO_OSPEEDR_OSPEEDR7_1 +#define GPIO_OSPEEDER_OSPEEDR8_Pos GPIO_OSPEEDR_OSPEEDR8_Pos +#define GPIO_OSPEEDER_OSPEEDR8_Msk GPIO_OSPEEDR_OSPEEDR8_Msk +#define GPIO_OSPEEDER_OSPEEDR8 GPIO_OSPEEDR_OSPEEDR8 +#define GPIO_OSPEEDER_OSPEEDR8_0 GPIO_OSPEEDR_OSPEEDR8_0 +#define GPIO_OSPEEDER_OSPEEDR8_1 GPIO_OSPEEDR_OSPEEDR8_1 +#define GPIO_OSPEEDER_OSPEEDR9_Pos GPIO_OSPEEDR_OSPEEDR9_Pos +#define GPIO_OSPEEDER_OSPEEDR9_Msk GPIO_OSPEEDR_OSPEEDR9_Msk +#define GPIO_OSPEEDER_OSPEEDR9 GPIO_OSPEEDR_OSPEEDR9 +#define GPIO_OSPEEDER_OSPEEDR9_0 GPIO_OSPEEDR_OSPEEDR9_0 +#define GPIO_OSPEEDER_OSPEEDR9_1 GPIO_OSPEEDR_OSPEEDR9_1 +#define GPIO_OSPEEDER_OSPEEDR10_Pos GPIO_OSPEEDR_OSPEEDR10_Pos +#define GPIO_OSPEEDER_OSPEEDR10_Msk GPIO_OSPEEDR_OSPEEDR10_Msk +#define GPIO_OSPEEDER_OSPEEDR10 GPIO_OSPEEDR_OSPEEDR10 +#define GPIO_OSPEEDER_OSPEEDR10_0 GPIO_OSPEEDR_OSPEEDR10_0 +#define GPIO_OSPEEDER_OSPEEDR10_1 GPIO_OSPEEDR_OSPEEDR10_1 +#define GPIO_OSPEEDER_OSPEEDR11_Pos GPIO_OSPEEDR_OSPEEDR11_Pos +#define GPIO_OSPEEDER_OSPEEDR11_Msk GPIO_OSPEEDR_OSPEEDR11_Msk +#define GPIO_OSPEEDER_OSPEEDR11 GPIO_OSPEEDR_OSPEEDR11 +#define GPIO_OSPEEDER_OSPEEDR11_0 GPIO_OSPEEDR_OSPEEDR11_0 +#define GPIO_OSPEEDER_OSPEEDR11_1 GPIO_OSPEEDR_OSPEEDR11_1 +#define GPIO_OSPEEDER_OSPEEDR12_Pos GPIO_OSPEEDR_OSPEEDR12_Pos +#define GPIO_OSPEEDER_OSPEEDR12_Msk GPIO_OSPEEDR_OSPEEDR12_Msk +#define GPIO_OSPEEDER_OSPEEDR12 GPIO_OSPEEDR_OSPEEDR12 +#define GPIO_OSPEEDER_OSPEEDR12_0 GPIO_OSPEEDR_OSPEEDR12_0 +#define GPIO_OSPEEDER_OSPEEDR12_1 GPIO_OSPEEDR_OSPEEDR12_1 +#define GPIO_OSPEEDER_OSPEEDR13_Pos GPIO_OSPEEDR_OSPEEDR13_Pos +#define GPIO_OSPEEDER_OSPEEDR13_Msk GPIO_OSPEEDR_OSPEEDR13_Msk +#define GPIO_OSPEEDER_OSPEEDR13 GPIO_OSPEEDR_OSPEEDR13 +#define GPIO_OSPEEDER_OSPEEDR13_0 GPIO_OSPEEDR_OSPEEDR13_0 +#define GPIO_OSPEEDER_OSPEEDR13_1 GPIO_OSPEEDR_OSPEEDR13_1 +#define GPIO_OSPEEDER_OSPEEDR14_Pos GPIO_OSPEEDR_OSPEEDR14_Pos +#define GPIO_OSPEEDER_OSPEEDR14_Msk GPIO_OSPEEDR_OSPEEDR14_Msk +#define GPIO_OSPEEDER_OSPEEDR14 GPIO_OSPEEDR_OSPEEDR14 +#define GPIO_OSPEEDER_OSPEEDR14_0 GPIO_OSPEEDR_OSPEEDR14_0 +#define GPIO_OSPEEDER_OSPEEDR14_1 GPIO_OSPEEDR_OSPEEDR14_1 +#define GPIO_OSPEEDER_OSPEEDR15_Pos GPIO_OSPEEDR_OSPEEDR15_Pos +#define GPIO_OSPEEDER_OSPEEDR15_Msk GPIO_OSPEEDR_OSPEEDR15_Msk +#define GPIO_OSPEEDER_OSPEEDR15 GPIO_OSPEEDR_OSPEEDR15 +#define GPIO_OSPEEDER_OSPEEDR15_0 GPIO_OSPEEDR_OSPEEDR15_0 +#define GPIO_OSPEEDER_OSPEEDR15_1 GPIO_OSPEEDR_OSPEEDR15_1 /******************* Bit definition for GPIO_PUPDR register ******************/ #define GPIO_PUPDR_PUPDR0_Pos (0U) @@ -7047,7 +7129,7 @@ typedef struct /******************* Bit definition for TIM_CCR5 register *******************/ #define TIM_CCR5_CCR5_Pos (0U) -#define TIM_CCR5_CCR5_Msk (0xFFFFFFFFUL << TIM_CCR5_CCR5_Pos) /*!< 0xFFFFFFFF */ +#define TIM_CCR5_CCR5_Msk (0xFFFFUL << TIM_CCR5_CCR5_Pos) /*!< 0xFFFF */ #define TIM_CCR5_CCR5 TIM_CCR5_CCR5_Msk /*!Release Notes for STM32F3xx C

                                                  Update History

                                                  - +

                                                  Main Changes

                                                  • General update
                                                      +
                                                    • Align GPIO OSPEEDR defines with naming used in reference manual.
                                                      • +
                                                    • Rename GPIO_OSPEEDER_OSPEEDRx to GPIO_OSPEEDR_OSPEEDRx.
                                                      • +
                                                    • Initialize VTOR in SystemInit() by default to keep SysTick working.
                                                      • +
                                                    • Allow redefinition of the macro VECT_TAB_OFFSET externally from the IDE, makefile, or command line.
                                                      • +
                                                    • +
                                                  +
                                                  +
                                                  +
                                                  + +
                                                  +

                                                  Main Changes

                                                  +
                                                    +
                                                  • General update +
                                                    • Remove duplicated definition of ADC12_CSR_ADRDY_OVR_SLV bit and add definition of ADC34_CSR_ADRDY_OVR_SLV bit
                                                    • Align the CEC_RXDR register bit definition with reference manual
                                                    • @@ -48,7 +63,7 @@

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                                                                        Main Changes

                                                                        • Remove support of Atollic TrueSTUDIO STM32 (TrueSTUDIO) toolchain.
                                                                        • FLASH updates @@ -183,7 +198,7 @@

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                                                                          Main Changes

                                                                          • COMP updates
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                                                                                      Main Changes

                                                                                      • Add the support of the STM32F302xE and the STM32F398xx devices.
                                                                                      • STM32F303xE update @@ -397,7 +412,7 @@

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                                                                                        Main Changes

                                                                                        • Add CMSIS files for STM32F303xE products
                                                                                        @@ -406,7 +421,7 @@

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                                                                                        • General
                                                                                            @@ -463,7 +478,7 @@

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                                                                                            -

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                                                                                            Main Changes

                                                                                            • Major update based on STM32Cube specification: new CMSIS device files release dedicated to STM32F301x6/x8, STM32F302x6/x8, STM32F302xB/xC, STM32F303x6/x8, STM32F373xB/xC, STM32F334x4/x6/x8, STM32F318xx, STM32F328xx, STM32F358xx and STM32F378xx devices .
                                                                                            • This version has to be used for STM32CubeF3 based development although files can be used independently too.
                                                                                              • @@ -473,7 +488,7 @@

                                                                                              Main Changes

                                                                                              -

                                                                                              Main Changes

                                                                                              +

                                                                                              Main Changes

                                                                                              • Add new startup files for the STM32F302x8 and STM32F334x8 devices for TrueSTUDIO toolchain.
                                                                                              • Update startup files for EWARM toolchain to cope with compiler enhancement of the V7.10 version.
                                                                                                • @@ -483,7 +498,7 @@

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                                                                                                Main Changes

                                                                                                +

                                                                                                Main Changes

                                                                                                • Add the support of the STM32F302x8 and the STM32F334x8 devices.
                                                                                                • Update devices names definition to be in line with the new new STM32F30x family devices names. @@ -516,7 +531,7 @@

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                                                                                                  • First official release for STM32F30x devices (Standard Library)
                                                                                                  diff --git a/system/Drivers/CMSIS/Device/ST/STM32F3xx/Release_Notes.md b/system/Drivers/CMSIS/Device/ST/STM32F3xx/Release_Notes.md new file mode 100644 index 0000000000..1f58223fd9 --- /dev/null +++ b/system/Drivers/CMSIS/Device/ST/STM32F3xx/Release_Notes.md @@ -0,0 +1,352 @@ + + +# **Release Notes for STM32F3xx CMSIS** +Copyright © 2016 STMicroelectronics\ + +[![ST logo](./_htmresc/st_logo.png)](https://www.st.com) + + + +# __Update History__ + +
                                                                                                  + +## Main Changes + +- General update + - Align GPIO OSPEEDR defines with naming used in reference manual. + - Rename GPIO_OSPEEDER_OSPEEDRx to GPIO_OSPEEDR_OSPEEDRx. + - Initialize VTOR in SystemInit() by default to keep SysTick working. + - Allow redefinition of the macro VECT_TAB_OFFSET externally from the IDE, makefile, or command line. + +
                                                                                                  + + +
                                                                                                  + +## Main Changes + +- General update + - Remove duplicated definition of ADC12_CSR_ADRDY_OVR_SLV bit and add definition of ADC34_CSR_ADRDY_OVR_SLV bit + - Align the CEC_RXDR register bit definition with reference manual + +
                                                                                                  + + +
                                                                                                  + +## Main Changes + +- General update + - General updates to fix known defects and implementation enhancements + - All source files: update disclaimer to add reference to the new license agreement. +- GCC start-up files updates + - Alignment with IAR/MDK-ARM startup files: Update to call SystemInit first in startup/Reset_Handler() +- STM32F301x8/STM32F302xC/STM32F303x8/STM32F318xx/STM32F328xx/STM32F358xx updates + - TIM16_OR_TI1_RMP wrong defined value + +
                                                                                                  + + +
                                                                                                  + +## Main Changes + +- General update + - Added new atomic register access macros in stm32f3xx.h file. + - Add LSI maximum startup time datasheet value: LSI_STARTUP_TIME. +- STM32F334x8 updates + - HRTIM: Add missing defines to reset all Slave Timer X +- STM32F373xC/ STM32F378xx updates + - Start-up files update to call COMP_IRQHandler instead of COMP1_2_IRQHandler + +
                                                                                                  + + +
                                                                                                  + +## Main Changes + +- General update + - system_stm32f3xx.c + - Protect Vector table modification following SRAM or FLASH preprocessor directive by a generic preprocessor directive : USER_VECT_TAB_ADDRESS + - Add License.md and Readme.md files required for GitHub publication + - Improve GCC startup files robustness. + +
                                                                                                  + + +
                                                                                                  + +## Main Changes + +- General update + - Use 'UL' unsigned long postfix for _Msk definitions and memory/peripheral base addresses for MISRA C 2012 Compliance + - SystemInit(): update to don't reset RCC registers to its reset values. +- STM32F334x8 update + - HRTIM updates: + - Fix too many defines for HRTIM Delayed Protection Flag Clear. + - Fix wrong definition of HRTIM1_TIMx constants + - Align HRTIM bits definition with reference manual +- Update OB_TypeDef structure to be aligned with reference manuals. +- Rename macro definition IS_**USB**_ALL_INSTANCE to IS_**PCD**_ALL_INSTANCE. +- Align ADC_DIFSEL_DIFSEL_Pos definition with reference manual. + +
                                                                                                  + + +
                                                                                                  + +## Main Changes +- General update + - Align ErrorStatus typedef to common error handling ( stm32f3xx.h ) +- TIM updates + - Add IS_TIM_SYNCHRO_INSTANCE macro for STM32F37xxx devices + - Add IS_TIM_HALL_SENSOR_INTERFACE_INSTANCE macro definition +
                                                                                                  + + +
                                                                                                  + +## Main Changes +- Remove support of Atollic TrueSTUDIO STM32 (TrueSTUDIO) toolchain. +- FLASH updates + - Clean-up OB_WRP2_nWRP2 && OB_WRP2_nWRP3 (Option Byte) definitions according to family diversity. +- RTC updates + - Renamed RTC_CR_BCK to RTC_CR_BKP in RTC_CR register in order to be aligned with STM32F3xx Reference Manual. +- SYSCFG updates + - Removed SYSCFG_CFGR3_DAC1_TRG3, SYSCFG_CFGR3_DAC1_TRG5, SYSCFG_CFGR3_TRIGGER definitions for STM32F328xx devices. +- SPI updates + - Removed SPI_SR_CHSIDE, SPI_SR_UDR definitions for STM32F303x8, STM32F328xx, STM32F334x8 devices. +- EXTI updates + - Add EXTI_EMR2_EM definition. +- COMP updates + - Clean-up COMPx_CSR definitions according to family diversity. +
                                                                                                  + + +
                                                                                                  + +## Main Changes +- COMP updates + - Corrected COMP inputs definition for STM32F3xxxx devices +- ADC updates + - Corrected SDADC_CONF1R_COMMON1_1 bit definition for STM32F373xC and STM32F378xx devices +- TIM updates + - Added macro IS_TIM_ADVANCED_INSTANCE() to identify advanced timer instances + - Remove TIM_CR2_OIS2N, TIM_CR2_OIS3, TIM_CR2_OIS3N and TIM_CR2_OIS4 definitions for STM32F373xC and STM32F378xx devices (alignment with STM32F3xx Reference Manual) +- RCC updates + - Renamed RCC_CFGR register fields defines for STM32F378xx and STM32F373xC devices to be aligned with STM32F3xx Reference Manual : SDADCPRE ==> SDPRE +- PWR updates + - Renamed PWR_CR register fields defines for STM32F378xx and STM32F373xC devices to be aligned with STM32F3xx Reference Manual : SDADCxEN ==> ENSDx +- USB updates + - compliance with MISRA C 2004 rules: + - MISRA C 2004 rule 10.6 ('U' suffix applied to all constants of 'unsigned' type). + - MISRA C 2004 rule 12.7 (bitwise operations not performed on signed integer types). +- EXTI updates + - Depends on devices, removed EXTI_IMR_MRxx, EXTI_EMR_MRxx, EXTI_RTSR_TRxx, EXTI_FTSR_TRxx, EXTI_SWIER_SWIERxx, EXTI_PR_PRxx, EXTI_IMR2_MRxx, EXTI__EMR2_MRxx, EXTI_RTSR2_TRxx, EXTI_FTSR2_TRxx, EXTI_SWIER2_SWIERxx, EXTI_PR2_PRxx definitions to be aligned with STM32F3xx +
                                                                                                  + + +
                                                                                                  + +## Main Changes +- General updates + - Updated CMSIS Device compliance with MISRA C 2004 rules: + - MISRA C 2004 rule 5.1 (bitwise operators ~ and <<). + - MISRA C 2004 rule 10.6 ('U' suffix applied to all constants of 'unsigned' type). + - Added FLASHSIZE_BASE and UID_BASE defines. + - Added HardFault_IRQn definition (Cortex-M4 Hard Fault Interrupt) + - Updated “Liberty” License with the new license “Ultimate Liberty”. + - Updated system_stm32f3xx.h/.c files: + - Added AHBPrescTable definition as external. + - Added APBPrescTable definition as external. +- ADC updates + - Updated/added ADCxy_COMMON definitions for alignment between all STM32 series. + - Aligned bit definitions and descriptions for ADC registers between all STM32 series. +- COMP updates + - Updated/added COMPxy_COMMON definitions for alignment between all STM32 series. + - Created literal COMP_CSR_COMPxSW1 (equivalent of COMP1_CSR_COMP1SW1 and COMP2_CSR_COMP2SW1). + - Removed COMPxxx_CSR_COMPyyyNONINSEL bit definitions for devices not supporting COMP3 or COMP5 instances + - and added COMP2_CSR_COMP2NONINSEL bit definition for STM32F303xE, STM32F398xx devices. + - Added COMP6_CSR_COMP6NONINSEL bit definition for for STM32F303xE and STM32F398xx devices. +- DAC updates + - Aligned DAC_CR_BOFFx bit definition in DAC_CR register to be declared on the 2 DAC channels. +- EXTI updates + - Aligned EXTI bits definition with others STM32 series. +- FMC updates + - Aligned FMC_BWTRx register bit definitions. +- I2C updates + - Added IS_I2S_EXT_ALL_INSTANCE definition for I2S Full-Duplex feature. + - Added IS_I2C_WAKEUP_FROMSTOP_INSTANCE definition for I2C instances supporting Wakeup from Stop mode. +- RCC updates + - Used RCC_CFGR_MCOSEL as reference in all STM32 series. + - Renamed RCC_CFGR_MCOSEL_PLL to RCC_CFGR_MCOSEL_PLL_DIV2 for alignment between all STM32 series. + - Renamed RCC_CFGR3_TIMxSW_HCLK to RCC_CFGR3_TIMxSW_PCLK2 in RCC_CFGR3 register. + - Renamed RCC_CFGR3_HRTIM1SW_HCLK to RCC_CFGR3_HRTIM1SW_PCLK2 in RCC_CFGR3 register. + - Removed RCC_CFGR_PLLNODIV bit definition from STM32F358xx, STM32F303xC and STM32F302xC devices. + - Removed RCC_CSR_VREGRSTF bit definition in RCC_CSR register for STM32F303xC and STM32F303xE devices. + - Removed USART2 and USART3 clock switch in RCC_CFGR3 register not supported by STM32F303x8, STM32F334x8 + - and STM32F328xx devices and for STM32F301x8, STM32F302x8 and STM32F318xx devices. + - Removed RCC_CSR_V18PWRRSTF bit definition in RCC_CSR register not supported by STM32F318xx, STM32F328xx, STM32F358xx, STM32F378xx and STM32F398xx devices. +- RTC updates + - Added missing bits definition for RTC_TAFCR register. + - Removed RTC_ISR_TAMP3F, RTC_TAFCR_TAMP3TRG, RTC_TAFCR_TAMP3E bit definitions in RTC_ISR and RTC_TAFCR registers for STM32F303x8, STM32F334x8, STM32F328xx, STM32F301x8, STM32F302x8 and STM32F318xx devices. +- TIM updates + - Removed TIM_SMCR_OCCS bit definition not supported by STM32F373xC.h and STM32F378xC. +- WWDG updates + - Aligned WWDG registers bits naming between all STM32 series. +
                                                                                                  + + +
                                                                                                  + +## Main Changes +- General updates + - Aligned all peripheral registers structures to uint32_t. + - Added preprocessor compilation switch STM32F3 definition (stm32f3xx.h). + - Added missing STM32F302xD and STM32F303xD mcus in the description list (stm32f3xx.h). + - Removed define for CCM(core coupled memory) data RAM base address in Bit-Band region. + - Removed __IO or __I from constant table declaration (system_stm32f3xx.c). + - Corrected _estack value in project template files. +- RCC updates + - Renamed RCC_CFGR3_USART1SW_PCLK to RCC_CFGR3_USART1SW_PCLKx according to devices. + - Added missing flag for RCC_CSR_VREGRSTF bit. + - Moved RCC_CFGR_MCO flag in correct devices. + - Fixed minor typod in the comments (RCC bit definition). +- RTC updates + - Updated list of RTC backup registers according to devices. +- HRTIM updates + - Corrected Bit definition for HRTIM_MCMP2R/HRTIM_MCMP3R/HRTIM_MCMP4R registers (STM32F334x8 device). +- GPIO updates + - Removed duplicated definition of IS_GPIO_ALL_INSTANCE macro. + - Used IS_GPIO_AF_INSTANCE and IS_GPIO_LOCK_INSTANCE macro definitions. + - Cleaned GPIO bank. Updated GPIO MLOCK capability. + - Added only one define BSRR for BSRRH/BSRRL GPIO port bit set/reset register. + - Added macro to check AF capability of GPIO instance. +- I2C updates + - Renamed I2C_CR1_DFN to I2C_CR1_DNF. + - Added define for OwnAdress 2 mask bit field values (I2C_OAR2_OA2MASK). +- UART updates + - Added IS_UART_DMA_INSTANCE macro to sort UART instances supporting DMA communication. +- FLASH updates + - Renamed FLASH_OBR_WDG_SW to FLASH_OBR_IWDG_SW. + - Added defines for DATA0 & DATA1 available in OBR register. +- USB updates + - Renamed two bitfields: USB_XXX_PMAOVRM to USB_XXX_PMAOVR and USB_CNTR_LP_MODE to USB_CNTR_LPMODE. +- TIM updates + - Corrected Repetition Counter bits definition (TIM_RCR_REP). +- DAC updates + - Corrected/added DAC channel output switch enable bits definition in DAC_CR register. +- FMC updates + - Updated Bits definitions for FMC registers. +- EXTI updates + - Updated Bit definitions for External Interrupt/Event Controller (EXTI). +
                                                                                                  + + +
                                                                                                  + +## Main Changes +- Add the support of the **STM32F302xE** and the **STM32F398xx** devices. +- STM32F303xE update + - Renamed SYSCFG_CFGR3 in SYSCFG_CFGR4 +- STM32F302xC update + - Removed DHR12R2, DHR12L2, DHR8R2 and DOR2 from DAC registers definition + - Removed all DAC channel 2 related constant definitions + - Removed TIM8 related constant definitions + - Removed DAC_CHANNEL_2 from IS_DAC_CHANNEL_INSTANCE() macro +
                                                                                                  + + +
                                                                                                  + +## Main Changes +- Add CMSIS files for STM32F303xE products +
                                                                                                  + + +
                                                                                                  + +## Main Changes +- General + - Add new macro IS_COMP_DAC1SWITCH_INSTANCE to check COMP instance with switch of DAC1 channel1 output to non inverting input +- STM32F301x8 update + - Add new define SYSCFG_CFGR2_LOCKUP_LOCK +- STM32F302x8 update + - Add USB interrupt remapping + - Add new defines USB_HP_IRQn, USB_LP_IRQn and USBWakeUp_RMP_IRQn for USB interrupt remapping + - Add new define SYSCFG_CFGR1_USB_IT_RMP + - Add new define SYSCFG_CFGR2_LOCKUP_LOCK +- STM32F303xC update + - Add new define SYSCFG_CFGR2_LOCKUP_LOCK + - Remove SYSCFG CFGR3 register description +- STM32F373xC update + - Add new define COMP1_2_3_IRQn alias definition on COMP_IRQn +- STM32F318xx update + - Rename COMP4_5_6_IRQn to COMP4_6_IRQn +- STM32F328xx update + - Remove HRTIM1 (cleanup stm32f328xx.h and startup files) +- STM32F358xx update + - Remove USB + - Rename USB_HP_CAN_TX_IRQn and USB_LP_CAN_RX0_IRQn to CAN_TX_IRQn and CAN_RX0_IRQn + - Remove USBWakeUp_IRQn, USB_HP_IRQn, USB_LP_IRQn and USBWakeUp_RMP_IRQn + - Remove define SYSCFG_CFGR1_USB_IT_RMP + - Remove SYSCFG CFGR3 register description +- STM32F378xx update + - Remove USBWakeUp_IRQn, USB_HP_IRQn and USB_LP_IRQn + - Add new define COMP1_2_3_IRQn alias definition on COMP_IRQn +
                                                                                                  + + +
                                                                                                  + +## Main Changes +- Major update based on STM32Cube specification: new CMSIS device files release dedicated to **STM32F301x6/x8, STM32F302x6/x8, STM32F302xB/xC, STM32F303x6/x8, STM32F373xB/xC, STM32F334x4/x6/x8, STM32F318xx, STM32F328xx, STM32F358xx and STM32F378xx devices .** +- **This version has to be used for STM32CubeF3 based development although files can be used independently too.** +
                                                                                                  + + +
                                                                                                  + +## Main Changes +- Add new startup files for the STM32F302x8 and STM32F334x8 devices for TrueSTUDIO toolchain. +- Update startup files for EWARM toolchain to cope with compiler enhancement of the V7.10 version. +
                                                                                                  + + +
                                                                                                  + +## Main Changes +- Add the support of the **STM32F302x8** and the **STM32F334x8** devices. +- Update devices names definition to be in line with the new new STM32F30x family devices names. + - **STM32F30X** replaced by **STM32F303xC.** +- stm32f30x.h + - Upddate to support the new STM32F30x family devices names. + - **STM32F30X** replaced by **STM32F303xC** + - Update IRQn enum to support the STM32F302x8 and STM32F334x8 devices. + - Update HSE_STARTUP_TIMEOUT value. + - Update HSI_STARTUP_TIMEOUT value. + - Add HRTIM peripheral registers and bits definitions. + - Add CFGR3 registers in the SYSCFG_TypeDef structure. + - Update peripheral base addresses to support the added peripherals: DAC2, I2C3, HRTIM. + - Update ADC_SQR4 register bit definition. + - Remove ADC34_CCR_TSEN and ADC34_CCR_VBATEN bits definitions. +- Add new startup files for the STM32F302x8 and STM32F334x8 devices for the supported compilers + - Replace startup_stm32f30x.s by startup_stm32f303xc.s file. + - startup_stm32f30x.s file is maintained for legacy purpose. +
                                                                                                  + + +
                                                                                                  + +## Main Changes +- First official release for **STM32F30x devices** (Standard Library) +
                                                                                                  + + +For complete documentation on STM32 Microcontrollers , +visit: http://www.st.com/stm32 +*This release note uses up to date web standards and, for this reason, should not be opened with Internet +Explorer but preferably with popular browsers such as Google Chrome, Mozilla Firefox, Opera or Microsoft +Edge.* \ No newline at end of file diff --git a/system/Drivers/CMSIS/Device/ST/STM32F3xx/Source/Templates/system_stm32f3xx.c b/system/Drivers/CMSIS/Device/ST/STM32F3xx/Source/Templates/system_stm32f3xx.c index 27d9350284..4b1654f8da 100644 --- a/system/Drivers/CMSIS/Device/ST/STM32F3xx/Source/Templates/system_stm32f3xx.c +++ b/system/Drivers/CMSIS/Device/ST/STM32F3xx/Source/Templates/system_stm32f3xx.c @@ -96,25 +96,27 @@ /* Note: Following vector table addresses must be defined in line with linker configuration. */ /*!< Uncomment the following line if you need to relocate the vector table - anywhere in Flash or Sram, else the vector table is kept at the automatic - remap of boot address selected */ + anywhere in Flash or SRAM, else it will be located at the base address + of the Flash. */ /* #define USER_VECT_TAB_ADDRESS */ #if defined(USER_VECT_TAB_ADDRESS) /*!< Uncomment the following line if you need to relocate your vector Table - in Sram else user remap will be done in Flash. */ + in SRAM else user remap will be done in Flash. */ /* #define VECT_TAB_SRAM */ #if defined(VECT_TAB_SRAM) #define VECT_TAB_BASE_ADDRESS SRAM_BASE /*!< Vector Table base address field. This value must be a multiple of 0x200. */ -#define VECT_TAB_OFFSET 0x00000000U /*!< Vector Table base offset field. - This value must be a multiple of 0x200. */ #else #define VECT_TAB_BASE_ADDRESS FLASH_BASE /*!< Vector Table base address field. This value must be a multiple of 0x200. */ -#define VECT_TAB_OFFSET 0x00000000U /*!< Vector Table base offset field. - This value must be a multiple of 0x200. */ #endif /* VECT_TAB_SRAM */ + +#if !defined(VECT_TAB_OFFSET) +#define VECT_TAB_OFFSET 0x00000000U /*!< Vector Table offset field. + This value must be a multiple of 0x200. */ +#endif /* VECT_TAB_OFFSET */ + #endif /* USER_VECT_TAB_ADDRESS */ /******************************************************************************/ @@ -177,6 +179,8 @@ void SystemInit(void) /* Configure the Vector Table location -------------------------------------*/ #if defined(USER_VECT_TAB_ADDRESS) SCB->VTOR = VECT_TAB_BASE_ADDRESS | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM */ +#else + SCB->VTOR = FLASH_BASE; /* Default Vector Table Location at the base address of Internal Flash */ #endif /* USER_VECT_TAB_ADDRESS */ } diff --git a/system/Drivers/CMSIS/Device/ST/STM32YYxx_CMSIS_version.md b/system/Drivers/CMSIS/Device/ST/STM32YYxx_CMSIS_version.md index 446b86d20a..29b208c2ba 100644 --- a/system/Drivers/CMSIS/Device/ST/STM32YYxx_CMSIS_version.md +++ b/system/Drivers/CMSIS/Device/ST/STM32YYxx_CMSIS_version.md @@ -5,7 +5,7 @@ * STM32F0: 2.3.7 * STM32F1: 4.3.5 * STM32F2: 2.2.6 - * STM32F3: 2.3.8 + * STM32F3: 2.3.9 * STM32F4: 2.6.11 * STM32F7: 1.2.10 * STM32G0: 1.4.5