test(miri): fix the shard failures from the first sharded master run

scripts/miri-tests.sh

@@ -39,6 +39,12 @@ export RUSTFLAGS="-Zrandomize-layout"
 # (rust-lang/miri#1371). Left disabled until both upstream stories close.
 # export MIRIFLAGS="-Zmiri-tree-borrows"
 
+# Miri adds random error to float operations such as exp by default. The
+# suite's oracles compare bit-exact across two code paths (facade vs hpc home,
+# tiled vs reference GEMM), which that error breaks: sigmoid_f32 differed by
+# 3 ulp in tests/simd_facade_reexports.rs on the 2026-11-06 master run.
+export MIRIFLAGS="-Zmiri-deterministic-floats"
+
 # Architectural limit on the Miri sweep:
 #
 # `crate::simd::*` (the production dispatch in `src/simd.rs`) re-exports
@@ -69,6 +75,9 @@ cargo +nightly miri nextest run -v --profile miri \
         ) and !test(/^simd::tests::/)
           and !test(/^hpc::framebuffer::pyramid_tests::/)
           and !test(/^cpu_guard::/)
+          and !test(/^simd_avx2::/)
+          and !test(/^simd_amx::/)
+          and !test(/^simd_int_ops::tests::gemm_u8_i8_/)
        '
 #
 # Tests that are correct but take hours under interpretation (the exhaustive
@@ -101,3 +110,10 @@ cargo +nightly miri nextest run -v --profile miri \
 #    `cpu_guard` reads the CPU with `cpuid`, which is inline assembly; Miri
 #    rejects it ("inline assembly is not supported"). The pre-`main` hook is
 #    `cfg(not(miri))` for the same reason, so test binaries start under Miri.
+#
+# 5. `!test(/^simd_avx2::/)`, `!test(/^simd_amx::/)`,
+#    `!test(/^simd_int_ops::tests::gemm_u8_i8_/)`
+#    Same classes as 2 and 4: `simd_avx2` calls AVX intrinsics ("requires
+#    unavailable target features: avx"), `simd_amx` and the u8 x i8 GEMM
+#    dispatch read `cpuid` (inline assembly). They first showed up on the
+#    2026-11-06 sharded run; the single unsharded run never got that far.

src/simd_nightly/tests.rs

@@ -690,7 +690,8 @@ fn f32x16_round_parity() {
     let src: [f32; 16] = [0.5, 1.5, 2.5, 3.5, 4.5, 5.5, -0.5, -1.5, 0.4, 1.6, 2.3, 3.7, -0.4, -1.6, 100.0, -100.0];
     let result = F32x16::from_array(src).round().to_array();
     for (i, (&r, &s)) in result.iter().zip(src.iter()).enumerate() {
-        assert_eq!(r, s.round(), "lane {i}");
+        // Ties to even on every backend (AVX-512 roundscale, NEON vrndn).
+        assert_eq!(r, s.round_ties_even(), "lane {i}");
     }
 }
 

tests/u9_domino.rs

@@ -97,6 +97,7 @@ fn flip_is_a_half_adder_in_every_lane() {
 /// Random masks (zero, full, one lane, random) at random significances,
 /// including 16, 63, 64 and beyond, in two different orders.
 #[test]
+#[cfg_attr(miri, ignore = "runs past the 20-minute miri per-test limit")]
 fn random_adds_match_the_oracle_in_any_order() {
     let mut s = 0x9E37_79B9_7F4A_7C15u64;
     let mut adds = Vec::new();
@@ -178,6 +179,7 @@ fn the_64k_boundary_flips_bit_16_then_carries_into_bit_17() {
 
 /// u16 products summed through every high representation against `u128`.
 #[test]
+#[cfg_attr(miri, ignore = "runs past the 20-minute miri per-test limit")]
 fn product_sums_match_native_and_d() {
     let mut s = 0x0123_4567_89AB_CDEFu64;
     for (blocks, dense) in [(1usize, false), (300, false), (300, true), (70_000, true)] {
@@ -372,6 +374,7 @@ fn abacus_overflow_refuses_and_leaves_the_counter_unchanged() {
 }
 
 #[test]
+#[cfg_attr(miri, ignore = "runs past the 20-minute miri per-test limit")]
 fn abacus_random_sequences_match_64_u128_counters() {
     let mut s = 0x0123_4567_89AB_CDEFu64;
     const B: usize = 12;