I am an Electronics and Communication Engineering student at IIIT Bhagalpur, building projects in RTL design, FPGA implementation, and verification.
My work includes AXI4-Stream interfaces, hardware encryption on ZCU104, and transistor-level CMOS design using Cadence Virtuoso.
Custom Verilog accelerator integrated with AXI DMA and Cortex-A53 software, with Python reference verification.
- Documented board tests: 11/11 ciphertext and authentication-tag matches against Python AESGCM.
- Modified ciphertext rejected in all 11 documented tamper tests.
- Compared CTR and GCM implementations for throughput, resource utilization, and timing.
Repository · Results · Build instructions
Parameterized SystemVerilog beat FIFO preserving TDATA, TKEEP, and TLAST, with scoreboard-based simulation and formal safety checks.
- 12 passing simulation runs across depths 1, 3, 4, and 16.
- Formal base checks and induction passed for an 8-bit, depth-4 configuration under documented assumptions.
- Deliberately injected handshake bug detected by simulation and formal verification.
- Automated simulation and formal checks through GitHub Actions.
Repository · Validation · Bug case study
Hierarchical 1-bit full adder designed using gpdk180 and simulated with Spectre at 1.8 V.
- Functional simulation across all eight input combinations.
- Output-load characterization from 5 fF to 50 fF.
- Documented propagation-delay measurements, average supply power, schematics, and waveforms.
Scope: schematic-level simulation; physical layout, DRC, and LVS are not included.
| Area | Tools and technologies |
|---|---|
| RTL and verification | Verilog, SystemVerilog, Icarus Verilog, GTKWave |
| Formal verification | Yosys/SMTBMC, Z3 |
| FPGA and interfaces | Vivado, Vitis, ZCU104, AXI4-Stream, AXI4-Lite, AXI DMA |
| CMOS design | Cadence Virtuoso, Spectre, gpdk180 |
| Programming and workflow | Python, C/C++, Git, GitHub Actions, WSL Ubuntu |
Developing my understanding of AXI interfaces, formal properties, and AES-GCM hardware architecture, with an emphasis on reproducible tests and documented results.
Open to internships and entry-level opportunities in RTL design, FPGA development, and design verification.