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MindForze
pipelinedProcessor
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A simple 5-stage pipelined processor in vhdl.
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AddOne.vhd
AddOne.vhd
AddOne.vhd.bak
AddOne.vhd.bak
BranchUnit.do
BranchUnit.do
BranchUnit.vhd
BranchUnit.vhd
BranchUnit.vhd.bak
BranchUnit.vhd.bak
ControlUnit.vhd
ControlUnit.vhd
ControlUnit.vhd.bak
ControlUnit.vhd.bak
DEreg.do
DEreg.do
DEregister.vhd
DEregister.vhd
DEregister.vhd.bak
DEregister.vhd.bak
EMreg.do
EMreg.do
EMregister.vhd
EMregister.vhd
EMregister.vhd.bak
EMregister.vhd.bak
FDreg.do
FDreg.do
FDregister.vhd
FDregister.vhd
FDregister.vhd.bak
FDregister.vhd.bak
FlagsReg.vhd
FlagsReg.vhd
FlagsReg.vhd.bak
FlagsReg.vhd.bak
FlagsRegRes.vhd
FlagsRegRes.vhd
FlagsRegRes.vhd.bak
FlagsRegRes.vhd.bak
ForwardingUnit.vhd
ForwardingUnit.vhd
ForwardingUnit.vhd.bak
ForwardingUnit.vhd.bak
InReg.vhd
InReg.vhd
InReg.vhd.bak
InReg.vhd.bak
InterruptUnit.vhd
InterruptUnit.vhd
InterruptUnit.vhd.bak
InterruptUnit.vhd.bak
MWreg.do
MWreg.do
MWregister.vhd
MWregister.vhd
MWregister.vhd.bak
MWregister.vhd.bak
Mux2.vhd
Mux2.vhd
Mux2.vhd.bak
Mux2.vhd.bak
OutReg.vhd
OutReg.vhd
OutReg.vhd.bak
OutReg.vhd.bak
PC.vhd
PC.vhd
PC.vhd.bak
PC.vhd.bak
PipelineProc.cr.mti
PipelineProc.cr.mti
PipelineProc.mpf
PipelineProc.mpf
Processor.vhd
Processor.vhd
Processor.vhd.bak
Processor.vhd.bak
README.md
README.md
Reg.vhd
Reg.vhd
Reg.vhd.bak
Reg.vhd.bak
RegPc.vhd.bak
RegPc.vhd.bak
RegSp.vhd
RegSp.vhd
RegSp.vhd.bak
RegSp.vhd.bak
Regfile.vhd
Regfile.vhd
Regfile.vhd.bak
Regfile.vhd.bak
SPtest.do
SPtest.do
SubOne.vhd
SubOne.vhd
SubOne.vhd.bak
SubOne.vhd.bak
alu.do
alu.do
alu.vhd
alu.vhd
alu.vhd.bak
alu.vhd.bak
dataMem.do
dataMem.do
dataMemory.vhd
dataMemory.vhd
dataMemory.vhd.bak
dataMemory.vhd.bak
instMem.do
instMem.do
instructionMemory.vhd
instructionMemory.vhd
instructionMemory.vhd.bak
instructionMemory.vhd.bak
int.do
int.do
my_adder.vhd
my_adder.vhd
my_n_adder.vhd
my_n_adder.vhd
n_bit_adder.vhd
n_bit_adder.vhd
n_bit_adder.vhd.bak
n_bit_adder.vhd.bak
pipelineproc.cr.mti
pipelineproc.cr.mti
pipelineproc.mpf
pipelineproc.mpf
processor.do
processor.do
transcript
transcript
vsim.wlf
vsim.wlf
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5-stage pipelined processor
About
A simple 5-stage pipelined processor in vhdl.
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forks
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