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research: point-source CPU phase 4b — step-0 containment route A/B (PyAutoArray#579) - #330

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feature/point-source-cpu-p4b
Sep 27, 2026
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feature/point-source-cpu-p4b

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Summary

Phase 4b data for the point-source CPU speed-up (PyAutoArray#579): the interleaved A/B of the step-0 containment routes that PyAutoArray #580 added. That PR is merged, with structured as the default. The results are bit-identical on every route.

On the quotable RAL Xeon 8490H row (job 357321), the new default structured runs 1.44× the old gather on a single call and 2.27× at vmap-16, and step-0 containment falls 60 %. Compile is +8.6 % and XLA temp memory −47 %. The node was loaded (loadavg ~200 on 236 cores), so the absolute ms are not comparable to phase 4a; the interleaved ratios stand. The supplementary EPYC 7702 CPU row gives 1.62×. The A100 row shows no regression (1.00×).

Scripts Changed

  • scripts/point_source_image/likelihood_breakdown/solver_config_sweep.py:
    • --step0-route {control,gather,nopad,components,structured}, a library route A/B beside control, with a per-route bit-identity gate.
    • A route-aware route_input_materialisation_ms. The old triangle_materialisation_ms always gathered, so it is relabelled general_gather_reference_ms.
    • A backend-aware fiducial gate: CPU …812, A100 …806.
    • The MAX_CONTAINING_SIZE __defaults__ patch no longer clobbers the new step0_layout=None default.
  • scripts/point_source_image/likelihood_breakdown/image_plane.py: the ray-trace prefix is now jnp.sum(plane.vertices), so the gather counts as containment. The old job-356365 split is marked not quotable.
  • hpc/batch_cpu/…solver_config_sweep_step0_{ral_cpu,gpu_node_cpu}_fp64 and hpc/batch_gpu/…_step0_a100_fp64: the RAL submits. They use the branch-clone PyAutoArray and assert import provenance.
  • results/breakdown/point_source_image/solver_config_sweep_step0_{hpc_ral_cpu,hpc_ral_cpu_epyc7702,hpc_ral_a100,laptop_cpu}_fp64.{json,png} and the three RAL job logs.
  • results/notes/point_source_cpu_campaign.md: the Phase 4b section.

Upstream PR

PyAutoLabs/PyAutoArray#580 (MERGED, 4383ea81)

Test Plan

  • The changed harness ran end to end on the laptop, the RAL 8490H, RAL EPYC and RAL A100. all_gates_pass: true on the CPUs; the A100 JSON predates the backend-aware fiducial fix, and the ledger says so.
  • Every route is bit-identical in stream, fiducial and prior log L, positions, image counts, grad and vmap 1/4/16. Completeness is 200/200 prior and 200/200 stress.
  • scripts/misc/tooling/build_readme.py --check is clean.
  • No local paths in any committed artefact.
  • The targeted workspace smoke for the library change (31/31) ran at PyAutoArray #580.

Part of PyAutoLabs/PyAutoArray#579.

Generated by the PyAutoLabs agent workflow.

🤖 Generated with Claude Code

Jammy2211 and others added 9 commits September 27, 2026 16:19
…sweep (PyAutoArray#579)

--step0-route (comma list of control,gather,nopad,components,structured)
replaces the geometry sweep with step0_<route> configs beside control at the
production geometry. Each sets autoarray's _STEP0_CONTAINMENT for the
duration of tracing only (fresh closure + clear_caches per route, as before).
Every route gets the timing rounds, completeness draws, grad gate, vmap
1/4/16 and its own step-0 prefix split. A new gate,
gates.step0_route_bit_identity, requires stream / fiducial / prior log L,
prior + stress positions, image counts, gradients and vmap values to be
bit-identical to the control. Output: solver_config_sweep_step0_<config>.

Also fix the MAX_CONTAINING_SIZE patch so it keeps the later __init__
defaults. Overwriting __defaults__ with a 1-tuple bound the new
step0_layout=None default to max_containing_size.

Co-Authored-By: Claude Opus 5.5 <noreply@anthropic.com>
…yAutoArray#579)

WSL2 laptop, 20 rounds x 20 calls, 200 prior + 200 stress draws, vmap
1/4/16, PyAutoArray c13b2d73 (library default "structured"). All routes are
bit-identical to control and all_gates_pass is True. Median ms per call:
control(=structured) 1.631, gather 2.221, nopad 2.249, components 1.555,
structured 1.613. The ship evidence is the RAL 8490H and A100 rows, which
come later.

Co-Authored-By: Claude Opus 5.5 <noreply@anthropic.com>
…mage_plane ray-trace prefix excludes the gather (PyAutoArray#579)

solver_config_sweep: the step0_split 'ray_trace_materialised' prefix returned
plane.triangles, the general (N,3,2) gather, on every route, so it read ~0.8 ms
whatever the route. It is now two prefixes: route_inputs (the six barycentric
input components the ACTIVE route feeds _barycentric_contains, captured at trace
time) -> route_input_materialisation_ms, and general_gather (plane.triangles,
route-independent reference; phase 4a's triangle_materialisation_ms) ->
general_gather_reference_ms. Containment stays the headline number.

image_plane: each step's ray-trace prefix is now jnp.sum(plane.vertices), so the
vertices[indices] gather is counted in containment, not ray trace. Pre-#579 rows
(job 356365) keep the old split and are marked not quotable in the docstring.

Co-Authored-By: Claude Opus 5.5 <noreply@anthropic.com>
…A/B (PyAutoArray#579)

The unpushed PyAutoArray branch is a bundle-fetched clone of the shared mirror
prepended to PYTHONPATH; the job refuses to run unless autoarray imports from it
(and the rest from the mirror), and asserts the JSON source_revisions after the
run, including that PyAutoArray descends from c13b2d73. CPU pinned to the phase-4a
8490H node euclid-ral-compute-10-4; A100 asserts the gpu backend.

Co-Authored-By: Claude Opus 5.5 <noreply@anthropic.com>
…he step-0 A/B (PyAutoArray#579)

ral is saturated (10-4 memory fully allocated, load ~155); the known fallback is
an idle gpu-partition node with no --gres. Pinned to euclid-ral-gpu-2, away from
the A100 leg; refuses to run if a GPU is visible.

Co-Authored-By: Claude Opus 5.5 <noreply@anthropic.com>
…d EPYC 7702 CPU (357335, supplementary) (PyAutoArray#579)

A100: every route 1.00x gather (launch-bound, as expected). EPYC 7702 CPU-only on
gpu-2 (ral saturated): structured 1.62x / components 1.61x over gather; labelled
supplementary, a different CPU from phase 4a's 8490H. Every route is bit-identical
to the control on both; 200/200 + 200/200 completeness.

Co-Authored-By: Claude Opus 5.5 <noreply@anthropic.com>
…route A/B (PyAutoArray#579)

EPYC 7702 CPU (357335, supplementary): structured 1.62x / components 1.61x over
gather, containment -66 %, vmap-16 1.87x; A100 (357322) ~1.00x, no regression;
every route bit-identical. The quotable 8490H row (357321) is still queued on the
saturated ral partition. Recommendation: keep structured as the default.

Co-Authored-By: Claude Opus 5.5 <noreply@anthropic.com>
Co-Authored-By: Claude Opus 5.5 <noreply@anthropic.com>
…ase 4b

Co-Authored-By: Claude Opus 5.5 <noreply@anthropic.com>
…cell + measured walls (357321/357322/357335)

Co-Authored-By: Claude Opus 5.5 <noreply@anthropic.com>
@Jammy2211
Jammy2211 merged commit 81af10f into main Sep 27, 2026
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@Jammy2211
Jammy2211 deleted the feature/point-source-cpu-p4b branch September 27, 2026 15:39
@Jammy2211 Jammy2211 removed the pending-release PR queued for the next release build label Oct 7, 2026
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