Repository navigation
ESP32 builds: the CPU at its chip's rated clock, beside flash and PSRAM - #377
Merged
Merged
Conversation
Every ESP32 board now runs its CPU at the highest clock its chip is rated for, as flash and PSRAM already do. A 48 kHz synth with a reverb clicked on a classic ESP32 at upstream's 160 MHz and played clean at 240. build_mp.py reads the CPU clock and target from the built sdkconfig and names a CPU below its chip's rating in the same boxed warning as slow flash and PSRAM, with the sdkconfig lines to set. The ratings are the top of ESP-IDF's CPU clock choice for each target: 240 MHz for the ESP32, S2, S3 and C5, 160 for the C3, C6 and C61, 120 for the C2, 96 for the H2, and 400 for a P4 of revision 3 or later (360 for an image that supports earlier ones). A single-core classic ESP32 build is held to 160, the rating of the ESP32-S0WD and D2WD. A P4 image that also runs on revision 0 no longer warns about its 40 MHz flash: ESP-IDF offers nothing faster there. The QT Py ESP32 Pico variant now sets 240 MHz, and so does every S3 build (upstream's octal-PSRAM variant already did; the generic quad-PSRAM S3 build ran at 160). The P4 builds already run at their rating. tests/test_build_mp.py covers each case; with the CPU left out of the warning, three of its tests fail.
This file contains hidden or bidirectional Unicode text that may be interpreted or compiled differently than what appears below. To review, open the file in an editor that reveals hidden Unicode characters.
Learn more about bidirectional Unicode characters
Sign up for free
to join this conversation on GitHub.
Already have an account?
Sign in to comment
Add this suggestion to a batch that can be applied as a single commit.This suggestion is invalid because no changes were made to the code.Suggestions cannot be applied while the pull request is closed.Suggestions cannot be applied while viewing a subset of changes.Only one suggestion per line can be applied in a batch.Add this suggestion to a batch that can be applied as a single commit.Applying suggestions on deleted lines is not supported.You must change the existing code in this line in order to create a valid suggestion.Outdated suggestions cannot be applied.This suggestion has been applied or marked resolved.Suggestions cannot be applied from pending reviews.Suggestions cannot be applied on multi-line comments.Suggestions cannot be applied while the pull request is queued to merge.Suggestion cannot be applied right now. Please check back later.
Every ESP32 board now runs its CPU at the highest clock its chip is rated for, as flash and PSRAM already do. At upstream's default 160 MHz, a 48 kHz synth with a reverb on a classic ESP32 ran out of time in each block and clicked; at 240 it plays clean. A build that leaves the CPU below its chip's rating now says so in the same boxed warning as slow flash or PSRAM, with the three sdkconfig lines to set.
The ratings are the top of ESP-IDF's CPU clock choice for each target in the pinned IDF (v5.5.4), which match the datasheets: 240 MHz for the ESP32, S2, S3 and C5, 160 for the C3, C6 and C61, 120 for the C2, 96 for the H2, and 400 for a P4 of revision 3 or later. A P4 image that supports earlier revisions is held to 360, which is all IDF offers there short of an experimental option; a single-core classic ESP32 build to 160, the rating of the ESP32-S0WD and D2WD. The QT Py ESP32 Pico variant now sets 240 MHz, as the Audio Kit does, and so does every S3 build: upstream's octal-PSRAM variant (under LCD_4_3, LCD_7 and T_EMBED) already did, but the generic quad-PSRAM S3 build ran at 160. The P4 variants already run at their rating. A P4 image for revision 0 chips also stops warning about its 40 MHz flash, since IDF offers nothing faster there.
How it was checked: the new tests in tests/test_build_mp.py pass, and with the CPU left out of the warning three of them fail. The note was run over existing build sdkconfigs (P4 C6_WIFI, WIFI6_DEV_KIT_H2 and PRE_REV3_C6_WIFI, S3 LCD_7 and SPIRAM_OCT): all quiet. A full
--port esp32 --board ESP32_GENERIC --variant QTPY_PICO --flash 8MB --modules allbuild finished with no warning, and its sdkconfig carriesCONFIG_ESP_DEFAULT_CPU_FREQ_MHZ=240,CONFIG_ESPTOOLPY_FLASHFREQ_80M=yandCONFIG_SPIRAM_SPEED_80M=y. Not checked: no board was flashed with these images, so the clocks haven't been read back from a running chip.