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rp2 builds: the CPU at its chip's rated clock, 200 MHz on an RP2040 - #380
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Raspberry Pi certified the RP2040 for 200 MHz at 1.15 V in pico-sdk 2.1.1, but the SDK still defaults to 125 MHz unless a build asks for its fastest supported clock. Every rp2 build now gets variants/rp2/board.cmake after the board's own settings, which sets PICO_USE_FASTEST_SUPPORTED_CLOCK; the SDK then raises the core voltage before the clock. Flash and PSRAM follow through the port's divider and stay inside their rating. The RP2350's fastest clock is its 150 MHz default, so its images don't change. The CircuitPython Feather RP2040 LVGL board asks for the same clock, and build_mp.py now says so after any rp2 build below its chip's rating, and after a CircuitPython espressif build below its rated CPU, flash or PSRAM clock, as it already does for MicroPython esp32 builds. Checked with build_mp.py's unit tests (with the setting and the include removed in turn, the new ones fail), and an RP2040-Plus build whose compile flags, generated board folder and boot code carry the 200 MHz clock and the voltage change.
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Every rp2 image now runs its CPU at the fastest clock its chip is rated for. On an RP2040 that is 200 MHz, which Raspberry Pi certified in pico-sdk 2.1.1 at a core voltage of 1.15 V, where the SDK's default is still 125. On an RP2350 the fastest is its 150 MHz default, so those images are unchanged. This follows what the esp32 builds already do for their CPU, flash and PSRAM clocks.
build_mp.py now makes a board folder for every rp2 build, and its
mpconfigboard.cmakeincludes the board's own settings and thenvariants/rp2/board.cmake, which setsPICO_USE_FASTEST_SUPPORTED_CLOCK. With that set, the SDK raises the core voltage at boot before it raises the clock. Flash and PSRAM follow through the port's divider and stay inside their rating: 100 MHz on boards that ran flash at 62.5, 50 MHz on boards whose boot stage reads at a quarter of the CPU clock, and 75 MHz on an RP2350. After a build, build_mp.py reads the clock from the build's CMake cache and compile flags, and warns when an image runs below its chip's rating. The CircuitPython Feather RP2040 LVGL board asks for the same clock in itsmpconfigboard.mk, and CircuitPython espressif builds now get the same rated-clock check as MicroPython esp32 builds.I ran build_mp.py's unit tests (101 pass; with the setting or the include removed, the new ones fail). An RP2040-Plus build carries
-DPICO_USE_FASTEST_SUPPORTED_CLOCK=1in its compile flags, and its boot code holds the 1200 MHz PLL, the 200 MHz clock and the voltage change. A plain RPI_PICO image boots to the REPL in Wokwi's RP2040 simulator, wheremachine.freq()reads 200000000. The CircuitPython Feather image's boot code holds the same clock and voltage change, and nothing in CircuitPython's startup sets the clock back. A Pico Plus 2 W build reads 150 MHz, prints no warning, and is byte-identical to the same build from main.Not verified: no RP2040 board has run the 200 MHz image on hardware yet, and the simulator doesn't model flash timing, so flash reads at 100 MHz are unproven, and the CircuitPython Feather image hasn't been flashed.