Dual-Issue Out-of-Order Superscalar RV32I Processor
1st Place + Special Jury Award — SanDisk Hardware Hackathon · 100+ competing teams
A fully synthesizable out-of-order execution engine implementing the Tomasulo algorithm for the RISC-V RV32I ISA. The front-end — fetch, decode, register renaming, and dynamic hazard-aware dispatch — is complete and verified. ROB commit-stage integration is under active development.
The front-end has been verified in simulation with directed self-checking testbenches. The waveform below demonstrates simultaneous dual-issue dispatch with correct RAT allocation and RAW hazard detection working.
| Component | Status | Notes |
|---|---|---|
| 2-wide instruction fetch | Complete | PC + IMEM, handles branch boundaries |
| 2-wide decode | Complete | RV32I full decode, immediate gen |
| Register Alias Table (RAT) | Complete | 32 arch → 64 phys, dual-alloc per cycle |
| Free list management | Complete | Circular free list with head/tail pointers |
| RAW hazard detection | Complete | Combinatorial intra-group bypass, scoreboard |
| Issue queue dispatch | Complete | issue0_valid + issue1_valid verified in sim |
| CDB broadcast | Complete | broadcast_valid confirmed in waveform |
| Execution units (ALU) | Complete | Verified via directed self-check |
| ROB commit stage | In progress | Precise exception support being integrated |
The waveform shows:
issue0_validandissue1_validasserting simultaneously — dual-issue workingprd_0andprd_1incrementing by 2 each active cycle — RAT dual-allocation correctbroadcast_validasserted — CDB writeback path activefree_ptradvancing correctly — no free list corruption under back-to-back dispatch
# Icarus Verilog with SystemVerilog support
brew install icarus-verilog # macOS
sudo apt install iverilog # Ubuntu
# Waveform viewer
# Surfer (recommended): https://surfer-project.org
# or GTKWave: sudo apt install gtkwavegit clone https://github.com/devtyagi3909/riscv-ooo-core.git
cd riscv-ooo-core
# Full directed testbench
./scripts/run_verification.sh
# Expected output:
# [PASS] Reset: PC held at 0
# [PASS] 2-wide fetch/decode: ADDI pair decoded correctly
# [PASS] RAT: prd_0/prd_1 allocated, free_ptr +2 on active cycle
# [PASS] Dispatch: issue0_valid and issue1_valid asserted simultaneously
# [PASS] CDB: broadcast_valid observed
# PASS: cpu_tb directed verification completed with no errors.surfer waveforms/cpu.vcd
# or
gtkwave waveforms/cpu.vcdriscv-ooo-core/
├── rtl/ # Synthesizable SystemVerilog
│ ├── fetch/ # 2-wide instruction fetch
│ ├── decode/ # RV32I decode, immediate generation
│ ├── rename/ # RAT, free list, physical register file
│ ├── dispatch/ # Issue queue, hazard scoreboard
│ └── execute/ # ALU, CDB broadcast
├── tb/
│ └── cpu_tb.v # Directed self-checking testbench
├── scripts/
│ └── run_verification.sh
├── waveforms/
│ └── cpu.vcd
└── assets/
└── surfer_trace.png # Waveform screenshot
This core was built at the SanDisk Hardware Hackathon — a 48-hour hardware design competition judged by senior engineers from Sandisk/Western Digital and academic faculty, fielding over 100 teams from across India.
The submission was awarded:
- 1st Place — overall hardware design category
- Special Jury Award — for microarchitectural depth and correctness of the OoO implementation
- Patterson & Hennessy — Computer Organization and Design: RISC-V Edition
- Tomasulo, R. (1967). An Efficient Algorithm for Exploiting Multiple Arithmetic Units
- RISC-V International — RISC-V ISA Specification
MIT — see LICENSE