esp32s3: add support for the cores scheduler by deadprogram · Pull Request #5910 · tinygo-org/tinygo

deadprogram · 2026-10-17T23:11:26Z

This PR adds -scheduler=cores to the ESP32-S3, so goroutines can run on both CPUs. The default scheduler is still tasks.

Fixes #5353. This replaces draft PR #5358, thank you for the start on this work.

Commits

targets: fix two context bugs in the esp32s3 interrupt handler. These bugs are already in dev and can also occur in single core programs. The GC stop the world hits both of them.
- The handler moves a1 to its frame. That register is also the a5/a9/a13 of the caller of the interrupted function. A deep handler spilled that caller's a0..a3 to the wrong address, so the interrupted code returned through garbage. The handler now moves the four words to the place where the underflow reads them.
- SCOMPARE1 was not saved. If a handler used an atomic between an interrupted wsr.scompare1 and s32c1i, that compare and swap reported success without a store.
esp32s3: add support for the cores scheduler.
- Core 1 starts at call_start_cpu1 with its own system stack, as in ESP-IDF start_other_core.
- The FROM_CPU software interrupts on CPU line 3 wake a waiting core and pause it for the GC. All free level 1 lines from 6 to 30 were already in use, so interrupt.New now accepts lines 1 to 30.
- Spin locks use s32c1i. ticks() takes a lock, because both cores share the timer update latch.
- interrupt.In, interruptPending and the sleep wake flags are per core.
- Adds machine.CurrentCore and machine.NumCores. examples/core-assign now also builds for the ESP32-S3.

Cost

The second system stack adds 4 KB of RAM to every esp32s3 build, as on rp2040 and rp2350.
The unicore code size grows by 72 bytes, from the interrupt handler fixes.

Tested

Tested on a XIAO ESP32-S3:

examples/core-assign gives the expected output.
A 2 minute stress test passed with no errors: 679 GC cycles and 1.19M interrupts. It ran:
- a channel ping-pong between the cores
- allocators on both cores
- sleepers with different periods on both cores
- time.Now monotonicity checks on both cores
- a 10 kHz timer interrupt
examples/serial works with both schedulers.
With the espradio changes in radio: run the blob on core 0 with the cores scheduler espradio#101, scan, connect with DHCP, http-get, the BLE scanner and ESP-NOW work with both schedulers.

Known limits

Only core 0 gets the timer alarm interrupt, so core 1 busy waits in sleepTicks.

The level 1 handler moves a1 to its frame. That register is also the a5, a9 or a13 of the caller of the interrupted function. So a handler deep enough to spill that caller saved its a0..a3 below the frame, and not below the interrupted SP where the underflow reads them back. The interrupted code then returned through garbage. Copy the four words to the correct place after the handler returns. The handler also did not save SCOMPARE1. If a handler used an atomic between an interrupted wsr.scompare1 and s32c1i, that compare and swap reported success without a store. Both can occur in single core programs. The GC stop the world for the cores scheduler hits both of them.

github-actions · 2026-10-17T23:28:19Z

Size difference with the dev branch:

Binary size difference

 flash                          ram
 before   after   diff          before   after   diff
  23684   23680     -4  -0.02%    8588    8588      0   0.00% tinygo build -size short -o ./build/test.bin -target=esp32-coreboard-v2 ./examples/gdew0154m09/main.go
  12464   12460     -4  -0.03%    4696    4692     -4  -0.09% tinygo build -size short -o ./build/test.elf -target=m5stack-core2 ./examples/ft6336/basic/
  20044   20040     -4  -0.02%    4964    4964      0   0.00% tinygo build -size short -o ./build/test.elf -target=m5stack-core2 ./examples/ft6336/touchpaint/
  18772   18772      0   0.00%    6876    6876      0   0.00% tinygo build -size short -o ./build/test.hex -target=feather-rp2040 ./examples/adafruit4650
  63916   63916      0   0.00%    6884    6884      0   0.00% tinygo build -size short -o ./build/test.hex -target=itsybitsy-m0 ./examples/adt7410/main.go
  11436   11436      0   0.00%    5436    5436      0   0.00% tinygo build -size short -o ./build/test.hex -target=itsybitsy-m0 ./examples/adxl345/main.go
  15612   15612      0   0.00%    7492    7492      0   0.00% tinygo build -size short -o ./build/test.hex -target=pybadge ./examples/amg88xx
  10668   10668      0   0.00%    5396    5396      0   0.00% tinygo build -size short -o ./build/test.hex -target=itsybitsy-m0 ./examples/apa102/main.go
  13948   13948      0   0.00%    7252    7252      0   0.00% tinygo build -size short -o ./build/test.hex -target=nano-33-ble ./examples/apds9960/proximity/main.go
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   8856    8856      0   0.00%    2320    2320      0   0.00% tinygo build -size short -o ./build/test.hex -target=microbit ./examples/at24cx/main.go
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davecheney

LGTM with some nit picking suggestions about code duplication if you want to address them.

davecheney · 2026-10-17T23:27:23Z


+// CurrentCore returns the core number the call was made from. PRID bit 13 is
+// the core ID, see xt_utils_get_raw_core_id in esp-idf xt_utils.h.
+func CurrentCore() int {


can you use go:linkname to deduplicate this? Its less about code size and more about DRYing it up so the knowledge of how to get the current core is defined once.

davecheney · 2026-10-17T23:35:03Z

+	"unsafe"
+)
+
+const numCPU = 2


I'm not in love with the duplication between numCPU and maxCores. I know they're different packages, but ideally the number of cores should be defined once.

davecheney · 2026-10-17T23:35:52Z

+// Return the current core number: 0 or 1. PRID bit 13 is the core ID, see
+// xt_utils_get_raw_core_id in esp-idf components/xtensa/include/xt_utils.h.
+func currentCPU() uint32 {
+	return uint32(device.AsmFull("rsr {}, PRID", nil)>>13) & 1


this is the third version of currentCore, but it has a different name this time. Definitely time for Atwood's rule of 3s

deadprogram · 2026-10-18T00:19:12Z

Thanks @davecheney all of them are addressed.

pause() now uses SystemStack().
runtime.currentCPU is now the only place that reads PRID. machine and runtime/interrupt use go:linkname to call it.
interrupt.In and handleInterrupt now index with currentCPU()&1. The bounds check is gone in the IR for both schedulers.
Done now instead of later. interrupt_esp32s3_cores.go and interrupt_esp32s3_unicore.go are removed. inInterrupt is [2]bool in both builds, one flag for each hardware core. The unicore runtime.currentCPU still returns 0 without reading PRID.
maxCores is gone, so numCPU is the only core count.
Same as 2.
signalCore(core, value) now sets or clears the FROM_CPU interrupt, and the handler and startup use it too.

Retested on a XIAO ESP32-S3. A 130 s stress run with -scheduler=cores passed with 9240 GC cycles and 1.1M timer interrupts, checking interrupt.In and machine.CurrentCore on both cores. The same test with -scheduler=tasks also passed.

davecheney

LGTM. No notes

rdon-key · 2026-10-18T03:25:32Z

It's exciting to see multicore support coming to the ESP32-S3. Thanks for all the work on this!

I noticed a potential issue with GPIO and I2S DMA interrupt initialization under the cores scheduler.

Both peripherals route their interrupt source to core 0 through INTERRUPT_CORE0:

GPIO (CPU interrupt line 10): setupPinInterrupt() in machine_esp32s3.go
I2S DMA (CPU interrupt line 18): i2sEnableInterrupt() in machine_esp32s3_i2s.go

However, interrupt.Enable() only sets the bit in the calling core's INTENABLE. If this runs in a goroutine that is currently on core 1, the line is enabled on core 1 instead, so the handler never runs:

GPIO: setup runs once via sync.Once, so later SetInterrupt() calls don't fix it.
I2S: WriteMono()/WriteStereo() stall once the DMA buffers fill, and ReadMono()/ReadStereo() wait forever for data.

This isn't limited to goroutines assigned to core 1. Any goroutine without an affinity, including main after it blocks, can resume on either core, so the failure could be intermittent.

I haven't reproduced this on hardware, but machine.AssignCore(1) followed by pin.SetInterrupt(...) should show it if I'm reading the code correctly.

If this is a real issue, one option could be to forward Enable() from core 1 to core 0 through the existing signalCore()/crossCoreHandler() path, so peripheral interrupts are always enabled on core 0.

Start core 1 and run goroutines on both cores with -scheduler=cores. The default scheduler is still tasks. - Core 1 starts at call_start_cpu1 with its own system stack. - The FROM_CPU software interrupts on CPU line 3 wake a waiting core and pause it for the GC. Lines 1 to 5 are now valid for interrupt.New. - Spin locks use s32c1i. ticks() takes a lock, because the timer update latch is shared by both cores. - interrupt.In and the sleep wake flags are per core. - interrupt.Enable on core 1 enables the line on core 0, since peripheral interrupts are routed to core 0. - Add machine.CurrentCore and machine.NumCores. Fixes #5353. Replaces #5358.

deadprogram · 2026-10-18T08:34:51Z

Thanks @rdon-key you are right, and it reproduces on hardware.

On a XIAO ESP32-S3, a goroutine with machine.AssignCore(1) that calls SetInterrupt and then toggles the pin got 0 of 100 GPIO callbacks. I2S WriteStereo from core 1 stalled after 512 frames.

The fix follows your suggestion. On core 1, interrupt.Enable sets a request bit and signals core 0 through signalCore. crossCoreHandler on core 0 enables the line in its own INTENABLE, then clears the bit. Core 1 waits for that. Core 1 enables its own cross core line directly.

With the fix the same test gets 100 of 100 GPIO callbacks, and I2S runs at about 44.1k frames per second. The stress test still passes with both schedulers.

deadprogram · 2026-10-18T14:55:32Z

Thank you @deadprogram and @rdon-key for review and feedback. Now merging.

deadprogram mentioned this pull request Oct 17, 2026

radio: run the blob on core 0 with the cores scheduler tinygo-org/espradio#101

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davecheney approved these changes Oct 17, 2026

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deadprogram force-pushed the esp32s3-cores branch from 1eb3032 to 511e631 Compare October 18, 2026 00:19

davecheney approved these changes Oct 18, 2026

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deadprogram force-pushed the esp32s3-cores branch from 511e631 to 227b306 Compare October 18, 2026 08:34

deadprogram merged commit e8cfe79 into dev Oct 18, 2026
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deadprogram deleted the esp32s3-cores branch October 18, 2026 14:55

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esp32s3: add support for the cores scheduler - #5910

esp32s3: add support for the cores scheduler#5910
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