Skip to content
#

digital-logic-design

Star

Here are 227 public repositories matching this topic...

Language: All
Filter by language
All 227 Verilog 38 VHDL 27 C++ 18 Java 9 Python 7 HTML 5 JavaScript 5 SystemVerilog 5 Assembly 4 C 4
Sort: Most stars
Sort options
Most stars Fewest stars Most forks Fewest forks Recently updated Least recently updated

Multimedia-Processing / Digital-Logic-Design

Star 19

透過數位邏輯結合VHDL與Verilog的過程，作為從基礎數位邏輯到計算機系統結構，並實作出一顆CPU的教學書籍，希望未來可以成為教學範例檔案。目前將開發轉移到GitLab，因為可以呈現數學與MUL圖。

fpga digital vhdl verilog learn xilinx digital-logic systemverilog hdl verilog-hdl xilinx-fpga xilinx-vivado digital-logic-design altera-fpga altera-cyclone-v-sockit altera-cyclone-iii-de0 altera-quartus soc-kit altera-cyclone vhdl-verilog
  • Updated Oct 25, 2023
  • Verilog
FAST-NUCES-Material

arham2003 / FAST-NUCES-Material

Star 16

BS AI FAST NUCES Coursework material from 2022 - 2026. Access Course Outlines, Books, and Slides with ease.

nlp computer-science machine-learning ai computer-vision operating-system artificial-neural-networks recommender-system entrepreneurship programming-fundamentals database-systems coal data-structures-and-algorithms digital-logic-design fast-nu generative-ai fast-nuces genai agentic-ai ppit
  • Updated Jun 28, 2026
  • Jupyter Notebook

ramiomer94 / VLSI-design-projects

Star 13

This repository contains all major projects completed as part of the EECS 4612: Digital VLSI Design course at York University. The projects showcase the complete ASIC design flow — from RTL design to GDSII layout — using industry-grade tools like Cadence Genus, Innovus, and Virtuoso.

verilog semiconductor-physics genus custom-layout virtuoso digital-logic-design static-timing-analysis vlsi-design asic-design rtl-design innovus standard-cells eda-tools rtl-verification cmos-design rtl-to-gdsii cadence-tools
  • Updated Jul 12, 2025
  • Verilog
DIGITAL-LOGIC-DESIGN-AND-ANALYSIS-AND-DIGITAL-SYSTEM-LAB

Amey-Thakur / DIGITAL-LOGIC-DESIGN-AND-ANALYSIS-AND-DIGITAL-SYSTEM-LAB

Sponsor
Star 11

CSC302: Digital Logic Design and Analysis [DLDA] & CSL301: Digital System Lab [DS Lab] | SE Semester III | Computer Engineering

computer-science engineering vhdl computer-engineering textbooks boolean-algebra digital-systems study-materials digital-electronics digital-logic-design vhdl-coursework university-of-mumbai digital-system-design digital-logic-design-lab ameythakur amey megasatish reference-books ameyarc amey-thakur
  • Updated Sep 5, 2026

hasnainroopawalla / digital-logic-simulator

Star 10

Interactive digital logic circuit simulator built with React and WebGPU. Build logic gates, connect circuits, create custom chips, and simulate digital logic in your browser.

react javascript education typescript browser simulator webpack binary shaders logic webassembly wasm circuit-simulator digital-logic logic-gates boolean-algebra logic-gate-simulator webgpu gates digital-logic-design
  • Updated Oct 15, 2026
  • TypeScript

Add this topic to your repo

To associate your repository with the digital-logic-design topic, visit your repo's landing page and select "manage topics."

Learn more