Design and simulation of an ultra-low power 8-input Domino OR gate operating in the sub-threshold region using Cadence Virtuoso (GPDK 180nm), with power, delay, and switching threshold analysis.
-
Updated
Jun 28, 2026
#
subthreshold
Here are 2 public repositories matching this topic...
All-MOSFET subthreshold voltage reference in 180 nm CMOS — design, characterisation, and reliability analysis
monte-carlo reliability spectre cadence cmos ic-design analog-design voltage-reference nbti subthreshold
-
Updated
Sep 6, 2026
Add this topic to your repo
To associate your repository with the subthreshold topic, visit your repo's landing page and select "manage topics."