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Cortex-M: add opt-in explicit layout lowering - #21928

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Cortex-M: add opt-in explicit layout lowering#21928
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@rascani rascani commented Aug 18, 2026

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Stack from ghstack (oldest at bottom):

  • (to be filled)

Thread an experimental explicit-layout mode through the shared Cortex-M Edge compile configuration, AOT compiler, quantizer support, tester, and pass manager. Legacy dim-order export remains the default. Explicit mode disables dim-order operators, converts Conv1d through the common transform, and uses the common channels-last dialect and region optimizer to form layout regions across supported convolution and pooling operations.

Lower channels-last anchors to fixed NHWC Cortex-M schemas and surviving structural boundaries to cortex_m::transpose. Constant padding inside a region selects pad_nhwc. Channel-broadcast add and multiply use explicit-layout quantizer checks and fixed NHWC runtime schemas, keeping these regions int8 instead of introducing float QDQ islands. Equal-shape add and multiply continue to use the layout-independent legacy schemas. Softmax remains outside automatic propagation so its dimension satisfies the Cortex-M last-dimension kernel contract.

Preserve complete operator metadata through common replacement, while explicitly requiring per-tensor activation and output qparams for tensors whose dimensions change. Per-channel activation or output axes are rejected from explicit regions until a backend remapping contract exists; per-channel weight metadata remains valid because weights are not permuted.

Add graph, planned-memory, and FVP coverage for regular, depthwise, transpose, pooling, padding, multi-op, channel-broadcast add/multiply, softmax-barrier, and Conv1d paths, including the public AOT flag. Planned-arena tests assert the expected targets before comparing memory. The channel-broadcast cases plan 1,600 bytes in both modes, eliminating the previous explicit-mode 2,304-byte float-intermediate plan.

Differential Revision: D116374086

cc @digantdesai @freddan80 @per @zingo @oscarandersson8218 @mansnils @Sebastian-Larsson @robell

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rascani requested a review from digantdesai as a code owner August 18, 2026 23:06
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🔗 Helpful Links

🧪 See artifacts and rendered test results at hud.pytorch.org/pr/pytorch/executorch/21928

Note: Links to docs will display an error until the docs builds have been completed.

❌ 29 New Failures, 1 Unrelated Failure, 1 Unclassified Failure

As of commit 624ccd3 with merge base ed2d9ec (image):

NEW FAILURES - The following jobs have failed:

UNCLASSIFIED FAILURE - DrCI could not classify the following job because the workflow did not run on the merge base. The failure may be pre-existing on trunk or introduced by this PR:

  • Build CMSIS Pack / build-cmsis-pack / linux-job (gh) (this job did not run on the merge base, so DrCI cannot tell whether the failure is pre-existing)
    /pytorch/executorch/backends/cortex_m/ops/cortex_m_ops_common.h:357:22: error: invalid conversion from 'int64_t (*)(ActivationLayout)' {aka 'long long int (*)(ActivationLayout)'} to 'ssize_t' {aka 'int'} [-fpermissive]

BROKEN TRUNK - The following job failed but were present on the merge base:

👉 Rebase onto the `viable/strict` branch to avoid these failures

This comment was automatically generated by Dr. CI and updates every 15 minutes.

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@meta-cla meta-cla Bot added the CLA Signed This label is managed by the Facebook bot. Authors need to sign the CLA before a PR can be reviewed. label Aug 18, 2026
@rascani
rascani marked this pull request as draft August 18, 2026 23:08
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