Cortex-M: add opt-in explicit layout lowering - #21928
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Stack from ghstack (oldest at bottom):
Thread an experimental explicit-layout mode through the shared Cortex-M Edge compile configuration, AOT compiler, quantizer support, tester, and pass manager. Legacy dim-order export remains the default. Explicit mode disables dim-order operators, converts Conv1d through the common transform, and uses the common channels-last dialect and region optimizer to form layout regions across supported convolution and pooling operations.
Lower channels-last anchors to fixed NHWC Cortex-M schemas and surviving structural boundaries to cortex_m::transpose. Constant padding inside a region selects pad_nhwc. Channel-broadcast add and multiply use explicit-layout quantizer checks and fixed NHWC runtime schemas, keeping these regions int8 instead of introducing float QDQ islands. Equal-shape add and multiply continue to use the layout-independent legacy schemas. Softmax remains outside automatic propagation so its dimension satisfies the Cortex-M last-dimension kernel contract.
Preserve complete operator metadata through common replacement, while explicitly requiring per-tensor activation and output qparams for tensors whose dimensions change. Per-channel activation or output axes are rejected from explicit regions until a backend remapping contract exists; per-channel weight metadata remains valid because weights are not permuted.
Add graph, planned-memory, and FVP coverage for regular, depthwise, transpose, pooling, padding, multi-op, channel-broadcast add/multiply, softmax-barrier, and Conv1d paths, including the public AOT flag. Planned-arena tests assert the expected targets before comparing memory. The channel-broadcast cases plan 1,600 bytes in both modes, eliminating the previous explicit-mode 2,304-byte float-intermediate plan.
Differential Revision: D116374086
cc @digantdesai @freddan80 @per @zingo @oscarandersson8218 @mansnils @Sebastian-Larsson @robell